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authorAndrey Smirnov <andrew.smirnov@gmail.com>2017-01-10 07:08:58 -0800
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-12 07:40:00 +0100
commit7a8d295cdf605e2bc01c201b9998917ebaf2f46f (patch)
tree3de2646c96321b2e104c9f312483e8a723d0a23a
parent390f49096e8b1dea250ab4439461211601e51f03 (diff)
downloadbarebox-7a8d295cdf605e2bc01c201b9998917ebaf2f46f.tar.gz
barebox-7a8d295cdf605e2bc01c201b9998917ebaf2f46f.tar.xz
i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtype
Add IMX_PLLV3_SYS_VF610 subtype to pllv3 code to be able to control and re-clock PLL1 and PLL2 on Vybrid SoC. This commit also introduces imx_clk_pllv3_locked which allows the user to create PLLv3 and specify how it should be polled for "locked" status (used in .set_rate callback) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/imx/clk-pllv3.c108
-rw-r--r--drivers/clk/imx/clk.h5
2 files changed, 113 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 29c0f1c70..dd924a46d 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -26,6 +26,8 @@
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
+#define SYS_VF610_PLL_OFFSET 0x10
+
#define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_BYPASS (0x1 << 16)
@@ -38,6 +40,8 @@ struct clk_pllv3 {
u32 div_mask;
u32 div_shift;
const char *parent;
+ void __iomem *lock_reg;
+ u32 lock_mask;
};
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
@@ -279,6 +283,88 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
.disable = clk_pllv3_disable,
};
+static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+
+ u32 mfn = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
+ u32 mfd = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
+ u32 div = (readl(pll->base) & pll->div_mask) ? 22 : 20;
+
+ return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
+static long clk_pllv3_sys_vf610_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long min_rate = parent_rate * 20;
+ unsigned long max_rate = 528000000;
+ u32 mfn, mfd = 1000000;
+ u64 temp64;
+
+ if (rate >= max_rate)
+ return max_rate;
+ else if (rate < min_rate)
+ rate = min_rate;
+
+ temp64 = (u64) (rate - 20 * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ return parent_rate * 20 + parent_rate / mfd * mfn;
+}
+
+static int clk_pllv3_sys_vf610_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long min_rate = parent_rate * 20;
+ unsigned long max_rate = 528000000;
+ u32 val;
+ u32 mfn, mfd = 1000000;
+ u64 temp64;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ val = readl(pll->base);
+
+ if (rate == max_rate) {
+ writel(0, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
+ val |= pll->div_mask;
+ writel(val, pll->base);
+
+ return 0;
+ } else {
+ val &= ~pll->div_mask;
+ }
+
+ temp64 = (u64) (rate - 20 * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ writel(val, pll->base);
+ writel(mfn, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
+ writel(mfd, pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
+
+ while (!(readl(pll->lock_reg) & pll->lock_mask))
+ ;
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_vf610_ops = {
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_sys_vf610_recalc_rate,
+ .round_rate = clk_pllv3_sys_vf610_round_rate,
+ .set_rate = clk_pllv3_sys_vf610_set_rate,
+};
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
u32 div_mask)
@@ -290,6 +376,9 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
pll = xzalloc(sizeof(*pll));
switch (type) {
+ case IMX_PLLV3_SYS_VF610:
+ ops = &clk_pllv3_sys_vf610_ops;
+ break;
case IMX_PLLV3_SYS:
ops = &clk_pllv3_sys_ops;
break;
@@ -327,3 +416,22 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
return &pll->clk;
}
+
+struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
+ const char *parent, void __iomem *base,
+ u32 div_mask, void __iomem *lock_reg, u32 lock_mask)
+{
+ struct clk *clk;
+ struct clk_pllv3 *pll;
+
+ clk = imx_clk_pllv3(type, name, parent, base, div_mask);
+ if (IS_ERR(clk))
+ return clk;
+
+ pll = to_clk_pllv3(clk);
+
+ pll->lock_reg = lock_reg;
+ pll->lock_mask = lock_mask;
+
+ return clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 970f65c7d..0b28fb24f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -78,6 +78,7 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent,
enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
IMX_PLLV3_SYS,
+ IMX_PLLV3_SYS_VF610,
IMX_PLLV3_USB,
IMX_PLLV3_USB_VF610,
IMX_PLLV3_AV,
@@ -89,6 +90,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
u32 div_mask);
+struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
+ const char *parent, void __iomem *base,
+ u32 div_mask, void __iomem *lock_reg, u32 lock_mask);
+
struct clk *imx_clk_pfd(const char *name, const char *parent,
void __iomem *reg, u8 idx);