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author | Lucas Stach <dev@lynxeye.de> | 2014-05-14 22:45:35 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-15 14:17:12 +0200 |
commit | 86a752954bf79cdc4f45057920934cc3dec67727 (patch) | |
tree | 2dadf2d70e970265e2c2b97f73f0d55c56a6bed5 | |
parent | a1f576c1e9ddef034117d40fe4c80d8f589325a0 (diff) | |
download | barebox-86a752954bf79cdc4f45057920934cc3dec67727.tar.gz barebox-86a752954bf79cdc4f45057920934cc3dec67727.tar.xz |
clk: tegra30: register i2c clocks
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/mach-tegra/include/mach/tegra30-car.h | 2 | ||||
-rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 16 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h index ce110602fc..286a2a613a 100644 --- a/arch/arm/mach-tegra/include/mach/tegra30-car.h +++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h @@ -25,6 +25,8 @@ #define CRC_CLK_SOURCE_MSEL_SRC_PLLM 2 #define CRC_CLK_SOURCE_MSEL_SRC_CLKM 3 +#define CRC_CLK_SOURCE_I2C4 0x3c4 + #define CRC_RST_DEV_V_SET 0x430 #define CRC_RST_DEV_V_MSELECT (1 << 3) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 9536288f89..3b508304c5 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -296,6 +296,22 @@ static void tegra30_periph_init(void) clks[TEGRA30_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4", mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, CRC_CLK_SOURCE_SDMMC4, TEGRA30_CLK_SDMMC4, 1); + + clks[TEGRA30_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1", + mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_I2C1, TEGRA30_CLK_I2C1, 1); + clks[TEGRA30_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2", + mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_I2C2, TEGRA30_CLK_I2C2, 1); + clks[TEGRA30_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3", + mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_I2C3, TEGRA30_CLK_I2C3, 1); + clks[TEGRA30_CLK_I2C4] = tegra_clk_register_periph_div16("i2c4", + mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_I2C4, TEGRA30_CLK_I2C4, 1); + clks[TEGRA30_CLK_I2C5] = tegra_clk_register_periph_div16("i2c5", + mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base, + CRC_CLK_SOURCE_DVC, TEGRA30_CLK_I2C5, 1); } static struct tegra_clk_init_table init_table[] = { |