diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-04 15:24:27 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-04 15:24:57 +0200 |
| commit | 94de405d8f56aa66283d7497c707380762440601 (patch) | |
| tree | ef6618eb4604ff3cbc69af90d9ec6feb4db5e771 | |
| parent | ddba7e606bc7a6b3715d6c123c0a9b708a6b8776 (diff) | |
| parent | d4edd480b2ab0754361b142e307796405310d34b (diff) | |
| download | barebox-94de405d8f56aa66283d7497c707380762440601.tar.gz barebox-94de405d8f56aa66283d7497c707380762440601.tar.xz | |
Merge branch 'for-next/imx-clk'
106 files changed, 4479 insertions, 3093 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7b7b0585ae..8278c82e3a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -40,6 +40,8 @@ config ARCH_IMX bool "Freescale iMX-based" select GENERIC_GPIO select GPIOLIB + select COMMON_CLK + select CLKDEV_LOOKUP config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index 4dc5501f44..bf3cbc375a 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -93,21 +93,21 @@ static void imx25_usb_init(void) unsigned int tmp; /* Host 1 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600); tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; tmp |= MX35_H1_USBTE_BIT; tmp |= MX35_H1_IPPUE_DOWN_BIT; - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x584); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584); tmp |= 3 << 30; - writel(tmp, IMX_OTG_BASE + 0x584); + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584); /* Set to Host mode */ - tmp = readl(IMX_OTG_BASE + 0x5a8); - writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8); + writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8); } #endif @@ -119,7 +119,7 @@ static struct fsl_usb2_platform_data usb_pdata = { static int eukrea_cpuimx25_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024); + arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, 64 * 1024 * 1024); return 0; } @@ -219,12 +219,12 @@ static int eukrea_cpuimx25_devices_init(void) #ifdef CONFIG_USB imx25_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); #endif #ifdef CONFIG_USB_GADGET /* Workaround ENGcm09152 */ - writel(readl(IMX_OTG_BASE + 0x608) | (1 << 23), IMX_OTG_BASE + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200, + writel(readl(MX25_USB_OTG_BASE_ADDR + 0x608) | (1 << 23), MX25_USB_OTG_BASE_ADDR + 0x608); + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX25_USB_OTG_BASE_ADDR, 0x200, IORESOURCE_MEM, &usb_pdata); #endif @@ -253,13 +253,13 @@ void __bare_init nand_boot(void) static int eukrea_cpuimx25_core_init(void) { /* enable UART1, FEC, SDHC, USB & I2C clock */ - writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23) + writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23) | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28), - IMX_CCM_BASE + CCM_CGCR0); - writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15) - | (1 << 13), IMX_CCM_BASE + CCM_CGCR1); - writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14), - IMX_CCM_BASE + CCM_CGCR2); + MX25_CCM_BASE_ADDR + CCM_CGCR0); + writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15) + | (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1); + writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14), + MX25_CCM_BASE_ADDR + CCM_CGCR2); return 0; } diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 44019e5356..cd80b251be 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -57,20 +57,20 @@ void __bare_init __naked reset(void) common_reset(); /* restart the MPLL and wait until it's stable */ - writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), - IMX_CCM_BASE + CCM_CCTL); - while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; + writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27), + MX25_CCM_BASE_ADDR + CCM_CCTL); + while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {}; /* Configure dividers and ARM clock source * ARM @ 400 MHz * AHB @ 133 MHz */ - writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); /* Enable UART1 / FEC / */ -/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0); - writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1); - writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/ +/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0); + writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1); + writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2);*/ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -118,10 +118,10 @@ void __bare_init __naked reset(void) writel(0x1, 0xb8003000); /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(IMX_CCM_BASE + CCM_PCDR2); + r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2); r &= ~0xf; r |= 0x1; - writel(r, IMX_CCM_BASE + CCM_PCDR2); + writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -137,22 +137,22 @@ void __bare_init __naked reset(void) writel(0x0029572B, ESDCFG0); writel(0x92210000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x400); + writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400); writel(0xA2210000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0); - writeb(0xda, IMX_SDRAM_CS0); + writeb(0xda, MX25_CSD0_BASE_ADDR); + writeb(0xda, MX25_CSD0_BASE_ADDR); writel(0xB2210000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x33); - writeb(0xda, IMX_SDRAM_CS0 + 0x1000000); + writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33); + writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); writel(0x82216080, ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX25_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index 068cc11d3e..cff4f77985 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -37,6 +37,7 @@ #include <io.h> #include <mach/imx-nand.h> #include <mach/imx-pll.h> +#include <mach/weim.h> #include <mach/imxfb.h> #include <ns16550.h> #include <asm/mmu.h> @@ -223,13 +224,13 @@ device_initcall(eukrea_cpuimx27_devices_init); static int eukrea_cpuimx27_console_init(void) { #ifdef CONFIG_DRIVER_SERIAL_IMX - imx_add_uart((void *)IMX_UART1_BASE, DEVICE_ID_DYNAMIC); + imx27_add_uart0(); #endif /* configure 8 bit UART on cs3 */ FMCR &= ~0x2; imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000); #ifdef CONFIG_DRIVER_SERIAL_NS16550 - add_ns16550_device(DEVICE_ID_DYNAMIC, IMX_CS3_BASE + QUART_OFFSET, 0xf, + add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf, IORESOURCE_MEM_16BIT, &quad_uart_serial_plat); #endif return 0; diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index af4deeb53b..1983d480f9 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -111,8 +111,8 @@ reset: #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 3c7fb6992e..53cc428c84 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -97,21 +97,21 @@ static void imx35_usb_init(void) unsigned int tmp; /* Host 1 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x600); tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; tmp |= MX35_H1_USBTE_BIT | MX35_H1_PM_BIT | MX35_H1_TLL_BIT ; tmp |= MX35_H1_IPPUE_DOWN_BIT; - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x584); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x584); tmp |= 3 << 30; - writel(tmp, IMX_OTG_BASE + 0x584); + writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x584); /* Set to Host mode */ - tmp = readl(IMX_OTG_BASE + 0x5a8); - writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x5a8); + writel(tmp | 0x3, MX35_USB_OTG_BASE_ADDR + 0x5a8); } #endif @@ -124,7 +124,7 @@ static struct fsl_usb2_platform_data usb_pdata = { static int eukrea_cpuimx35_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024); + arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024); return 0; } @@ -216,13 +216,13 @@ static int eukrea_cpuimx35_devices_init(void) #ifdef CONFIG_USB imx35_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX35_USB_HS_BASE_ADDR, NULL); #endif #ifdef CONFIG_USB_GADGET /* Workaround ENGcm09152 */ - tmp = readl(IMX_OTG_BASE + 0x608); - writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200, + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608); + writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608); + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200, IORESOURCE_MEM, &usb_pdata); #endif armlinux_set_bootparams((void *)0x80000100); @@ -246,70 +246,70 @@ static int eukrea_cpuimx35_core_init(void) u32 reg; /* enable clock for I2C1, SDHC1, USB and FEC */ - reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); reg |= 0x3 << CCM_CGR1_FEC_SHIFT; reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT; reg |= 0x3 << CCM_CGR1_I2C1_SHIFT, - reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); - reg = readl(IMX_CCM_BASE + CCM_CGR2); + reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2); reg |= 0x3 << CCM_CGR2_USB_SHIFT; - reg = writel(reg, IMX_CCM_BASE + CCM_CGR2); + reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, IMX_AIPS1_BASE); - writel(0x77777777, IMX_AIPS1_BASE + 0x4); - writel(0x77777777, IMX_AIPS2_BASE); - writel(0x77777777, IMX_AIPS2_BASE + 0x4); + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ - writel(0x0, IMX_AIPS1_BASE + 0x40); - writel(0x0, IMX_AIPS1_BASE + 0x44); - writel(0x0, IMX_AIPS1_BASE + 0x48); - writel(0x0, IMX_AIPS1_BASE + 0x4C); - reg = readl(IMX_AIPS1_BASE + 0x50); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS1_BASE + 0x50); + writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - writel(0x0, IMX_AIPS2_BASE + 0x40); - writel(0x0, IMX_AIPS2_BASE + 0x44); - writel(0x0, IMX_AIPS2_BASE + 0x48); - writel(0x0, IMX_AIPS2_BASE + 0x4C); - reg = readl(IMX_AIPS2_BASE + 0x50); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS2_BASE + 0x50); + writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ /* SGPCR - always park on last master */ - writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ - writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ - writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ - writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ - writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ /* MGPCR - restore default values */ - writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ - writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ - writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ - writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ - writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ - writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ /* * M3IF Control Register (M3IFCTL) @@ -324,7 +324,7 @@ static int eukrea_cpuimx35_core_init(void) * ------------ * 0x00000040 */ - writel(0x40, IMX_M3IF_BASE); + writel(0x40, MX35_M3IF_BASE_ADDR); return 0; } @@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 2721cf2ff0..ea932f773e 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -41,10 +41,10 @@ static void __bare_init __naked insdram(void) uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(IMX_CCM_BASE + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, IMX_CCM_BASE + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ r = STACK_BASE + STACK_SIZE - 12; @@ -59,7 +59,7 @@ static void __bare_init __naked insdram(void) void __bare_init __naked reset(void) { uint32_t r, s; - unsigned long ccm_base = IMX_CCM_BASE; + unsigned long ccm_base = MX35_CCM_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -128,9 +128,9 @@ void __bare_init __naked reset(void) r |= 0x03000000; writel(r, ccm_base + CCM_CGR2); - r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; - writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -146,22 +146,22 @@ void __bare_init __naked reset(void) writel(0x0009572B, ESDCFG0); writel(0x92220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x400); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); writel(0xA2220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0); - writeb(0xda, IMX_SDRAM_CS0); + writeb(0xda, MX35_CSD0_BASE_ADDR); + writeb(0xda, MX35_CSD0_BASE_ADDR); writel(0xB2220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x33); - writeb(0xda, IMX_SDRAM_CS0 + 0x2000000); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); writel(0x82228080, ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX35_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c index 331c2e8c39..a0ae938809 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -119,18 +119,18 @@ static void imx25_usb_init(void) unsigned int tmp; /* Host 2 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600); tmp &= ~(3 << 21); tmp |= (2 << 21) | (1 << 4) | (1 << 5); - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x584); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584); tmp |= 3 << 30; - writel(tmp, IMX_OTG_BASE + 0x584); + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584); /* Set to Host mode */ - tmp = readl(IMX_OTG_BASE + 0x5a8); - writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8); + writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8); } #endif @@ -195,7 +195,7 @@ static int imx25_mem_init(void) #else #error "Unsupported SDRAM type" #endif - arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM_SIZE); + arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, SDRAM_SIZE); add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); return 0; @@ -209,13 +209,13 @@ static int imx25_devices_init(void) * the CPLD has to be initialized. */ imx25_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); #endif imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); @@ -298,7 +298,7 @@ void __bare_init nand_boot(void) static int imx25_core_setup(void) { - writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2); return 0; } diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index 14259f4d08..f911f9d7f8 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -47,7 +47,7 @@ CCM_PDR0_W: .word 0x00801000 MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word IMX_CCM_BASE +CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR .globl reset reset: @@ -66,10 +66,10 @@ reset: str r1, [r0, #MX25_CCM_MCR] /* enable all the clocks */ - writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0) - writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1) - writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2) - writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR) + writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0) + writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1) + writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2) + writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) /* Skip SDRAM initialization if we run from RAM */ cmp pc, #0x80000000 @@ -87,7 +87,7 @@ reset: mov r12, #0x00 mov r2, #0x1 /* mDDR */ - mov r1, #IMX_SDRAM_CS0 + mov r1, #MX25_CSD0_BASE_ADDR bl setup_sdram_bank // cmp r3, #0x0 // orreq r12, r12, #1 @@ -100,8 +100,8 @@ reset: #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + ldr r0, =MX25_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX25_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 @@ -148,7 +148,7 @@ setup_sdram_bank: tst r2, #0x1 ldreq r3, [r4, #0x0] ldrne r3, [r4, #0x4] - cmp r1, #IMX_SDRAM_CS1 + cmp r1, #MX25_CSD1_BASE_ADDR strlo r3, [r0, #0x4] strhs r3, [r0, #0xC] @@ -162,7 +162,7 @@ setup_sdram_bank: tst r2, #0x1 bne skip_set_mode - cmp r1, #IMX_SDRAM_CS1 + cmp r1, #MX25_CSD1_BASE_ADDR ldr r3, ESDCTL_0xB2220000 strlo r3, [r0, #0x0] strhs r3, [r0, #0x8] @@ -184,7 +184,7 @@ setup_sdram_bank: strb r3, [r1, r4] skip_set_mode: - cmp r1, #IMX_SDRAM_CS1 + cmp r1, #MX25_CSD1_BASE_ADDR ldr r3, ESDCTL_0xA2220000 strlo r3, [r0, #0x0] strhs r3, [r0, #0x8] @@ -208,7 +208,7 @@ skip_set_mode: ldrne r4, [r4, #0x4] strb r3, [r1, r4] - cmp r1, #IMX_SDRAM_CS1 + cmp r1, #MX25_CSD1_BASE_ADDR ldr r3, ESDCTL_0x82226080 strlo r3, [r0, #0x0] strhs r3, [r0, #0x8] @@ -243,5 +243,5 @@ ESDCTL_0x82226080: .word 0x82216080 ESDCTL_CONFIG: .word 0x007FFC3F .word 0x007FFC3F ESDCTL_DELAY5: .word 0x00F49F00 -ESDCTL_BASE_W: .word IMX_ESD_BASE +ESDCTL_BASE_W: .word MX25_ESDCTL_BASE_ADDR diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c index 199841f468..9a01424402 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -39,6 +39,7 @@ #include <generated/mach-types.h> #include <mach/gpio.h> +#include <mach/weim.h> #include <mach/imx-nand.h> #include <mach/imx-regs.h> #include <mach/iomux-mx35.h> @@ -128,8 +129,8 @@ static void set_board_rev(int rev) static int f3s_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024); - arm_add_mem_device("ram1", IMX_SDRAM_CS1, 128 * 1024 * 1024); + arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024); + arm_add_mem_device("ram1", MX35_CSD1_BASE_ADDR, 128 * 1024 * 1024); return 0; } @@ -140,11 +141,9 @@ static int f3s_devices_init(void) uint32_t reg; /* CS0: Nor Flash */ - writel(0x0000cf03, CSCR_U(0)); - writel(0x10000d03, CSCR_L(0)); - writel(0x00720900, CSCR_A(0)); + imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - reg = readl(IMX_CCM_BASE + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -155,7 +154,7 @@ static int f3s_devices_init(void) * This platform supports NOR and NAND */ imx35_add_nand(&nand_info); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 64 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0); switch ((reg >> 25) & 0x3) { case 0x01: /* NAND is the source */ @@ -178,7 +177,7 @@ static int f3s_devices_init(void) imx35_add_i2c0(NULL); imx35_add_fec(&fec_info); - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS5_BASE, IMX_CS5_RANGE, + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE, IORESOURCE_MEM, NULL); imx35_add_mmc0(NULL); @@ -278,71 +277,70 @@ static int f3s_core_init(void) { u32 reg; - writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */ - writel(0x22252521, CSCR_L(5)); - writel(0x22220A00, CSCR_A(5)); + /* CS5: smc9117 */ + imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); /* enable clock for I2C1 and FEC */ - reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); reg |= 0x3 << CCM_CGR1_FEC_SHIFT; reg |= 0x3 << CCM_CGR1_I2C1_SHIFT; - reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); + reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, IMX_AIPS1_BASE); - writel(0x77777777, IMX_AIPS1_BASE + 0x4); - writel(0x77777777, IMX_AIPS2_BASE); - writel(0x77777777, IMX_AIPS2_BASE + 0x4); + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ - writel(0x0, IMX_AIPS1_BASE + 0x40); - writel(0x0, IMX_AIPS1_BASE + 0x44); - writel(0x0, IMX_AIPS1_BASE + 0x48); - writel(0x0, IMX_AIPS1_BASE + 0x4C); - reg = readl(IMX_AIPS1_BASE + 0x50); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS1_BASE + 0x50); + writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - writel(0x0, IMX_AIPS2_BASE + 0x40); - writel(0x0, IMX_AIPS2_BASE + 0x44); - writel(0x0, IMX_AIPS2_BASE + 0x48); - writel(0x0, IMX_AIPS2_BASE + 0x4C); - reg = readl(IMX_AIPS2_BASE + 0x50); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS2_BASE + 0x50); + writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ /* SGPCR - always park on last master */ - writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ - writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ - writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ - writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ - writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ /* MGPCR - restore default values */ - writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ - writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ - writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ - writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ - writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ - writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ return 0; } diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index 0718fc610c..e5d0feb18f 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -54,7 +54,7 @@ CCM_PDR0_W: .word 0x00001000 MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word IMX_CCM_BASE +CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR .globl reset reset: @@ -157,8 +157,8 @@ reset: #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */ + ldr r0, =MX35_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX35_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c index d5f2291ff3..933a9cd057 100644 --- a/arch/arm/boards/guf-cupid/board.c +++ b/arch/arm/boards/guf-cupid/board.c @@ -36,6 +36,7 @@ #include <fec.h> #include <fb.h> #include <asm/mmu.h> +#include <mach/weim.h> #include <mach/imx-ipu-fb.h> #include <mach/imx-pll.h> #include <mach/iomux-mx35.h> @@ -95,7 +96,7 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { static int cupid_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024); + arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024); return 0; } @@ -116,7 +117,7 @@ static int cupid_devices_init(void) gpio_direction_output(GPIO_LCD_ENABLE, 0); gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); - reg = readl(IMX_CCM_BASE + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -250,60 +251,59 @@ static int cupid_core_setup(void) * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, IMX_AIPS1_BASE); - writel(0x77777777, IMX_AIPS1_BASE + 0x4); - writel(0x77777777, IMX_AIPS2_BASE); - writel(0x77777777, IMX_AIPS2_BASE + 0x4); + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ - writel(0x0, IMX_AIPS1_BASE + 0x40); - writel(0x0, IMX_AIPS1_BASE + 0x44); - writel(0x0, IMX_AIPS1_BASE + 0x48); - writel(0x0, IMX_AIPS1_BASE + 0x4C); - tmp = readl(IMX_AIPS1_BASE + 0x50); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); tmp &= 0x00FFFFFF; - writel(tmp, IMX_AIPS1_BASE + 0x50); + writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - writel(0x0, IMX_AIPS2_BASE + 0x40); - writel(0x0, IMX_AIPS2_BASE + 0x44); - writel(0x0, IMX_AIPS2_BASE + 0x48); - writel(0x0, IMX_AIPS2_BASE + 0x4C); - tmp = readl(IMX_AIPS2_BASE + 0x50); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); tmp &= 0x00FFFFFF; - writel(tmp, IMX_AIPS2_BASE + 0x50); + writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ /* SGPCR - always park on last master */ - writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ - writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ - writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ - writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ - writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ /* MGPCR - restore default values */ - writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ - writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ - writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ - writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ - writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ - writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */ - writel(0x444A4541, CSCR_L(0)); - writel(0x44443302, CSCR_A(0)); + /* CS0: NOR Flash */ + imx35_setup_weimcs(0, 0x0000DCF6, 0x444A4541, 0x44443302); /* * M3IF Control Register (M3IFCTL) @@ -318,7 +318,7 @@ static int cupid_core_setup(void) * ------------ * 0x00000040 */ - writel(0x40, IMX_M3IF_BASE); + writel(0x40, MX35_M3IF_BASE_ADDR); return 0; } @@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 677ff95626..d451fd9393 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -48,10 +48,10 @@ static void __bare_init __naked insdram(void) uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(IMX_CCM_BASE + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, IMX_CCM_BASE + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ r = STACK_BASE + STACK_SIZE - 12; @@ -66,7 +66,7 @@ static void __bare_init __naked insdram(void) static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr) { volatile int loop; - void *r9 = (void *)IMX_SDRAM_CS0; + void *r9 = (void *)MX35_CSD0_BASE_ADDR; u32 r11 = 0xda; /* dummy constant */ u32 r1, r0; @@ -249,7 +249,7 @@ void __bare_init __naked reset(void) #define WDOG_WMCR 0x8 /* silence reset WDOG */ - writew(0, IMX_WDOG_BASE + WDOG_WMCR); + writew(0, MX35_WDOG_BASE_ADDR + WDOG_WMCR); /* Skip SDRAM initialization if we run from RAM */ r0 = get_pc(); @@ -299,27 +299,27 @@ void __bare_init __naked reset(void) /* Configure clocks */ /* setup cpu/bus clocks */ - writel(0x003f4208, IMX_CCM_BASE + CCM_CCMR); + writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR); /* configure MPLL */ - writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); /* configure PPLL */ - writel(PPCTL_PARAM_300, IMX_CCM_BASE + CCM_PPCTL); + writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL); /* configure core dividers */ r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2); - writel(r0, IMX_CCM_BASE + CCM_PDR0); + writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0); /* configure clock-gates */ - r0 = readl(IMX_CCM_BASE + CCM_CGR0); + r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0); r0 |= 0x00300000; - writel(r0, IMX_CCM_BASE + CCM_CGR0); + writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0); - r0 = readl(IMX_CCM_BASE + CCM_CGR1); + r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); r0 |= 0x00000c03; - writel(r0, IMX_CCM_BASE + CCM_CGR1); + writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1); /* Configure SDRAM */ /* Try 32-Bit 256 MB DDR memory */ @@ -329,10 +329,10 @@ void __bare_init __naked reset(void) #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r0 = get_pc(); - if (r0 < IMX_NFC_BASE || r0 > IMX_NFC_BASE + 0x800) + if (r0 < MX35_NFC_BASE_ADDR || r0 > MX35_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX35_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 7f25a1122e..7adee929b0 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -115,21 +115,21 @@ static void neso_usbh_init(void) { uint32_t temp; - temp = readl(IMX_OTG_BASE + 0x600); + temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600); temp &= ~((3 << 21) | 1); temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11); - writel(temp, IMX_OTG_BASE + 0x600); + writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600); - temp = readl(IMX_OTG_BASE + 0x584); + temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584); temp &= ~(3 << 30); temp |= 2 << 30; - writel(temp, IMX_OTG_BASE + 0x584); + writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584); mdelay(10); gpio_set_value(USBH2_PHY_CS_GPIO, 0); mdelay(10); - ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1); + ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); } #endif @@ -276,7 +276,7 @@ static int neso_devices_init(void) #ifdef CONFIG_USB neso_usbh_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); #endif imx27_add_fec(&fec_info); diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 2d57990773..52fe6cffa8 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -101,10 +101,10 @@ void __bare_init __naked reset(void) #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX27_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c index 1aecf18afe..22406beb5a 100644 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -27,6 +27,7 @@ #include <asm/barebox-arm.h> #include <io.h> #include <mach/gpio.h> +#include <mach/weim.h> #include <partition.h> #include <fs.h> #include <fcntl.h> @@ -83,26 +84,16 @@ static int imx21ads_timing_init(void) /* Configure External Interface Module */ /* CS0: burst flash */ - CS0U = 0x00003E00; - CS0L = 0x00000E01; + imx21_setup_eimcs(0, 0x00003E00, 0x00000E01); /* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */ - CS1U = 0x00002000; - CS1L = 0x11118501; - - /* CS2: disable (not available, since CSD0 in use) */ - CS2U = 0x0; - CS2L = 0x0; - - /* CS3: disable */ - CS3U = 0x0; - CS3L = 0x0; - /* CS4: disable */ - CS4U = 0x0; - CS4L = 0x0; - /* CS5: disable */ - CS5U = 0x0; - CS5L = 0x0; + imx21_setup_eimcs(1, 0x00002000, 0x11118501); + + /* CS2-CS5: disable */ + imx21_setup_eimcs(2, 0x0, 0x0); + imx21_setup_eimcs(3, 0x0, 0x0); + imx21_setup_eimcs(4, 0x0, 0x0); + imx21_setup_eimcs(5, 0x0, 0x0); temp = PCDR0; temp &= ~0xF000; @@ -163,9 +154,11 @@ static int mx21ads_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC8000000, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR, + 32 * 1024 * 1024, 0); imx21_add_nand(&nand_info); - add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE, 0x1000, + add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, + MX21_CS1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); imx21_add_fb(&imx_fb_data); diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S index 8181866417..0cb8aaf950 100644 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -120,8 +120,8 @@ reset: #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */ + ldr r0, =MX21_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX21_NFC_BASE_ADDR + 0x800 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c index 0a9074d364..22c6e40f9f 100644 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -23,6 +23,7 @@ #include <io.h> #include <fec.h> #include <mach/gpio.h> +#include <mach/weim.h> #include <partition.h> #include <fs.h> #include <fcntl.h> @@ -54,10 +55,10 @@ static int imx27ads_timing_init(void) imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900); /* Select FEC data through data path */ - writew(0x0020, IMX_CS4_BASE + 0x10); + writew(0x0020, MX27_CS4_BASE_ADDR + 0x10); /* Enable CPLD FEC data path */ - writew(0x0010, IMX_CS4_BASE + 0x14); + writew(0x0010, MX27_CS4_BASE_ADDR + 0x14); return 0; } diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index 79d942df64..5413ea801c 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -52,8 +52,8 @@ struct imx_nand_platform_data nand_info = { static int tx25_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 32 * 1024 * 1024); - arm_add_mem_device("ram0", IMX_SDRAM_CS1, 32 * 1024 * 1024); + arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, 32 * 1024 * 1024); + arm_add_mem_device("ram0", MX25_CSD1_BASE_ADDR, 32 * 1024 * 1024); add_mem_device("ram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); @@ -108,7 +108,7 @@ static int tx25_devices_init(void) imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 1da6b4d135..3192abdeb6 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -122,12 +122,12 @@ void __bare_init __naked reset(void) writel(0x1, 0xb8003000); /* configure ARM clk */ - writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); /* enable all the clocks */ - writel(0x1fffffff, IMX_CCM_BASE + CCM_CGCR0); - writel(0xffffffff, IMX_CCM_BASE + CCM_CGCR1); - writel(0x000fdfff, IMX_CCM_BASE + CCM_CGCR2); + writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0); + writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1); + writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -135,7 +135,7 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* set to 3.3v SDRAM */ - writel(0x800, IMX_IOMUXC_BASE + 0x454); + writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454); writel(ESDMISC_RST, ESDMISC); @@ -153,10 +153,10 @@ void __bare_init __naked reset(void) #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX25_NFC_BASE_ADDR || r > MX25_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX25_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S index 804af7222b..a6747c2482 100644 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ b/arch/arm/boards/pcm037/lowlevel_init.S @@ -46,13 +46,12 @@ reset: common_reset r0 - writel(IPU_CONF_DI_EN, IPU_CONF) - writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR) + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR) DELAY 0x40000 - writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR) - writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR) + writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR) + writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR) writel(PDR0_CSI_PODF(0xff1) | \ PDR0_PER_PODF(7) | \ @@ -61,10 +60,10 @@ reset: PDR0_IPG_PODF(1) | \ PDR0_MAX_PODF(3) | \ PDR0_MCU_PODF(0), \ - IMX_CCM_BASE + CCM_PDR0) + MX31_CCM_BASE_ADDR + CCM_PDR0) - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL) + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL) /* Configure IOMUXC * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) @@ -100,15 +99,15 @@ clear_iomux: writel(0x00000004, ESDMISC) writel(0x006ac73a, ESDCFG0) writel(0x90100000 | ROWS0, ESDCTL0) - writel(0x12344321, IMX_SDRAM_CS0 + 0xf00) + writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) writel(0xa0100000 | ROWS0, ESDCTL0) - writel(0x12344321, IMX_SDRAM_CS0) - writel(0x12344321, IMX_SDRAM_CS0) + writel(0x12344321, MX31_CSD0_BASE_ADDR) + writel(0x12344321, MX31_CSD0_BASE_ADDR) writel(0xb0100000 | ROWS0, ESDCTL0) - writeb(0xda, IMX_SDRAM_CS0 + 0x33) - writeb(0xff, IMX_SDRAM_CS0 + 0x01000000) + writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) + writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) writel(0x80226080 | ROWS0, ESDCTL0) - writel(0xDEADBEEF, IMX_SDRAM_CS0) + writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) writel(0x0000000c, ESDMISC) #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE @@ -119,23 +118,23 @@ clear_iomux: #endif writel(0x006ac73a, ESDCFG1) writel(0x90100000 | ROWS1, ESDCTL1) - writel(0x12344321, IMX_SDRAM_CS1 + 0xf00) + writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) writel(0xa0100000 | ROWS1, ESDCTL1) - writel(0x12344321, IMX_SDRAM_CS1) - writel(0x12344321, IMX_SDRAM_CS1) + writel(0x12344321, MX31_CSD1_BASE_ADDR) + writel(0x12344321, MX31_CSD1_BASE_ADDR) writel(0xb0100000 | ROWS1, ESDCTL1) - writeb(0xda, IMX_SDRAM_CS1 + 0x33) - writeb(0xff, IMX_SDRAM_CS1 + 0x01000000) + writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) + writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) writel(0x80226080 | ROWS1, ESDCTL1) - writel(0xDEADBEEF, IMX_SDRAM_CS1) + writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) writel(0x0000000c, ESDMISC) #endif #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 28d3b135f4..1a1688d053 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -29,6 +29,7 @@ #include <asm/armlinux.h> #include <asm-generic/sections.h> #include <mach/gpio.h> +#include <mach/weim.h> #include <io.h> #include <asm/mmu.h> #include <partition.h> @@ -66,15 +67,15 @@ static void pcm037_usb_init(void) writel(tmp, 0x53f80000); /* Host 1 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); tmp &= ~((3 << 21) | 1); tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x184); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184); tmp &= ~(3 << 30); tmp |= 2 << 30; - writel(tmp, IMX_OTG_BASE + 0x184); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184); imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0); imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1); @@ -90,10 +91,10 @@ static void pcm037_usb_init(void) imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP); mdelay(50); - ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1); + ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1); /* Host 2 */ - tmp = readl(IOMUXC_BASE + 0x8); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8); tmp |= 1 << 11; writel(tmp, IOMUXC_BASE + 0x8); @@ -124,31 +125,31 @@ static void pcm037_usb_init(void) imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); tmp &= ~((3 << 21) | 1); tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x584); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); tmp &= ~(3 << 30); tmp |= 2 << 30; - writel(tmp, IMX_OTG_BASE + 0x584); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); mdelay(50); - ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1); + ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); /* Set to Host mode */ - tmp = readl(IMX_OTG_BASE + 0x1a8); - writel(tmp | 0x3, IMX_OTG_BASE + 0x1a8); + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); + writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); } #endif static int pcm037_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024); + arm_add_mem_device("ram0", MX31_CSD0_BASE_ADDR, SDRAM0 * 1024 * 1024); #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE - arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024); + arm_add_mem_device("ram1", MX31_CSD1_BASE_ADDR, SDRAM1 * 1024 * 1024); #endif return 0; @@ -165,27 +166,20 @@ postmmu_initcall(pcm037_mmu_init); static int imx31_devices_init(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; - - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; - - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; - - __REG(CSCR_U(5)) = 0x0000DCF6; /* CS5: SJA1000 */ - __REG(CSCR_L(5)) = 0x444A0301; - __REG(CSCR_A(5)) = 0x44443302; + /* CS0: Nor Flash */ + imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); + /* CS1: Network Controller */ + imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302); + /* CS4: SRAM */ + imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00); + /* CS5: SJA1000 */ + imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); /* * Up to 32MiB NOR type flash, connected to * CS line 0, data width is 16 bit */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); /* * Create partitions that should be @@ -200,7 +194,7 @@ static int imx31_devices_init(void) * up to 2MiB static RAM type memory, connected * to CS4, data width is 16 bit */ - add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */ + add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */ IORESOURCE_MEM_WRITEABLE); imx31_add_nand(&nand_info); @@ -209,13 +203,13 @@ static int imx31_devices_init(void) * connected to CS line 1 and interrupt line * GPIO3, data width is 16 bit */ - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE, - IMX_CS1_RANGE, IORESOURCE_MEM, NULL); + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR, + MX31_CS1_SIZE, IORESOURCE_MEM, NULL); #ifdef CONFIG_USB pcm037_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL); #endif armlinux_set_bootparams((void *)0x80000100); diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index cc70777e74..7ecff3afa8 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -106,10 +106,10 @@ void __bare_init __naked reset(void) #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX27_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index a51825b795..58b1ec9ef4 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -31,6 +31,7 @@ #include <io.h> #include <mach/imx-nand.h> #include <mach/imx-pll.h> +#include <mach/weim.h> #include <mach/imxfb.h> #include <i2c/i2c.h> #include <mach/spi.h> diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index 5834311aad..a6b6c83efa 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -18,6 +18,7 @@ #include <platform_ide.h> #include <mach/imx-regs.h> #include <mach/iomux-mx27.h> +#include <mach/weim.h> #include <mach/gpio.h> #include <mach/devices-imx27.h> #include <usb/ulpi.h> @@ -31,28 +32,28 @@ static void pcm970_usbh2_init(void) { uint32_t temp; - temp = readl(IMX_OTG_BASE + 0x600); + temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600); temp &= ~((3 << 21) | 1); temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(temp, IMX_OTG_BASE + 0x600); + writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600); - temp = readl(IMX_OTG_BASE + 0x584); + temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584); temp &= ~(3 << 30); temp |= 2 << 30; - writel(temp, IMX_OTG_BASE + 0x584); + writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584); mdelay(10); - if (!ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1)) - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + if (!ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1)) + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); } #endif #ifdef CONFIG_DISK_INTF_PLATFORM_IDE static struct resource pcm970_ide_resources[] = { { - .start = IMX_PCMCIA_MEM_BASE, - .end = IMX_PCMCIA_MEM_BASE + SZ_1K - 1, + .start = MX27_PCMCIA_MEM_BASE_ADDR, + .end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1, .flags = IORESOURCE_MEM, }, }; diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index 8c52b8c7b0..4516e9f017 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -46,10 +46,10 @@ static void __bare_init __naked insdram(void) uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(IMX_CCM_BASE + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, IMX_CCM_BASE + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ r = STACK_BASE + STACK_SIZE - 12; @@ -64,8 +64,8 @@ static void __bare_init __naked insdram(void) void __bare_init __naked reset(void) { uint32_t r, s; - unsigned long ccm_base = IMX_CCM_BASE; - unsigned long iomuxc_base = IMX_IOMUXC_BASE; + unsigned long ccm_base = MX35_CCM_BASE_ADDR; + unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -118,7 +118,7 @@ void __bare_init __naked reset(void) writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); /* Check silicon revision and use 532MHz if >=2.1 */ - r = readl(IMX_IIM_BASE + 0x24); + r = readl(MX35_IIM_BASE_ADDR + 0x24); if (r >= IMX35_CHIP_REVISION_2_1) writel(CCM_PDR0_532, ccm_base + CCM_PDR0); else @@ -133,9 +133,9 @@ void __bare_init __naked reset(void) r |= 0x00000003; writel(r, ccm_base + CCM_CGR1); - r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; - writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -161,7 +161,7 @@ void __bare_init __naked reset(void) /* select Precharge-All mode */ writel(0x92220000, ESDCTL0); /* Precharge-All */ - writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Load-Mode-Register mode */ writel(0xB8001000, ESDCTL0); @@ -177,13 +177,13 @@ void __bare_init __naked reset(void) /* select Precharge-All mode */ writel(0x92220000, ESDCTL0); /* Precharge-All */ - writel(0x12345678, IMX_SDRAM_CS0 + 0x400); + writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Manual-Refresh mode */ writel(0xA2220000, ESDCTL0); /* Manual-Refresh 2 times */ - writel(0x87654321, IMX_SDRAM_CS0); - writel(0x87654321, IMX_SDRAM_CS0); + writel(0x87654321, MX35_CSD0_BASE_ADDR); + writel(0x87654321, MX35_CSD0_BASE_ADDR); /* select Load-Mode-Register mode */ writel(0xB2220000, ESDCTL0); @@ -208,10 +208,10 @@ void __bare_init __naked reset(void) #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX35_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c index 3170161cfd..09bc96af78 100644 --- a/arch/arm/boards/pcm043/pcm043.c +++ b/arch/arm/boards/pcm043/pcm043.c @@ -38,6 +38,7 @@ #include <fb.h> #include <led.h> #include <asm/mmu.h> +#include <mach/weim.h> #include <mach/imx-ipu-fb.h> #include <mach/imx-pll.h> #include <mach/iomux-mx35.h> @@ -93,13 +94,13 @@ static struct fb_videomode pcm043_fb_mode[] = { static struct imx_ipu_fb_platform_data ipu_fb_data = { .mode = pcm043_fb_mode, .num_modes = ARRAY_SIZE(pcm043_fb_mode), - .framebuffer_ovl = (void *) (IMX_SDRAM_CS0 + SZ_128M - SZ_1M), + .framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M), .bpp = 16, }; static int pcm043_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, SZ_128M); + arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, SZ_128M); return 0; } @@ -122,13 +123,11 @@ static int imx35_devices_init(void) uint32_t reg; /* CS0: Nor Flash */ - writel(0x22C0CF00, CSCR_U(0)); - writel(0x75000D01, CSCR_L(0)); - writel(0x00000900, CSCR_A(0)); + imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900); led_gpio_register(&led0); - reg = readl(IMX_CCM_BASE + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -144,7 +143,7 @@ static int imx35_devices_init(void) * Up to 32MiB NOR type flash, connected to * CS line 0, data width is 16 bit */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */ switch ( (reg >> 25) & 0x3) { @@ -224,56 +223,56 @@ static int pcm043_core_setup(void) * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, IMX_AIPS1_BASE); - writel(0x77777777, IMX_AIPS1_BASE + 0x4); - writel(0x77777777, IMX_AIPS2_BASE); - writel(0x77777777, IMX_AIPS2_BASE + 0x4); + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ - writel(0x0, IMX_AIPS1_BASE + 0x40); - writel(0x0, IMX_AIPS1_BASE + 0x44); - writel(0x0, IMX_AIPS1_BASE + 0x48); - writel(0x0, IMX_AIPS1_BASE + 0x4C); - tmp = readl(IMX_AIPS1_BASE + 0x50); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); tmp &= 0x00FFFFFF; - writel(tmp, IMX_AIPS1_BASE + 0x50); + writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - writel(0x0, IMX_AIPS2_BASE + 0x40); - writel(0x0, IMX_AIPS2_BASE + 0x44); - writel(0x0, IMX_AIPS2_BASE + 0x48); - writel(0x0, IMX_AIPS2_BASE + 0x4C); - tmp = readl(IMX_AIPS2_BASE + 0x50); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); tmp &= 0x00FFFFFF; - writel(tmp, IMX_AIPS2_BASE + 0x50); + writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ /* SGPCR - always park on last master */ - writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ - writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ - writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ - writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ - writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ /* MGPCR - restore default values */ - writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ - writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ - writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ - writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ - writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ - writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ /* * M3IF Control Register (M3IFCTL) @@ -288,7 +287,7 @@ static int pcm043_core_setup(void) * ------------ * 0x00000040 */ - writel(0x40, IMX_M3IF_BASE); + writel(0x40, MX35_M3IF_BASE_ADDR); return 0; } @@ -309,10 +308,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S index 0cba308723..3c36889e7a 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S +++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S @@ -96,8 +96,8 @@ reset: #ifdef CONFIG_NAND_IMX_BOOT ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ - ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ - ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */ + ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ /* skip NAND boot if not running from NFC space */ cmp pc, r0 diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 77fa8a92cd..45e59fbfd2 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -136,10 +136,10 @@ static void pca100_usb_register(void) mdelay(10); - ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL); - ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL); + ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); } #endif @@ -155,10 +155,10 @@ static void pca100_usb_init(void) { u32 reg; - reg = readl(IMX_OTG_BASE + 0x600); + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600); reg &= ~((3 << 21) | 1); reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); - writel(reg, IMX_OTG_BASE + 0x600); + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600); /* * switch usbotg and usbh2 to ulpi mode. Do this *before* @@ -166,15 +166,15 @@ static void pca100_usb_init(void) * triggering. Also, do this even when USB support is * disabled to give Linux USB support a good start. */ - reg = readl(IMX_OTG_BASE + 0x584); + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584); reg &= ~(3 << 30); reg |= 2 << 30; - writel(reg, IMX_OTG_BASE + 0x584); + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584); - reg = readl(IMX_OTG_BASE + 0x184); + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184); reg &= ~(3 << 30); reg |= 2 << 30; - writel(reg, IMX_OTG_BASE + 0x184); + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184); /* disable the usb phys */ imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN); diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index 9bd9a7cb63..c83132adc8 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -22,6 +22,7 @@ #include <mach/imx-regs.h> #include <asm/armlinux.h> #include <mach/gpio.h> +#include <mach/weim.h> #include <io.h> #include <partition.h> #include <fs.h> @@ -70,19 +71,11 @@ static int scb9328_devices_init(void) /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ FMCR = 0x1; - CS0U = 0x000F2000; - CS0L = 0x11110d01; - - CS1U = 0x000F0a00; - CS1L = 0x11110601; - CS2U = 0x0; - CS2L = 0x0; - CS3U = 0x000FFFFF; - CS3L = 0x00000303; - CS4U = 0x000F0a00; - CS4L = 0x11110301; - CS5U = 0x00008400; - CS5L = 0x00000D03; + imx1_setup_eimcs(0, 0x000F2000, 0x11110d01); + imx1_setup_eimcs(1, 0x000F0a00, 0x11110601); + imx1_setup_eimcs(3, 0x000FFFFF, 0x00000303); + imx1_setup_eimcs(4, 0x000F0a00, 0x11110301); + imx1_setup_eimcs(5, 0x00008400, 0x00000D03); add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x10000000, 16 * 1024 * 1024, 0); add_dm9000_device(DEVICE_ID_DYNAMIC, 0x16000000, 0x16000004, diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7ab812abc5..d27d4f34d5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -552,14 +552,6 @@ endmenu menu "i.MX specific settings " -config IMX_CLKO - bool "clko command" - depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 - help - The i.MX SoCs have a Pin which can output different reference frequencies. - Say y here if you want to have the clko command which lets you select the - frequency to output on this pin. - config IMX_IIM tristate "IIM fusebox device" depends on !ARCH_IMX21 && !ARCH_IMX21 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 2b595bce43..e43f92e430 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,19 +1,18 @@ obj-y += clocksource.o gpio.o obj-$(CONFIG_RESET_SOURCE) += reset_source.o -obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o imx1.o iomux-v1.o -obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o -obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o -obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o -obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o -obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o -obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o -obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o -obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o usb-imx6.o -obj-$(CONFIG_IMX_CLKO) += clko.o +obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o +obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o +obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o +obj-$(CONFIG_ARCH_IMX27) += imx27.o iomux-v1.o clk-imx27.o +obj-$(CONFIG_ARCH_IMX31) += imx31.o iomux-v2.o clk-imx31.o +obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o +obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o +obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o +obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o -obj-y += speed.o +obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o obj-y += devices.o obj-y += boot.o diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c new file mode 100644 index 0000000000..45e9c6643f --- /dev/null +++ b/arch/arm/mach-imx/clk-imx1.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx1-regs.h> + +#include "clk.h" + +#define CCM_CSCR 0x0 +#define CCM_MPCTL0 0x4 +#define CCM_SPCTL0 0xc +#define CCM_PCDR 0x20 + +enum imx1_clks { + dummy, clk32, clk16m, clk32_premult, prem, mpll, spll, mcu, + fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate, + mma_gate, usbd_gate, clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *prem_sel_clks[] = { + "clk32_premult", + "clk16m", +}; + +static const char *clko_sel_clks[] = { + "per1", + "hclk", + "clk48m", + "clk16m", + "prem", + "fclk", +}; + +int __init mx1_clocks_init(void __iomem *regs, unsigned long fref) +{ + clks[dummy] = clk_fixed("dummy", 0); + clks[clk32] = clk_fixed("clk32", fref); + clks[clk16m] = clk_fixed("clk16m", 16000000); + clks[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); + clks[prem] = imx_clk_mux("prem", regs + CCM_CSCR, 16, 1, prem_sel_clks, + ARRAY_SIZE(prem_sel_clks)); + clks[mpll] = imx_clk_pllv1("mpll", "clk32_premult", regs + CCM_MPCTL0); + clks[spll] = imx_clk_pllv1("spll", "prem", regs + CCM_SPCTL0); + clks[mcu] = imx_clk_divider("mcu", "clk32_premult", regs + CCM_CSCR, 15, 1); + clks[fclk] = imx_clk_divider("fclk", "mpll", regs + CCM_CSCR, 15, 1); + clks[hclk] = imx_clk_divider("hclk", "spll", regs + CCM_CSCR, 10, 4); + clks[clk48m] = imx_clk_divider("clk48m", "spll", regs + CCM_CSCR, 26, 3); + clks[per1] = imx_clk_divider("per1", "spll", regs + CCM_PCDR, 0, 4); + clks[per2] = imx_clk_divider("per2", "spll", regs + CCM_PCDR, 4, 4); + clks[per3] = imx_clk_divider("per3", "spll", regs + CCM_PCDR, 16, 7); + clks[clko] = imx_clk_mux("clko", regs + CCM_CSCR, 29, 3, clko_sel_clks, + ARRAY_SIZE(clko_sel_clks)); + + clkdev_add_physbase(clks[per1], MX1_TIM1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX1_TIM2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX1_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX1_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX1_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX1_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX1_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[hclk], MX1_I2C_BASE_ADDR, NULL); + + return 0; +} + +static int imx1_ccm_probe(struct device_d *dev) +{ + void __iomem *regs; + + regs = dev_request_mem_region(dev, 0); + + mx1_clocks_init(regs, 32000); + + return 0; +} + +static struct driver_d imx1_ccm_driver = { + .probe = imx1_ccm_probe, + .name = "imx1-ccm", +}; + +static int imx1_ccm_init(void) +{ + return platform_driver_register(&imx1_ccm_driver); +} +postcore_initcall(imx1_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c new file mode 100644 index 0000000000..69aaa9e6ad --- /dev/null +++ b/arch/arm/mach-imx/clk-imx21.c @@ -0,0 +1,119 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx21-regs.h> + +#include "clk.h" + +/* Register offsets */ +#define CCM_CSCR 0x0 +#define CCM_MPCTL0 0x4 +#define CCM_MPCTL1 0x8 +#define CCM_SPCTL0 0xc +#define CCM_SPCTL1 0x10 +#define CCM_OSC26MCTL 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1c +#define CCM_PCCR0 0x20 +#define CCM_PCCR1 0x24 +#define CCM_CCSR 0x28 +#define CCM_PMCTL 0x2c +#define CCM_PMCOUNT 0x30 +#define CCM_WKGDCTL 0x34 + +enum imx21_clks { + ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1, + per2, per3, per4, usb_div, nfc_div, clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *mpll_sel_clks[] = { + "fpm", + "ckih", +}; + +static const char *spll_sel_clks[] = { + "fpm", + "ckih", +}; + +static int imx21_ccm_probe(struct device_d *dev) +{ + void __iomem *base; + unsigned long lref = 32768; + unsigned long href = 26000000; + + base = dev_request_mem_region(dev, 0); + + clks[ckil] = clk_fixed("ckil", lref); + clks[ckih] = clk_fixed("ckih", href); + clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); + clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks, + ARRAY_SIZE(mpll_sel_clks)); + clks[spll_sel] = imx_clk_mux("spll_sel", base + CCM_CSCR, 17, 1, spll_sel_clks, + ARRAY_SIZE(spll_sel_clks)); + clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0); + clks[spll] = imx_clk_pllv1("spll", "spll_sel", base + CCM_SPCTL0); + clks[fclk] = imx_clk_divider("fclk", "mpll", base + CCM_CSCR, 29, 3); + clks[hclk] = imx_clk_divider("hclk", "fclk", base + CCM_CSCR, 10, 4); + clks[ipg] = imx_clk_divider("ipg", "hclk", base + CCM_CSCR, 9, 1); + clks[per1] = imx_clk_divider("per1", "mpll", base + CCM_PCDR1, 0, 6); + clks[per2] = imx_clk_divider("per2", "mpll", base + CCM_PCDR1, 8, 6); + clks[per3] = imx_clk_divider("per3", "mpll", base + CCM_PCDR1, 16, 6); + clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6); + clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3); + clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4); + + clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_GPT3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3], MX21_CSPI3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL); + + return 0; +} + +static struct driver_d imx21_ccm_driver = { + .probe = imx21_ccm_probe, + .name = "imx21-ccm", +}; + +static int imx21_ccm_init(void) +{ + return platform_driver_register(&imx21_ccm_driver); +} +postcore_initcall(imx21_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c new file mode 100644 index 0000000000..3b9588ced5 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx25.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2009 by Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx25-regs.h> + +#include "clk.h" + +#define CCM_MPCTL 0x00 +#define CCM_UPCTL 0x04 +#define CCM_CCTL 0x08 +#define CCM_CGCR0 0x0C +#define CCM_CGCR1 0x10 +#define CCM_CGCR2 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1C +#define CCM_PCDR2 0x20 +#define CCM_PCDR3 0x24 +#define CCM_RCSR 0x28 +#define CCM_CRDR 0x2C +#define CCM_DCVR0 0x30 +#define CCM_DCVR1 0x34 +#define CCM_DCVR2 0x38 +#define CCM_DCVR3 0x3c +#define CCM_LTR0 0x40 +#define CCM_LTR1 0x44 +#define CCM_LTR2 0x48 +#define CCM_LTR3 0x4c +#define CCM_MCR 0x64 + +enum mx25_clks { + dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, + per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel, + per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, + per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, + per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, + clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *cpu_sel_clks[] = { + "mpll", + "mpll_cpu_3_4", +}; + +static const char *per_sel_clks[] = { + "ahb", + "upll", +}; + +static int imx25_ccm_probe(struct device_d *dev) +{ + void __iomem *base; + + base = dev_request_mem_region(dev, 0); + + writel(0x10e88578, base + CCM_CGCR0); + writel(0x0478e1e0, base + CCM_CGCR0); + writel(0x0007c400, base + CCM_CGCR0); + + clks[dummy] = clk_fixed("dummy", 0); + clks[osc] = clk_fixed("osc", 24000000); + clks[mpll] = imx_clk_pllv1("mpll", "osc", base + CCM_MPCTL); + clks[upll] = imx_clk_pllv1("upll", "osc", base + CCM_UPCTL); + clks[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); + clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CCTL, 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); + clks[cpu] = imx_clk_divider("cpu", "cpu_sel", base + CCM_CCTL, 30, 2); + clks[ahb] = imx_clk_divider("ahb", "cpu", base + CCM_CCTL, 28, 2); + clks[usb_div] = imx_clk_divider("usb_div", "upll", base + CCM_CCTL, 16, 6); + clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); + clks[per0_sel] = imx_clk_mux("per0_sel", base + CCM_MCR, 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per1_sel] = imx_clk_mux("per1_sel", base + CCM_MCR, 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per2_sel] = imx_clk_mux("per2_sel", base + CCM_MCR, 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per3_sel] = imx_clk_mux("per3_sel", base + CCM_MCR, 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per4_sel] = imx_clk_mux("per4_sel", base + CCM_MCR, 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per5_sel] = imx_clk_mux("per5_sel", base + CCM_MCR, 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per6_sel] = imx_clk_mux("per6_sel", base + CCM_MCR, 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per7_sel] = imx_clk_mux("per7_sel", base + CCM_MCR, 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per8_sel] = imx_clk_mux("per8_sel", base + CCM_MCR, 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per9_sel] = imx_clk_mux("per9_sel", base + CCM_MCR, 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per10_sel] = imx_clk_mux("per10_sel", base + CCM_MCR, 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per11_sel] = imx_clk_mux("per11_sel", base + CCM_MCR, 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per12_sel] = imx_clk_mux("per12_sel", base + CCM_MCR, 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per13_sel] = imx_clk_mux("per13_sel", base + CCM_MCR, 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per14_sel] = imx_clk_mux("per14_sel", base + CCM_MCR, 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per15_sel] = imx_clk_mux("per15_sel", base + CCM_MCR, 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); + clks[per0] = imx_clk_divider("per0", "per0_sel", base + CCM_PCDR0, 0, 6); + clks[per1] = imx_clk_divider("per1", "per1_sel", base + CCM_PCDR0, 8, 6); + clks[per2] = imx_clk_divider("per2", "per2_sel", base + CCM_PCDR0, 16, 6); + clks[per3] = imx_clk_divider("per3", "per3_sel", base + CCM_PCDR0, 24, 6); + clks[per4] = imx_clk_divider("per4", "per4_sel", base + CCM_PCDR1, 0, 6); + clks[per5] = imx_clk_divider("per5", "per5_sel", base + CCM_PCDR1, 8, 6); + clks[per6] = imx_clk_divider("per6", "per6_sel", base + CCM_PCDR1, 16, 6); + clks[per7] = imx_clk_divider("per7", "per7_sel", base + CCM_PCDR1, 24, 6); + clks[per8] = imx_clk_divider("per8", "per8_sel", base + CCM_PCDR2, 0, 6); + clks[per9] = imx_clk_divider("per9", "per9_sel", base + CCM_PCDR2, 8, 6); + clks[per10] = imx_clk_divider("per10", "per10_sel", base + CCM_PCDR2, 16, 6); + clks[per11] = imx_clk_divider("per11", "per11_sel", base + CCM_PCDR2, 24, 6); + clks[per12] = imx_clk_divider("per12", "per12_sel", base + CCM_PCDR3, 0, 6); + clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6); + clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6); + clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6); + + clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per15], MX25_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_I2C3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL); + + return 0; +} + +static struct driver_d imx25_ccm_driver = { + .probe = imx25_ccm_probe, + .name = "imx25-ccm", +}; + +static int imx25_ccm_init(void) +{ + return platform_driver_register(&imx25_ccm_driver); +} +postcore_initcall(imx25_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c new file mode 100644 index 0000000000..abfde0fd62 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx27.c @@ -0,0 +1,154 @@ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx27-regs.h> +#include <mach/generic.h> + +#include "clk.h" + +/* Register offsets */ +#define CCM_CSCR 0x0 +#define CCM_MPCTL0 0x4 +#define CCM_MPCTL1 0x8 +#define CCM_SPCTL0 0xc +#define CCM_SPCTL1 0x10 +#define CCM_OSC26MCTL 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1c +#define CCM_PCCR0 0x20 +#define CCM_PCCR1 0x24 +#define CCM_CCSR 0x28 +#define CCM_PMCTL 0x2c +#define CCM_PMCOUNT 0x30 +#define CCM_WKGDCTL 0x34 + +enum mx27_clks { + dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, + per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div, + clko_en, clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *cpu_sel_clks[] = { + "mpll_main2", + "mpll", +}; + +static const char *clko_sel_clks[] = { + "ckil", + NULL, + "ckih", + "ckih", + "ckih", + "mpll", + "spll", + "cpu_div", + "ahb", + "ipg", + "per1_div", + "per2_div", + "per3_div", + "per4_div", + NULL, + NULL, + "nfc_div", + NULL, + NULL, + NULL, + "ckil", + "usb_div", + NULL, +}; + +static int imx27_ccm_probe(struct device_d *dev) +{ + void __iomem *base; + + base = dev_request_mem_region(dev, 0); + + writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN | + PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | PCCR0_I2C2_EN | + PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | PCCR0_GPT4_EN | + PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | PCCR0_GPIO_EN | + PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | PCCR0_CSPI1_EN, + base + CCM_PCCR0); + + writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK3_EN | + PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | PCCR1_HCLK_USB | + PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN | PCCR1_USB_EN | + PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN | + PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN, + base + CCM_PCCR1); + + clks[dummy] = clk_fixed("dummy", 0); + clks[ckih] = clk_fixed("ckih", 26000000); + clks[ckil] = clk_fixed("ckil", 32768); + clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL0); + clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0); + clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); + + if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) { + clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2); + clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); + } else { + clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 9, 4); + clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CSCR, 8, 1); + } + + clks[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + CCM_PCDR0, 6, 4); + clks[per1_div] = imx_clk_divider("per1_div", "mpll_main2", base + CCM_PCDR1, 0, 6); + clks[per2_div] = imx_clk_divider("per2_div", "mpll_main2", base + CCM_PCDR1, 8, 6); + clks[per3_div] = imx_clk_divider("per3_div", "mpll_main2", base + CCM_PCDR1, 16, 6); + clks[per4_div] = imx_clk_divider("per4_div", "mpll_main2", base + CCM_PCDR1, 24, 6); + clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 28, 3); + clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CSCR, 15, 1, cpu_sel_clks, + ARRAY_SIZE(cpu_sel_clks)); + clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks, + ARRAY_SIZE(clko_sel_clks)); + if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) + clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2); + else + clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3); + clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3); + + clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_GPT3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_GPT4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_GPT5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_GPT6_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per1_div], MX27_UART6_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_CSPI3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3_div], MX27_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL); + + return 0; +} + +static struct driver_d imx27_ccm_driver = { + .probe = imx27_ccm_probe, + .name = "imx27-ccm", +}; + +static int imx27_ccm_init(void) +{ + return platform_driver_register(&imx27_ccm_driver); +} +postcore_initcall(imx27_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c new file mode 100644 index 0000000000..cf8963a326 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx31.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx31-regs.h> + +#include "clk.h" + +/* Register addresses */ +#define CCM_CCMR 0x00 +#define CCM_PDR0 0x04 +#define CCM_PDR1 0x08 +//#define CCM_RCSR 0x0C +#define CCM_MPCTL 0x10 +#define CCM_UPCTL 0x14 +#define CCM_SRPCTL 0x18 +#define CCM_COSR 0x1C +#define CCM_CGR0 0x20 +#define CCM_CGR1 0x24 +#define CCM_CGR2 0x28 +#define CCM_WIMR 0x2C +#define CCM_LDC 0x30 +#define CCM_DCVR0 0x34 +#define CCM_DCVR1 0x38 +#define CCM_DCVR2 0x3C +#define CCM_DCVR3 0x40 +#define CCM_LTR0 0x44 +#define CCM_LTR1 0x48 +#define CCM_LTR2 0x4C +#define CCM_LTR3 0x50 +#define CCM_LTBR0 0x54 +#define CCM_LTBR1 0x58 +#define CCM_PMCR0 0x5C +#define CCM_PMCR1 0x60 +#define CCM_PDR2 0x64 + +enum mx31_clks { + ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div, + per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, + fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, + iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, + uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, + mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate, + sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, + uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate, + gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *mcu_main_sel[] = { + "spll", + "mpll", +}; + +static const char *per_sel[] = { + "per_div", + "ipg", +}; + +static int imx31_ccm_probe(struct device_d *dev) +{ + void __iomem *base; + + base = dev_request_mem_region(dev, 0); + + writel(0xffffffff, base + CCM_CGR0); + writel(0xffffffff, base + CCM_CGR1); + writel(0xffffffff, base + CCM_CGR2); + + clks[ckih] = clk_fixed("ckih", 26000000); + clks[ckil] = clk_fixed("ckil", 32768); + clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL); + clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SRPCTL); + clks[upll] = imx_clk_pllv1("upll", "ckih", base + CCM_UPCTL); + clks[mcu_main] = imx_clk_mux("mcu_main", base + CCM_PMCR0, 31, 1, + mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); + clks[hsp] = imx_clk_divider("hsp", "mcu_main", base + CCM_PDR0, 11, 3); + clks[ahb] = imx_clk_divider("ahb", "mcu_main", base + CCM_PDR0, 3, 3); + clks[nfc] = imx_clk_divider("nfc", "ahb", base + CCM_PDR0, 8, 3); + clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_PDR0, 6, 2); + clks[per_div] = imx_clk_divider("per_div", "upll", base + CCM_PDR0, 16, 5); + clks[per] = imx_clk_mux("per", base + CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); + + clkdev_add_physbase(clks[per], MX31_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_UART4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_UART5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_I2C3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX31_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX31_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX31_CSPI3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_SDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_SDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per], MX31_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[hsp], MX31_IPU_CTRL_BASE_ADDR, NULL); + + return 0; +} + +static struct driver_d imx31_ccm_driver = { + .probe = imx31_ccm_probe, + .name = "imx31-ccm", +}; + +static int imx31_ccm_init(void) +{ + return platform_driver_register(&imx31_ccm_driver); +} +postcore_initcall(imx31_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c new file mode 100644 index 0000000000..dfa75614fa --- /dev/null +++ b/arch/arm/mach-imx/clk-imx35.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx35-regs.h> + +#include "clk.h" + +#define CCM_CCMR 0x00 +#define CCM_PDR0 0x04 +#define CCM_PDR1 0x08 +#define CCM_PDR2 0x0C +#define CCM_PDR3 0x10 +#define CCM_PDR4 0x14 +#define CCM_RCSR 0x18 +#define CCM_MPCTL 0x1C +#define CCM_PPCTL 0x20 +#define CCM_ACMR 0x24 +#define CCM_COSR 0x28 +#define CCM_CGR0 0x2C +#define CCM_CGR1 0x30 +#define CCM_CGR2 0x34 +#define CCM_CGR3 0x38 + +struct arm_ahb_div { + unsigned char arm, ahb, sel; +}; + +static struct arm_ahb_div clk_consumer[] = { + { .arm = 1, .ahb = 4, .sel = 0}, + { .arm = 1, .ahb = 3, .sel = 1}, + { .arm = 2, .ahb = 2, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 4, .ahb = 1, .sel = 0}, + { .arm = 1, .ahb = 5, .sel = 0}, + { .arm = 1, .ahb = 8, .sel = 0}, + { .arm = 1, .ahb = 6, .sel = 1}, + { .arm = 2, .ahb = 4, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, + { .arm = 4, .ahb = 2, .sel = 0}, + { .arm = 0, .ahb = 0, .sel = 0}, +}; + +static char hsp_div_532[] = { 4, 8, 3, 0 }; +static char hsp_div_400[] = { 3, 6, 3, 0 }; + +enum mx35_clks { + ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, + arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, + esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, + spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, + ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, + audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, + edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, + esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, + gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, + kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, + rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, + ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, + wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate, + clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *std_sel[] = { + "ppll", + "arm", +}; + +static const char *ipg_per_sel[] = { + "ahb_per_div", + "arm_per_div", +}; + +static int imx35_ccm_probe(struct device_d *dev) +{ + u32 pdr0, consumer_sel, hsp_sel; + struct arm_ahb_div *aad; + unsigned char *hsp_div; + void __iomem *base; + + base = dev_request_mem_region(dev, 0); + + writel(0xffffffff, base + CCM_CGR0); + writel(0xffffffff, base + CCM_CGR1); + writel(0xffffffff, base + CCM_CGR2); + writel(0xffffffff, base + CCM_CGR3); + + pdr0 = __raw_readl(base + CCM_PDR0); + consumer_sel = (pdr0 >> 16) & 0xf; + aad = &clk_consumer[consumer_sel]; + if (!aad->arm) { + pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); + /* + * We are basically stuck. Continue with a default entry and hope we + * get far enough to actually show the above message + */ + aad = &clk_consumer[0]; + } + + clks[ckih] = clk_fixed("ckih", 24000000); + clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL); + clks[ppll] = imx_clk_pllv1("ppll", "ckih", base + CCM_PPCTL); + + clks[mpll_075] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); + + if (aad->sel) + clks[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); + else + clks[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); + + if (clk_get_rate(clks[arm]) > 400000000) + hsp_div = hsp_div_532; + else + hsp_div = hsp_div_400; + + hsp_sel = (pdr0 >> 20) & 0x3; + if (!hsp_div[hsp_sel]) { + pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); + hsp_sel = 0; + } + + clks[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); + + clks[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); + clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); + + clks[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + CCM_PDR4, 16, 6); + clks[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + CCM_PDR0, 12, 3); + clks[ipg_per] = imx_clk_mux("ipg_per", base + CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); + + clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); + clks[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + CCM_PDR4, 10, 6); + + clks[esdhc_sel] = imx_clk_mux("esdhc_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); + clks[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + CCM_PDR3, 0, 6); + clks[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + CCM_PDR3, 8, 6); + clks[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + CCM_PDR3, 16, 6); + + clks[usb_sel] = imx_clk_mux("usb_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); + clks[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + CCM_PDR4, 22, 6); + + clkdev_add_physbase(clks[uart_div], MX35_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_div], MX35_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_div], MX35_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX35_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX35_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX35_I2C3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX35_CSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX35_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX35_FEC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX35_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc1_div], MX35_ESDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc2_div], MX35_ESDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc3_div], MX35_ESDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[hsp], MX35_IPU_CTRL_BASE_ADDR, NULL); + + return 0; +} + +static struct driver_d imx35_ccm_driver = { + .probe = imx35_ccm_probe, + .name = "imx35-ccm", +}; + +static int imx35_ccm_init(void) +{ + return platform_driver_register(&imx35_ccm_driver); +} +postcore_initcall(imx35_ccm_init); diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c new file mode 100644 index 0000000000..365fcb3338 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx5.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx-regs.h> + +#include "clk.h" + +/* Register addresses of CCM*/ +#define CCM_CCR 0x00 +#define CCM_CCDR 0x04 +#define CCM_CSR 0x08 +#define CCM_CCSR 0x0C +#define CCM_CACRR 0x10 +#define CCM_CBCDR 0x14 +#define CCM_CBCMR 0x18 +#define CCM_CSCMR1 0x1C +#define CCM_CSCMR2 0x20 +#define CCM_CSCDR1 0x24 +#define CCM_CS1CDR 0x28 +#define CCM_CS2CDR 0x2C +#define CCM_CDCDR 0x30 +#define CCM_CHSCDR 0x34 +#define CCM_CSCDR2 0x38 +#define CCM_CSCDR3 0x3C +#define CCM_CSCDR4 0x40 +#define CCM_CWDR 0x44 +#define CCM_CDHIPR 0x48 +#define CCM_CDCR 0x4C +#define CCM_CTOR 0x50 +#define CCM_CLPCR 0x54 +#define CCM_CISR 0x58 +#define CCM_CIMR 0x5C +#define CCM_CCOSR 0x60 +#define CCM_CGPR 0x64 +#define CCM_CCGR0 0x68 +#define CCM_CCGR1 0x6C +#define CCM_CCGR2 0x70 +#define CCM_CCGR3 0x74 +#define CCM_CCGR4 0x78 +#define CCM_CCGR5 0x7C +#define CCM_CCGR6 0x80 +#define CCM_CCGR7 0x84 + +#define CCM_CMEOR 0x84 + +enum imx5_clks { + dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, + uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s, + emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred, + usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, lp_apm, + periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2, + tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf, + esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, + gpc_dvfs, pll1_sw, pll2_sw, + pll3_sw, pll4_sw, per_lp_apm, per_pred1, per_pred2, per_podf, per_root, + clk_max +}; + +static struct clk *clks[clk_max]; + +/* This is used multiple times */ +static const char *standard_pll_sel[] = { + "pll1_sw", + "pll2_sw", + "pll3_sw", + "lp_apm", +}; + +static const char *lp_apm_sel[] = { + "osc", +}; + +static const char *periph_apm_sel[] = { + "pll1_sw", + "pll3_sw", + "lp_apm", +}; + +static const char *main_bus_sel[] = { + "pll2_sw", + "periph_apm", +}; + +static const char *per_lp_apm_sel[] = { + "main_bus", + "lp_apm", +}; + +static const char *per_root_sel[] = { + "per_podf", + "ipg", +}; + +static const char *esdhc_c_sel[] = { + "esdhc_a_podf", + "esdhc_b_podf", +}; + +static const char *esdhc_d_sel[] = { + "esdhc_a_podf", + "esdhc_b_podf", +}; + +static const char *emi_slow_sel[] = { + "main_bus", + "ahb", +}; + +static const char *usb_phy_sel_str[] = { + "osc", + "usb_phy_podf", +}; + +static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil, + unsigned long rate_osc, unsigned long rate_ckih1, + unsigned long rate_ckih2) +{ + writel(0xffffffff, base + CCM_CCGR0); + writel(0xffffffff, base + CCM_CCGR1); + writel(0xffffffff, base + CCM_CCGR2); + writel(0xffffffff, base + CCM_CCGR3); + writel(0xffffffff, base + CCM_CCGR4); + writel(0xffffffff, base + CCM_CCGR5); + writel(0xffffffff, base + CCM_CCGR6); + writel(0xffffffff, base + CCM_CCGR7); + + clks[dummy] = clk_fixed("dummy", 0); + clks[ckil] = clk_fixed("ckil", rate_ckil); + clks[osc] = clk_fixed("osc", rate_osc); + clks[ckih1] = clk_fixed("ckih1", rate_ckih1); + clks[ckih2] = clk_fixed("ckih2", rate_ckih2); + + clks[lp_apm] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1, + lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clks[periph_apm] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2, + periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); + clks[main_bus] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1, + main_bus_sel, ARRAY_SIZE(main_bus_sel)); + clks[per_lp_apm] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1, + per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); + clks[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2); + clks[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3); + clks[per_podf] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3); + clks[per_root] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1, + per_root_sel, ARRAY_SIZE(per_root_sel)); + clks[ahb] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3); + clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2); + clks[axi_a] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3); + clks[axi_b] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3); + clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3); + clks[uart_root] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3); + + clks[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3); + clks[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3); + clks[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3); + clks[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3); + clks[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); + clks[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); + + clks[emi_sel] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1, + emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); + clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3); + clks[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3); + clks[ecspi_sel] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3); + clks[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6); + clks[usboh3_sel] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2, + standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3); + clks[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2); + clks[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3); + clks[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3); + clks[usb_phy_sel] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1, + usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); + clks[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3); +} + +#ifdef CONFIG_ARCH_IMX51 +int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc, + unsigned long rate_ckih1, unsigned long rate_ckih2) +{ + clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR); + clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR); + clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR); + + mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + + clkdev_add_physbase(clks[uart_root], MX51_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_root], MX51_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_root], MX51_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX51_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX51_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX51_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX51_CSPI_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX51_MXC_FEC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_a_podf], MX51_MMC_SDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_b_podf], MX51_MMC_SDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_c_s], MX51_MMC_SDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_d_s], MX51_MMC_SDHC4_BASE_ADDR, NULL); + + return 0; +} + +static int imx51_ccm_probe(struct device_d *dev) +{ + void __iomem *regs; + + regs = dev_request_mem_region(dev, 0); + + mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */ + + return 0; +} + +static struct driver_d imx51_ccm_driver = { + .probe = imx51_ccm_probe, + .name = "imx51-ccm", +}; + +static int imx51_ccm_init(void) +{ + return platform_driver_register(&imx51_ccm_driver); +} +postcore_initcall(imx51_ccm_init); +#endif + +#ifdef CONFIG_ARCH_IMX53 +int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc, + unsigned long rate_ckih1, unsigned long rate_ckih2) +{ + clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR); + clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR); + clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR); + clks[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR); + + mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + + clkdev_add_physbase(clks[uart_root], MX53_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_root], MX53_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_root], MX53_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX53_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX53_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per_root], MX53_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX53_CSPI_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX53_FEC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_a_podf], MX53_ESDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_c_s], MX53_ESDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_b_podf], MX53_ESDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[esdhc_d_s], MX53_ESDHC4_BASE_ADDR, NULL); + + return 0; +} + +static int imx53_ccm_probe(struct device_d *dev) +{ + void __iomem *regs; + + regs = dev_request_mem_region(dev, 0); + + mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */ + + return 0; +} + +static struct driver_d imx53_ccm_driver = { + .probe = imx53_ccm_probe, + .name = "imx53-ccm", +}; + +static int imx53_ccm_init(void) +{ + return platform_driver_register(&imx53_ccm_driver); +} +postcore_initcall(imx53_ccm_init); +#endif diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c new file mode 100644 index 0000000000..19a8bc6836 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx6.c @@ -0,0 +1,306 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx6-regs.h> + +#include "clk.h" + +#define CCGR0 0x68 +#define CCGR1 0x6c +#define CCGR2 0x70 +#define CCGR3 0x74 +#define CCGR4 0x78 +#define CCGR5 0x7c +#define CCGR6 0x80 +#define CCGR7 0x84 + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +enum mx6q_clks { + dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, + pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, + pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, + periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, + esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, + gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, + ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, + ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, + ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, + usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, + emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, + periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, + asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, + gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, + ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, + ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, + ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, + usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, + emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, + mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, + can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, + esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, + hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, + ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, + mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, + gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, + ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, + usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, + pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + clk_max +}; + +static struct clk *clks[clk_max]; + +static const char *step_sels[] = { + "osc", + "pll2_pfd2_396m", +}; + +static const char *pll1_sw_sels[] = { + "pll1_sys", + "step", +}; + +static const char *periph_pre_sels[] = { + "pll2_bus", + "pll2_pfd2_396m", + "pll2_pfd0_352m", + "pll2_198m", +}; + +static const char *periph_clk2_sels[] = { + "pll3_usb_otg", + "osc", +}; + +static const char *periph_sels[] = { + "periph_pre", + "periph_clk2", +}; + +static const char *periph2_sels[] = { + "periph2_pre", + "periph2_clk2", +}; + +static const char *axi_sels[] = { + "periph", + "pll2_pfd2_396m", + "pll3_pfd1_540m", +}; + +static const char *usdhc_sels[] = { + "pll2_pfd2_396m", + "pll2_pfd0_352m", +}; + +static const char *enfc_sels[] = { + "pll2_pfd0_352m", + "pll2_bus", + "pll3_usb_otg", + "pll2_pfd2_396m", +}; + +static const char *emi_sels[] = { + "axi", + "pll3_usb_otg", + "pll2_pfd2_396m", + "pll2_pfd0_352m", +}; + +static const char *vdo_axi_sels[] = { + "axi", + "ahb", +}; + +static const char *cko1_sels[] = { + "pll3_usb_otg", + "pll2_bus", + "pll1_sys", + "pll5_video", + "dummy", + "axi", + "enfc", + "ipu1_di0", + "ipu1_di1", + "ipu2_di0", + "ipu2_di1", + "ahb", + "ipg", + "ipg_per", + "ckil", + "pll4_audio", +}; + +static int imx6_ccm_probe(struct device_d *dev) +{ + void __iomem *base, *anatop_base, *ccm_base; + unsigned long ckil_rate = 32768; + unsigned long ckih_rate = 0; + unsigned long osc_rate = 24000000; + + anatop_base = (void *)MX6_ANATOP_BASE_ADDR; + ccm_base = dev_request_mem_region(dev, 0); + + base = anatop_base; + + clks[dummy] = clk_fixed("dummy", 0); + clks[ckil] = clk_fixed("ckil", ckil_rate); + clks[ckih] = clk_fixed("ckih", ckih_rate); + clks[osc] = clk_fixed("osc", osc_rate); + + /* type name parent_name base gate_mask div_mask */ + clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f); + clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1); + clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3); + clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f); + clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f); + clks[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0); + clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); + clks[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); + + /* name parent_name reg idx */ + clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clks[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); + clks[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); + clks[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); + clks[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); + clks[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); + clks[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); + + /* name parent_name mult div */ + clks[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); + clks[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); + clks[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + clks[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + clks[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); + + base = ccm_base; + + /* name reg shift width parent_names num_parents */ + clks[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); + clks[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); + clks[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); + clks[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); + clks[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); + clks[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels)); + clks[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); + clks[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); + + /* name reg shift width busy: reg, shift parent_names num_parents */ + clks[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); + clks[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); + + /* name parent_name reg shift width */ + clks[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); + clks[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); + clks[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); + clks[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); + clks[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); + clks[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); + clks[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); + clks[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); + clks[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); + clks[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); + clks[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); + clks[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); + clks[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); + clks[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); + clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); + clks[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); + + /* name parent_name reg shift width busy: reg, shift */ + clks[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); + clks[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); + clks[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); + clks[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); + clks[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); + + + clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_serial_podf], MX6_UART4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[uart_serial_podf], MX6_UART5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI5_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX6_GPT_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg], MX6_ENET_BASE_ADDR, NULL); + clkdev_add_physbase(clks[usdhc1_podf], MX6_USDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[usdhc2_podf], MX6_USDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[usdhc3_podf], MX6_USDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[usdhc4_podf], MX6_USDHC4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX6_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL); + + writel(0xffffffff, ccm_base + CCGR0); + writel(0xffffffff, ccm_base + CCGR1); + writel(0xffffffff, ccm_base + CCGR2); + writel(0xffffffff, ccm_base + CCGR3); + writel(0xffffffff, ccm_base + CCGR4); + writel(0xffffffff, ccm_base + CCGR5); + writel(0xffffffff, ccm_base + CCGR6); + writel(0xffffffff, ccm_base + CCGR7); + + return 0; +} + +static struct driver_d imx6_ccm_driver = { + .probe = imx6_ccm_probe, + .name = "imx6-ccm", +}; + +static int imx6_ccm_init(void) +{ + return platform_driver_register(&imx6_ccm_driver); +} +postcore_initcall(imx6_ccm_init); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c new file mode 100644 index 0000000000..8f6d5ad7a8 --- /dev/null +++ b/arch/arm/mach-imx/clk-pfd.c @@ -0,0 +1,148 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <malloc.h> +#include <asm-generic/div64.h> + +#include "clk.h" + +/** + * struct clk_pfd - IMX PFD clock + * @clk_hw: clock source + * @reg: PFD register address + * @idx: the index of PFD encoded in the register + * + * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd + * data encoded, and member idx is used to specify the one. And each + * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. + */ +struct clk_pfd { + struct clk clk; + void __iomem *reg; + u8 idx; + const char *parent; +}; + +#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk) + +#define SET 0x4 +#define CLR 0x8 +#define OTG 0xc + +static int clk_pfd_enable(struct clk *clk) +{ + struct clk_pfd *pfd = to_clk_pfd(clk); + writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); + + return 0; +} + +static void clk_pfd_disable(struct clk *clk) +{ + struct clk_pfd *pfd = to_clk_pfd(clk); + + writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); +} + +static unsigned long clk_pfd_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_pfd *pfd = to_clk_pfd(clk); + u64 tmp = parent_rate; + u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f; + + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static long clk_pfd_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + u64 tmp = *prate; + u8 frac; + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + tmp = *prate; + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static int clk_pfd_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pfd *pfd = to_clk_pfd(clk); + u64 tmp = parent_rate; + u8 frac; + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + + writel(0x3f << (pfd->idx * 8), pfd->reg + CLR); + writel(frac << (pfd->idx * 8), pfd->reg + SET); + + return 0; +} + +static const struct clk_ops clk_pfd_ops = { + .enable = clk_pfd_enable, + .disable = clk_pfd_disable, + .recalc_rate = clk_pfd_recalc_rate, + .round_rate = clk_pfd_round_rate, + .set_rate = clk_pfd_set_rate, +}; + +struct clk *imx_clk_pfd(const char *name, const char *parent, + void __iomem *reg, u8 idx) +{ + struct clk_pfd *pfd; + int ret; + + pfd = xzalloc(sizeof(*pfd)); + + pfd->reg = reg; + pfd->idx = idx; + pfd->parent = parent; + pfd->clk.name = name; + pfd->clk.ops = &clk_pfd_ops; + pfd->clk.parent_names = &pfd->parent; + pfd->clk.num_parents = 1; + + ret = clk_register(&pfd->clk); + if (ret) { + free(pfd); + return ERR_PTR(ret); + } + + return &pfd->clk; +} diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/clk-pllv1.c index c86ad71758..6785da0dee 100644 --- a/arch/arm/mach-imx/speed.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -1,10 +1,4 @@ /* - * - * (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -16,25 +10,33 @@ * GNU General Public License for more details. * */ - -#include <asm-generic/div64.h> #include <common.h> -#include <command.h> -#include <complete.h> -#include <mach/clock.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <malloc.h> +#include <asm-generic/div64.h> -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -unsigned int imx_decode_pll(unsigned int reg_val, unsigned int freq) +#include "clk.h" + +struct clk_pllv1 { + struct clk clk; + void __iomem *reg; + const char *parent; +}; + +static unsigned long clk_pllv1_recalc_rate(struct clk *clk, + unsigned long parent_rate) { + struct clk_pllv1 *pll = container_of(clk, struct clk_pllv1, clk); unsigned long long ll; int mfn_abs; unsigned int mfi, mfn, mfd, pd; + u32 reg_val = readl(pll->reg); + unsigned long freq = parent_rate; mfi = (reg_val >> 10) & 0xf; mfn = reg_val & 0x3ff; @@ -65,18 +67,28 @@ unsigned int imx_decode_pll(unsigned int reg_val, unsigned int freq) return ll; } -extern void imx_dump_clocks(void); +struct clk_ops clk_pllv1_ops = { + .recalc_rate = clk_pllv1_recalc_rate, +}; -static int do_clocks(int argc, char *argv[]) +struct clk *imx_clk_pllv1(const char *name, const char *parent, + void __iomem *base) { - imx_dump_clocks(); + struct clk_pllv1 *pll = xzalloc(sizeof(*pll)); + int ret; - return 0; -} + pll->parent = parent; + pll->reg = base; + pll->clk.ops = &clk_pllv1_ops; + pll->clk.name = name; + pll->clk.parent_names = &pll->parent; + pll->clk.num_parents = 1; -BAREBOX_CMD_START(dump_clocks) - .cmd = do_clocks, - .usage = "show clock frequencies", - BAREBOX_CMD_COMPLETE(empty_complete) -BAREBOX_CMD_END + ret = clk_register(&pll->clk); + if (ret) { + free(pll); + return ERR_PTR(ret); + } + return &pll->clk; +} diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c new file mode 100644 index 0000000000..69072698c4 --- /dev/null +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -0,0 +1,164 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx-regs.h> +#include <malloc.h> +#include <asm-generic/div64.h> + +#include "clk.h" + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ + +struct clk_pllv2 { + struct clk clk; + void __iomem *reg; + const char *parent; +}; + +static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, + u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dbl; + uint64_t temp; + + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * parent_rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static unsigned long clk_pllv2_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + u32 dp_op, dp_mfd, dp_mfn, dp_ctl; + void __iomem *pllbase; + struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk); + + pllbase = pll->reg; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + + return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn); +} + +struct clk_ops clk_pllv2_ops = { + .recalc_rate = clk_pllv2_recalc_rate, +}; + +struct clk *imx_clk_pllv2(const char *name, const char *parent, + void __iomem *base) +{ + struct clk_pllv2 *pll = xzalloc(sizeof(*pll)); + int ret; + + pll->parent = parent; + pll->reg = base; + pll->clk.ops = &clk_pllv2_ops; + pll->clk.name = name; + pll->clk.parent_names = &pll->parent; + pll->clk.num_parents = 1; + + ret = clk_register(&pll->clk); + if (ret) { + free(pll); + return ERR_PTR(ret); + } + + return &pll->clk; +} diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c new file mode 100644 index 0000000000..a99eec56a3 --- /dev/null +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -0,0 +1,386 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <init.h> +#include <driver.h> +#include <linux/clk.h> +#include <io.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <mach/imx-regs.h> +#include <malloc.h> +#include <clock.h> +#include <asm-generic/div64.h> + +#include "clk.h" + +#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x20 + +#define BM_PLL_POWER (0x1 << 12) +#define BM_PLL_ENABLE (0x1 << 13) +#define BM_PLL_BYPASS (0x1 << 16) +#define BM_PLL_LOCK (0x1 << 31) + +struct clk_pllv3 { + struct clk clk; + void __iomem *base; + bool powerup_set; + u32 gate_mask; + u32 div_mask; + const char *parent; +}; + +#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk) + +static int clk_pllv3_enable(struct clk *clk) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 val; + int ret; + + val = readl(pll->base); + val &= ~BM_PLL_BYPASS; + if (pll->powerup_set) + val |= BM_PLL_POWER; + else + val &= ~BM_PLL_POWER; + writel(val, pll->base); + + /* Wait for PLL to lock */ + ret = wait_on_timeout(10 * MSECOND, !(readl(pll->base) & BM_PLL_LOCK)); + if (ret) + return ret; + + val = readl(pll->base); + val |= pll->gate_mask; + writel(val, pll->base); + + return 0; +} + +static void clk_pllv3_disable(struct clk *clk) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 val; + + val = readl(pll->base); + val &= ~pll->gate_mask; + writel(val, pll->base); + + val |= BM_PLL_BYPASS; + if (pll->powerup_set) + val &= ~BM_PLL_POWER; + else + val |= BM_PLL_POWER; + writel(val, pll->base); +} + +static unsigned long clk_pllv3_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 div = readl(pll->base) & pll->div_mask; + + return (div == 1) ? parent_rate * 22 : parent_rate * 20; +} + +static long clk_pllv3_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + + return (rate >= parent_rate * 22) ? parent_rate * 22 : + parent_rate * 20; +} + +static int clk_pllv3_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 val, div; + + if (rate == parent_rate * 22) + div = 1; + else if (rate == parent_rate * 20) + div = 0; + else + return -EINVAL; + + val = readl(pll->base); + val &= ~pll->div_mask; + val |= div; + writel(val, pll->base); + + return 0; +} + +static const struct clk_ops clk_pllv3_ops = { + .enable = clk_pllv3_enable, + .disable = clk_pllv3_disable, + .recalc_rate = clk_pllv3_recalc_rate, + .round_rate = clk_pllv3_round_rate, + .set_rate = clk_pllv3_set_rate, +}; + +static unsigned long clk_pllv3_sys_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 div = readl(pll->base) & pll->div_mask; + + return parent_rate * div / 2; +} + +static long clk_pllv3_sys_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + unsigned long min_rate = parent_rate * 54 / 2; + unsigned long max_rate = parent_rate * 108 / 2; + u32 div; + + if (rate > max_rate) + rate = max_rate; + else if (rate < min_rate) + rate = min_rate; + div = rate * 2 / parent_rate; + + return parent_rate * div / 2; +} + +static int clk_pllv3_sys_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + unsigned long min_rate = parent_rate * 54 / 2; + unsigned long max_rate = parent_rate * 108 / 2; + u32 val, div; + + if (rate < min_rate || rate > max_rate) + return -EINVAL; + + div = rate * 2 / parent_rate; + val = readl(pll->base); + val &= ~pll->div_mask; + val |= div; + writel(val, pll->base); + + return 0; +} + +static const struct clk_ops clk_pllv3_sys_ops = { + .enable = clk_pllv3_enable, + .disable = clk_pllv3_disable, + .recalc_rate = clk_pllv3_sys_recalc_rate, + .round_rate = clk_pllv3_sys_round_rate, + .set_rate = clk_pllv3_sys_set_rate, +}; + +static unsigned long clk_pllv3_av_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 mfn = readl(pll->base + PLL_NUM_OFFSET); + u32 mfd = readl(pll->base + PLL_DENOM_OFFSET); + u32 div = readl(pll->base) & pll->div_mask; + + return (parent_rate * div) + ((parent_rate / mfd) * mfn); +} + +static long clk_pllv3_av_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + unsigned long min_rate = parent_rate * 27; + unsigned long max_rate = parent_rate * 54; + u32 div; + u32 mfn, mfd = 1000000; + u64 temp64; + + if (rate > max_rate) + rate = max_rate; + else if (rate < min_rate) + rate = min_rate; + + div = rate / parent_rate; + temp64 = (u64) (rate - div * parent_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + return parent_rate * div + parent_rate / mfd * mfn; +} + +static int clk_pllv3_av_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + unsigned long min_rate = parent_rate * 27; + unsigned long max_rate = parent_rate * 54; + u32 val, div; + u32 mfn, mfd = 1000000; + u64 temp64; + + if (rate < min_rate || rate > max_rate) + return -EINVAL; + + div = rate / parent_rate; + temp64 = (u64) (rate - div * parent_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + val = readl(pll->base); + val &= ~pll->div_mask; + val |= div; + writel(val, pll->base); + writel(mfn, pll->base + PLL_NUM_OFFSET); + writel(mfd, pll->base + PLL_DENOM_OFFSET); + + return 0; +} + +static const struct clk_ops clk_pllv3_av_ops = { + .enable = clk_pllv3_enable, + .disable = clk_pllv3_disable, + .recalc_rate = clk_pllv3_av_recalc_rate, + .round_rate = clk_pllv3_av_round_rate, + .set_rate = clk_pllv3_av_set_rate, +}; + +static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 div = readl(pll->base) & pll->div_mask; + + switch (div) { + case 0: + return 25000000; + case 1: + return 50000000; + case 2: + return 100000000; + case 3: + return 125000000; + } + + return 0; +} + +static long clk_pllv3_enet_round_rate(struct clk *clk, unsigned long rate, + unsigned long *prate) +{ + if (rate >= 125000000) + rate = 125000000; + else if (rate >= 100000000) + rate = 100000000; + else if (rate >= 50000000) + rate = 50000000; + else + rate = 25000000; + return rate; +} + +static int clk_pllv3_enet_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + u32 val, div; + + switch (rate) { + case 25000000: + div = 0; + break; + case 50000000: + div = 1; + break; + case 100000000: + div = 2; + break; + case 125000000: + div = 3; + break; + default: + return -EINVAL; + } + + val = readl(pll->base); + val &= ~pll->div_mask; + val |= div; + writel(val, pll->base); + + return 0; +} + +static const struct clk_ops clk_pllv3_enet_ops = { + .enable = clk_pllv3_enable, + .disable = clk_pllv3_disable, + .recalc_rate = clk_pllv3_enet_recalc_rate, + .round_rate = clk_pllv3_enet_round_rate, + .set_rate = clk_pllv3_enet_set_rate, +}; + +static const struct clk_ops clk_pllv3_mlb_ops = { + .enable = clk_pllv3_enable, + .disable = clk_pllv3_disable, +}; + +struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, + const char *parent, void __iomem *base, + u32 gate_mask, u32 div_mask) +{ + struct clk_pllv3 *pll; + const struct clk_ops *ops; + int ret; + + pll = xzalloc(sizeof(*pll)); + + switch (type) { + case IMX_PLLV3_SYS: + ops = &clk_pllv3_sys_ops; + break; + case IMX_PLLV3_USB: + ops = &clk_pllv3_ops; + pll->powerup_set = true; + break; + case IMX_PLLV3_AV: + ops = &clk_pllv3_av_ops; + break; + case IMX_PLLV3_ENET: + ops = &clk_pllv3_enet_ops; + break; + case IMX_PLLV3_MLB: + ops = &clk_pllv3_mlb_ops; + break; + default: + ops = &clk_pllv3_ops; + } + pll->base = base; + pll->gate_mask = gate_mask; + pll->div_mask = div_mask; + pll->parent = parent; + pll->clk.ops = ops; + pll->clk.name = name; + pll->clk.parent_names = &pll->parent; + pll->clk.num_parents = 1; + + ret = clk_register(&pll->clk); + if (ret) { + free(pll); + return ERR_PTR(ret); + } + + return &pll->clk; +} diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h new file mode 100644 index 0000000000..3d79950697 --- /dev/null +++ b/arch/arm/mach-imx/clk.h @@ -0,0 +1,66 @@ +#ifndef __IMX_CLK_H +#define __IMX_CLK_H + +static inline struct clk *imx_clk_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width) +{ + return clk_divider(name, parent, reg, shift, width); +} + +static inline struct clk *imx_clk_fixed_factor(const char *name, + const char *parent, unsigned int mult, unsigned int div) +{ + return clk_fixed_factor(name, parent, mult, div); +} + +static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, u8 num_parents) +{ + return clk_mux(name, reg, shift, width, parents, num_parents); +} + +struct clk *imx_clk_pllv1(const char *name, const char *parent, + void __iomem *base); + +struct clk *imx_clk_pllv2(const char *name, const char *parent, + void __iomem *base); + +enum imx_pllv3_type { + IMX_PLLV3_GENERIC, + IMX_PLLV3_SYS, + IMX_PLLV3_USB, + IMX_PLLV3_AV, + IMX_PLLV3_ENET, + IMX_PLLV3_MLB, +}; + +struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, + const char *parent, void __iomem *base, + u32 gate_mask, u32 div_mask); + +struct clk *imx_clk_pfd(const char *name, const char *parent, + void __iomem *reg, u8 idx); + +static inline struct clk *imx_clk_busy_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, + void __iomem *busy_reg, u8 busy_shift) +{ + /* + * For now we do not support rate setting, so just fall back to + * regular divider. + */ + return imx_clk_divider(name, parent, reg, shift, width); +} + +static inline struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, + u8 width, void __iomem *busy_reg, u8 busy_shift, + const char **parents, int num_parents) +{ + /* + * For now we do not support mux switching, so just fall back to + * regular mux. + */ + return imx_clk_mux(name, reg, shift, width, parents, num_parents); +} + +#endif /* __IMX_CLK_H */ diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c deleted file mode 100644 index aeafaa9c41..0000000000 --- a/arch/arm/mach-imx/clko.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <common.h> -#include <command.h> -#include <getopt.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> - -static int do_clko(int argc, char *argv[]) -{ - int opt, div = 0, src = -2, num = 1, ret; - - while((opt = getopt(argc, argv, "n:d:s:")) > 0) { - switch(opt) { - case 'n': - num = simple_strtoul(optarg, NULL, 0); - break; - case 'd': - div = simple_strtoul(optarg, NULL, 0); - break; - case 's': - src = simple_strtol(optarg, NULL, 0); - break; - } - } - - if (div == 0 && src == -2) - return COMMAND_ERROR_USAGE; - - if (src == -1) { - imx_clko_set_src(num, -1); - return 0; - } - - if (src != -2) - imx_clko_set_src(num, src); - - if (div != 0) { - ret = imx_clko_set_div(num, div); - if (ret < 0) - printf("CLKO-line %i not supported.\n", num); - else if (ret != div) - printf("Divider limited to %d.\n", ret); - } - - return 0; -} - -static __maybe_unused char cmd_clko_help[] = -"Usage: clko [OPTION]...\n" -"Route different signals to the i.MX clko pin\n" -" -n <num> Number of CLKO-line (Default 1)\n" -" -d <div> Divider\n" -" -s <source> Clock select. See Ref. Manual for valid sources. Use -1\n" -" for disabling clock output\n"; - -BAREBOX_CMD_START(clko) - .cmd = do_clko, - .usage = "Adjust CLKO setting", - BAREBOX_CMD_HELP(cmd_clko_help) -BAREBOX_CMD_END - diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index bd41e75888..5fa6201174 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -29,9 +29,10 @@ #include <init.h> #include <clock.h> #include <errno.h> +#include <linux/clk.h> +#include <linux/err.h> #include <notifier.h> #include <mach/imx-regs.h> -#include <mach/clock.h> #include <io.h> /* Part 1: Registers */ @@ -46,6 +47,8 @@ #define IMX31_TCTL_CLKSOURCE_IPG (1 << 6) /* Clock source bit position */ #define TCTL_TEN (1 << 0) /* Timer enable */ +static struct clk *clk_gpt; + struct imx_gpt_regs { unsigned int tcn; uint32_t tctl_val; @@ -77,7 +80,7 @@ static struct clocksource cs = { static int imx_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data) { - cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift); + cs.mult = clocksource_hz2mult(clk_get_rate(clk_gpt), cs.shift); return 0; } @@ -89,6 +92,7 @@ static int imx_gpt_probe(struct device_d *dev) { int i; int ret; + unsigned long rate; /* one timer is enough */ if (timer_base) @@ -118,10 +122,18 @@ static int imx_gpt_probe(struct device_d *dev) for (i = 0; i < 100; i++) writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */ + clk_gpt = clk_get(dev, NULL); + if (IS_ERR(clk_gpt)) { + rate = 20000000; + dev_err(dev, "failed to get clock\n"); + } else { + rate = clk_get_rate(clk_gpt); + } + writel(0, timer_base + GPT_TPRER); writel(regs->tctl_val, timer_base + GPT_TCTL); - cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift); + cs.mult = clocksource_hz2mult(rate, cs.shift); init_clock(&cs); diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 5cab32fd39..a5909923f6 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -122,7 +122,7 @@ static int __maybe_unused is_pagesize_2k(void) return 0; #endif #ifdef CONFIG_ARCH_IMX27 - if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5)) + if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) return 1; else return 0; diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c index b32e371275..790e4535d7 100644 --- a/arch/arm/mach-imx/imx1.c +++ b/arch/arm/mach-imx/imx1.c @@ -13,15 +13,25 @@ #include <common.h> #include <init.h> +#include <io.h> +#include <mach/imx-regs.h> +#include <mach/weim.h> + +void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower) +{ + writel(upper, MX1_EIM_BASE_ADDR + cs * 8); + writel(lower, MX1_EIM_BASE_ADDR + 4 + cs * 8); +} static int imx1_init(void) { - add_generic_device("imx1-gpt", 0, NULL, 0x00202000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 0, NULL, 0x0021c000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 1, NULL, 0x0021c100, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 2, NULL, 0x0021c200, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 3, NULL, 0x0021c300, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-ccm", 0, NULL, MX1_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx1_init); +postcore_initcall(imx1_init); diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index df3eaf2666..7ed0809760 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -13,7 +13,15 @@ #include <common.h> #include <init.h> +#include <io.h> #include <mach/imx-regs.h> +#include <mach/weim.h> + +void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower) +{ + writel(upper, MX21_EIM_BASE_ADDR + cs * 8); + writel(lower, MX21_EIM_BASE_ADDR + 4 + cs * 8); +} int imx_silicon_revision(void) { @@ -25,14 +33,15 @@ int imx_silicon_revision(void) static int imx21_init(void) { - add_generic_device("imx1-gpt", 0, NULL, 0x10003000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, MX21_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, MX21_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 3, NULL, MX21_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 4, NULL, MX21_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 5, NULL, MX21_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx21_init); +postcore_initcall(imx21_init); diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index dd10d58767..5e6532a8f9 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -16,8 +16,25 @@ #include <mach/imx-regs.h> #include <mach/iim.h> #include <io.h> +#include <mach/weim.h> #include <sizes.h> +void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional) +{ + writel(upper, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x0); + writel(lower, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x4); + writel(additional, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x8); +} + +/* IIM fuse definitions */ +#define IIM_BANK0_BASE (MX25_IIM_BASE_ADDR + 0x800) +#define IIM_BANK1_BASE (MX25_IIM_BASE_ADDR + 0xc00) +#define IIM_BANK2_BASE (MX25_IIM_BASE_ADDR + 0x1000) + +#define IIM_UID (IIM_BANK0_BASE + 0x20) +#define IIM_MAC_ADDR (IIM_BANK0_BASE + 0x68) + u64 imx_uid(void) { u64 uid = 0; @@ -41,15 +58,16 @@ static struct imx_iim_platform_data imx25_iim_pdata = { static int imx25_init(void) { - add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, + add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, &imx25_iim_pdata); - add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 3, NULL, 0x53f9c000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx25-ccm", 0, NULL, MX25_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpt", 0, NULL, MX25_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 0, NULL, MX25_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 1, NULL, MX25_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 2, NULL, MX25_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 3, NULL, MX25_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx25_init); +postcore_initcall(imx25_init); diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 32a32a33a6..8116e6f932 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -13,6 +13,7 @@ #include <common.h> #include <mach/imx-regs.h> +#include <mach/weim.h> #include <sizes.h> #include <init.h> #include <io.h> @@ -22,6 +23,14 @@ int imx_silicon_revision(void) return CID >> 28; } +void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional) +{ + writel(upper, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x0); + writel(lower, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4); + writel(additional, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x8); +} + /* * Initialize MAX on i.MX27. necessary to give the DMA engine * higher priority to the memory than the CPU. Needed for proper @@ -43,7 +52,7 @@ int imx_silicon_revision(void) static void imx27_init_max(void) { - void __iomem *max_base = (void *)IMX_MAX_BASE; + void __iomem *max_base = (void *)MX27_MAX_BASE_ADDR; u32 val; /* 0 is the highest priority */ @@ -64,18 +73,20 @@ static void imx27_init_max(void) static int imx27_init(void) { - add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, + add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); imx27_init_max(); - add_generic_device("imx1-gpt", 0, NULL, 0x10003000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx1-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx27-ccm", 0, NULL, MX27_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpt", 0, NULL, MX27_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 0, NULL, MX27_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 1, NULL, MX27_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 2, NULL, MX27_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + return 0; } -console_initcall(imx27_init); +postcore_initcall(imx27_init); diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 881c3e586e..90eee0a209 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -14,18 +14,29 @@ #include <common.h> #include <init.h> #include <sizes.h> +#include <io.h> #include <mach/imx-regs.h> +#include <mach/weim.h> + +void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional) +{ + writel(upper, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x0); + writel(lower, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x4); + writel(additional, MX31_WEIM_BASE_ADDR + (cs * 0x10) + 0x8); +} static int imx31_init(void) { - add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, + add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx31_init); +postcore_initcall(imx31_init); diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index 579e14814d..722dd4c38c 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -15,14 +15,23 @@ #include <sizes.h> #include <init.h> #include <io.h> +#include <mach/weim.h> #include <mach/imx-regs.h> #include <mach/iim.h> #include <mach/generic.h> +void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional) +{ + writel(upper, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x0); + writel(lower, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x4); + writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8); +} + int imx_silicon_revision() { uint32_t reg; - reg = readl(IMX_IIM_BASE + IIM_SREV); + reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV); /* 0×00 = TO 1.0, First silicon */ reg += IMX_CHIP_REV_1_0; @@ -41,7 +50,7 @@ int imx_silicon_revision() static int imx35_l2_fix(void) { - writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL); + writel(0x515, MX35_CLKCTL_BASE_ADDR + L2_MEM_VAL); return 0; } @@ -49,14 +58,15 @@ core_initcall(imx35_l2_fix); static int imx35_init(void) { - add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K, + add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx35_init); +postcore_initcall(imx35_init); diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 022614ffde..8709c43ac2 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -74,15 +74,16 @@ static int imx51_init(void) add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpt", 0, NULL, 0x73fa0000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 0, NULL, 0x73f84000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 1, NULL, 0x73f88000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 2, NULL, 0x73f8c000, 0x1000, IORESOURCE_MEM, NULL); - add_generic_device("imx31-gpio", 3, NULL, 0x73f90000, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 2, NULL, MX51_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } -coredevice_initcall(imx51_init); +postcore_initcall(imx51_init); /* * Saves the boot source media into the $barebox_loc enviroment variable diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index 2d7c174e25..88b4274fd5 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -70,6 +70,7 @@ static int imx53_init(void) add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 1, NULL, MX53_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); @@ -81,7 +82,7 @@ static int imx53_init(void) return 0; } -coredevice_initcall(imx53_init); +postcore_initcall(imx53_init); #define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5) #define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1) diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index babf8fea80..a5ec36471e 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -54,6 +54,7 @@ void imx6_init_lowlevel(void) static int imx6_init(void) { + add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, 0x02098000, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); @@ -65,4 +66,4 @@ static int imx6_init(void) return 0; } -coredevice_initcall(imx6_init); +postcore_initcall(imx6_init); diff --git a/arch/arm/mach-imx/include/mach/clkdev.h b/arch/arm/mach-imx/include/mach/clkdev.h new file mode 100644 index 0000000000..04b37a8980 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h index f613395768..304a7c885c 100644 --- a/arch/arm/mach-imx/include/mach/clock.h +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -1,41 +1 @@ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -ulong imx_get_mpllclk(void); - -#ifdef CONFIG_ARCH_IMX27 -ulong imx_get_armclk(void); -#endif -#ifdef CONFIG_ARCH_IMX1 -static inline ulong imx_get_armclk(void) -{ - return imx_get_mpllclk(); -} -#endif - -ulong imx_get_spllclk(void); -ulong imx_get_fclk(void); -ulong imx_get_hclk(void); -ulong imx_get_bclk(void); -ulong imx_get_perclk1(void); -ulong imx_get_perclk2(void); -ulong imx_get_perclk3(void); -ulong imx_get_ahbclk(void); -ulong imx_get_fecclk(void); -ulong imx_get_gptclk(void); -ulong imx_get_uartclk(void); -ulong imx_get_lcdclk(void); -ulong fsl_get_i2cclk(void); -ulong imx_get_mmcclk(void); -ulong imx_get_cspiclk(void); -ulong imx_get_ipgclk(void); -ulong imx_get_usbclk(void); - -int imx_clko_set_div(int num, int div); -void imx_clko_set_src(int num, int src); - -void imx_dump_clocks(void); - -#endif /* __ASM_ARCH_CLOCK_H */ +/* nothing, but some drivers need this include */ diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h index a45363f61d..c73113cf64 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx1.h +++ b/arch/arm/mach-imx/include/mach/devices-imx1.h @@ -2,10 +2,10 @@ static inline struct device_d *imx1_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX1_UART1_BASE_ADDR, 0); } static inline struct device_d *imx1_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX1_UART2_BASE_ADDR, 1); } diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h index 1e1fbbdf4c..31c5f8c17b 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx21.h +++ b/arch/arm/mach-imx/include/mach/devices-imx21.h @@ -3,22 +3,22 @@ static inline struct device_d *imx21_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX21_UART1_BASE_ADDR, 0); } static inline struct device_d *imx21_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 1); } static inline struct device_d *imx21_add_uart2(void) { - return imx_add_uart((void *)IMX_UART3_BASE, 2); + return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 2); } static inline struct device_d *imx21_add_uart3(void) { - return imx_add_uart((void *)IMX_UART4_BASE, 3); + return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 3); } static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h index bd9dd0a914..86cda35a43 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx25.h +++ b/arch/arm/mach-imx/include/mach/devices-imx25.h @@ -3,41 +3,80 @@ static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); + return imx_add_i2c((void *)MX25_I2C1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx25_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX25_I2C2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx25_add_i2c2(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX25_I2C3_BASE_ADDR, 2, pdata); } static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata); + return imx_add_spi((void *)MX25_CSPI1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx25_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX25_CSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx25_add_spi2(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX25_CSPI3_BASE_ADDR, 2, pdata); } static inline struct device_d *imx25_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX25_UART1_BASE_ADDR, 0); } static inline struct device_d *imx25_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX25_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx25_add_uart2(void) +{ + return imx_add_uart((void *)MX25_UART3_BASE_ADDR, 2); +} + +static inline struct device_d *imx25_add_uart3(void) +{ + return imx_add_uart((void *)MX25_UART4_BASE_ADDR, 3); +} + +static inline struct device_d *imx25_add_uart4(void) +{ + return imx_add_uart((void *)MX25_UART5_BASE_ADDR, 4); } static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata) { - return imx_add_nand((void *)IMX_NFC_BASE, pdata); + return imx_add_nand((void *)MX25_NFC_BASE_ADDR, pdata); } static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata) { - return imx_add_fb((void *)0x53fbc000, pdata); + return imx_add_fb((void *)MX25_LCDC_BASE_ADDR, pdata); } static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)IMX_FEC_BASE, pdata); + return imx_add_fec((void *)MX25_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata) { - return imx_add_esdhc((void *)0x53fb4000, 0, pdata); + return imx_add_esdhc((void *)MX25_ESDHC1_BASE_ADDR, 0, pdata); } +static inline struct device_d *imx25_add_mmc1(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX25_ESDHC2_BASE_ADDR, 1, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h index 6a3a2341b2..2799343e59 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx27.h +++ b/arch/arm/mach-imx/include/mach/devices-imx27.h @@ -3,70 +3,70 @@ static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); + return imx_add_spi((void *)MX27_CSPI1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx27_add_spi1(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata); + return imx_add_spi((void *)MX27_CSPI2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); + return imx_add_i2c((void *)MX27_I2C1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata); + return imx_add_i2c((void *)MX27_I2C2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx27_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX27_UART1_BASE_ADDR, 0); } static inline struct device_d *imx27_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX27_UART2_BASE_ADDR, 1); } static inline struct device_d *imx27_add_uart2(void) { - return imx_add_uart((void *)IMX_UART3_BASE, 2); + return imx_add_uart((void *)MX27_UART3_BASE_ADDR, 2); } static inline struct device_d *imx27_add_uart3(void) { - return imx_add_uart((void *)IMX_UART4_BASE, 3); + return imx_add_uart((void *)MX27_UART4_BASE_ADDR, 3); } static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata) { - return imx_add_nand((void *)IMX_NFC_BASE, pdata); + return imx_add_nand((void *)MX27_NFC_BASE_ADDR, pdata); } static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata) { - return imx_add_fb((void *)IMX_FB_BASE, pdata); + return imx_add_fb((void *)MX27_LCDC_BASE_ADDR, pdata); } static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)IMX_FEC_BASE, pdata); + return imx_add_fec((void *)MX27_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx27_add_mmc0(void *pdata) { - return imx_add_mmc((void *)IMX_SDHC1_BASE, 0, pdata); + return imx_add_mmc((void *)MX27_SDHC1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx27_add_mmc1(void *pdata) { - return imx_add_mmc((void *)IMX_SDHC2_BASE, 1, pdata); + return imx_add_mmc((void *)MX27_SDHC2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx27_add_mmc2(void *pdata) { - return imx_add_mmc((void *)IMX_SDHC3_BASE, 2, pdata); + return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata); } diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h index 5dcea82fb0..d45e4e1027 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx31.h +++ b/arch/arm/mach-imx/include/mach/devices-imx31.h @@ -2,34 +2,52 @@ #include <mach/imx-regs.h> #include <mach/devices.h> -#if 0 static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); + return imx_add_spi((void *)MX31_CSPI1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata); + return imx_add_spi((void *)MX31_CSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX31_CSPI3_BASE_ADDR, 2, pdata); } -#endif static inline struct device_d *imx31_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX31_UART1_BASE_ADDR, 0); } static inline struct device_d *imx31_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX31_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx31_add_uart2(void) +{ + return imx_add_uart((void *)MX31_UART3_BASE_ADDR, 2); +} + +static inline struct device_d *imx31_add_uart3(void) +{ + return imx_add_uart((void *)MX31_UART4_BASE_ADDR, 3); +} + +static inline struct device_d *imx31_add_uart4(void) +{ + return imx_add_uart((void *)MX31_UART5_BASE_ADDR, 4); } static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata) { - return imx_add_nand((void *)0xb8000000, pdata); + return imx_add_nand((void *)MX31_NFC_BASE_ADDR, pdata); } static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata) { - return imx_add_ipufb((void *)IPU_BASE, pdata); + return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata); } diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h index 9ecaa35ffe..27c49e7161 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx35.h +++ b/arch/arm/mach-imx/include/mach/devices-imx35.h @@ -3,60 +3,70 @@ static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); + return imx_add_i2c((void *)MX35_I2C1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata); + return imx_add_i2c((void *)MX35_I2C2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata) { - return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata); + return imx_add_i2c((void *)MX35_I2C3_BASE_ADDR, 2, pdata); } static inline struct device_d *imx35_add_spi0(struct spi_imx_master *pdata) { - return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata); + return imx_add_spi((void *)MX35_CSPI1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx35_add_spi(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX35_CSPI2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx35_add_uart0(void) { - return imx_add_uart((void *)IMX_UART1_BASE, 0); + return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0); } static inline struct device_d *imx35_add_uart1(void) { - return imx_add_uart((void *)IMX_UART2_BASE, 1); + return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx35_add_uart2(void) +{ + return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2); } static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata) { - return imx_add_nand((void *)IMX_NFC_BASE, pdata); + return imx_add_nand((void *)MX35_NFC_BASE_ADDR, pdata); } static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata) { - return imx_add_ipufb((void *)IMX_IPU_BASE, pdata); + return imx_add_ipufb((void *)MX35_IPU_CTRL_BASE_ADDR, pdata); } static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)IMX_FEC_BASE, pdata); + return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata) { - return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata); + return imx_add_esdhc((void *)MX35_ESDHC1_BASE_ADDR, 0, pdata); } static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata) { - return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata); + return imx_add_esdhc((void *)MX35_ESDHC2_BASE_ADDR, 1, pdata); } static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata) { - return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata); + return imx_add_esdhc((void *)MX35_ESDHC3_BASE_ADDR, 2, pdata); } diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h index d5ee3f58a6..cb60c84d31 100644 --- a/arch/arm/mach-imx/include/mach/imx1-regs.h +++ b/arch/arm/mach-imx/include/mach/imx1-regs.h @@ -1,82 +1,91 @@ #ifndef _IMX1_REGS_H #define _IMX1_REGS_H -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif +#define MX1_IO_BASE_ADDR 0x00200000 +#define MX1_IO_SIZE SZ_1M -#define IMX_IO_BASE 0x00200000 +#define MX1_CS0_PHYS 0x10000000 +#define MX1_CS0_SIZE 0x02000000 + +#define MX1_CS1_PHYS 0x12000000 +#define MX1_CS1_SIZE 0x01000000 + +#define MX1_CS2_PHYS 0x13000000 +#define MX1_CS2_SIZE 0x01000000 + +#define MX1_CS3_PHYS 0x14000000 +#define MX1_CS3_SIZE 0x01000000 + +#define MX1_CS4_PHYS 0x15000000 +#define MX1_CS4_SIZE 0x01000000 + +#define MX1_CS5_PHYS 0x16000000 +#define MX1_CS5_SIZE 0x01000000 /* * Register BASEs, based on OFFSETs */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) +#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) +#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) +#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) +#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) +#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) +#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) +#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) +#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) +#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) +#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) +#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) +#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) +#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) +#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) +#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) +#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) +#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) +#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) +#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) +#define MX1_SCM_BASE_ADDR (0x1B800 + MX1_IO_BASE_ADDR) +#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) +#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) +#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) +#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) +#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) +#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) + +/* FIXME: get rid of these */ +#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR +#define IMX_WDT_BASE MX1_WDT_BASE_ADDR +#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR /* SYSCTRL Registers */ -#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ -#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ -#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ +#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */ +#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */ +#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */ /* SDRAM controller registers */ -#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ -#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ -#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ +#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */ +#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */ +#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */ /* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ +#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */ +#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */ +#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ +#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */ #define CSCR_MPLL_RESTART (1<<21) -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ - /* assignements for GPIO alternate/primary functions */ /* FIXME: This list is not completed. The correct directions are diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h index 98e73ef27e..9952b8bd1f 100644 --- a/arch/arm/mach-imx/include/mach/imx21-regs.h +++ b/arch/arm/mach-imx/include/mach/imx21-regs.h @@ -1,44 +1,96 @@ #ifndef _IMX21_REGS_H #define _IMX21_REGS_H -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) - -#define IMX_SDRAM_BASE (0xdf000000) -#define IMX_EIM_BASE (0xdf001000) -#define IMX_NFC_BASE (0xdf003000) +#define MX21_AIPI_BASE_ADDR 0x10000000 +#define MX21_AIPI_SIZE SZ_1M +#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) +#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) +#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) +#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) +#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) +#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) +#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) +#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) +#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) +#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) +#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) +#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) +#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) +#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) +#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) +#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) +#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) +#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) +#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) +#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) +#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) +#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) +#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) +#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) +#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) +#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) +#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) +#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) +#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) +#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) +#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) +#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) + +#define MX21_AVIC_BASE_ADDR 0x10040000 + +#define MX21_SAHB1_BASE_ADDR 0x80000000 +#define MX21_SAHB1_SIZE SZ_1M +#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) + +/* Memory regions and CS */ +#define MX21_SDRAM_BASE_ADDR 0xc0000000 +#define MX21_CSD1_BASE_ADDR 0xc4000000 + +#define MX21_CS0_BASE_ADDR 0xc8000000 +#define MX21_CS1_BASE_ADDR 0xcc000000 +#define MX21_CS2_BASE_ADDR 0xd0000000 +#define MX21_CS3_BASE_ADDR 0xd1000000 +#define MX21_CS4_BASE_ADDR 0xd2000000 +#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 +#define MX21_CS5_BASE_ADDR 0xdd000000 + +/* NAND, SDRAM, WEIM etc controllers */ +#define MX21_X_MEMC_BASE_ADDR 0xdf000000 +#define MX21_X_MEMC_SIZE SZ_256K + +#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) +#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) +#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) +#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) + +#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ + +/* FIXME: Get rid of these */ +#define IMX_GPIO_BASE MX21_GPIO_BASE_ADDR +#define IMX_TIM1_BASE MX21_GPT1_BASE_ADDR +#define IMX_WDT_BASE MX21_WDOG_BASE_ADDR +#define IMX_SYSTEM_CTL_BASE MX21_SYSCTRL_BASE_ADDR /* AIPI */ -#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) -#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) -#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) -#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) +#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00) +#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04) +#define AIPI2_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x00) +#define AIPI2_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x04) /* System Control */ -#define SUID0 __REG(IMX_SYSTEM_CTL_BASE + 0x4) /* Silicon ID Register (12 bytes) */ -#define SUID1 __REG(IMX_SYSTEM_CTL_BASE + 0x8) /* Silicon ID Register (12 bytes) */ -#define CID __REG(IMX_SYSTEM_CTL_BASE + 0xC) /* Silicon ID Register (12 bytes) */ -#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ +#define SUID0 __REG(MX21_SYSCTRL_BASE_ADDR + 0x4) /* Silicon ID Register (12 bytes) */ +#define SUID1 __REG(MX21_SYSCTRL_BASE_ADDR + 0x8) /* Silicon ID Register (12 bytes) */ +#define CID __REG(MX21_SYSCTRL_BASE_ADDR + 0xC) /* Silicon ID Register (12 bytes) */ +#define FMCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */ +#define GPCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */ +#define WBCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */ +#define DSCR(x) __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ #define GPCR_BOOT_SHIFT 16 #define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) @@ -51,39 +103,23 @@ #define GPCR_BOOT_8BIT_NAND_512 7 /* SDRAM Controller registers bitfields */ -#define SDCTL0 __REG(IMX_SDRAM_BASE + 0x00) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAM_BASE + 0x04) /* SDRAM 0 Control Register */ -#define SDRST __REG(IMX_SDRAM_BASE + 0x18) /* SDRAM Reset Register */ -#define SDMISC __REG(IMX_SDRAM_BASE + 0x14) /* SDRAM Miscellaneous Register */ - - -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE + 0x00) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x04) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x08) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0x0C) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1C) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ +#define SDCTL0 __REG(MX21_X_MEMC_BASE_ADDR + 0x00) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(MX21_X_MEMC_BASE_ADDR + 0x04) /* SDRAM 0 Control Register */ +#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */ +#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */ /* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ +#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */ +#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */ +#define SPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ +#define OSC26MCTL __REG(MX21_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */ +#define PCDR0 __REG(MX21_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */ +#define PCDR1 __REG(MX21_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */ +#define PCCR0 __REG(MX21_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */ +#define PCCR1 __REG(MX21_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */ +#define CCSR __REG(MX21_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */ #define CSCR_MPEN (1 << 0) #define CSCR_SPEN (1 << 1) @@ -107,11 +143,4 @@ #define CCSR_32K_SR (1 << 15) -#define IMX_CS0_BASE 0xC8000000 -#define IMX_CS1_BASE 0xCC000000 -#define IMX_CS2_BASE 0xD0000000 -#define IMX_CS3_BASE 0xD1000000 -#define IMX_CS4_BASE 0xD2000000 -#define IMX_CS5_BASE 0xD3000000 - #endif /* _IMX21_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 5176b5e813..0bf6e119e0 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -19,31 +19,69 @@ #ifndef __ASM_ARCH_MX25_REGS_H #define __ASM_ARCH_MX25_REGS_H +#define MX25_AIPS1_BASE_ADDR 0x43f00000 +#define MX25_AIPS1_SIZE SZ_1M +#define MX25_AIPS2_BASE_ADDR 0x53f00000 +#define MX25_AIPS2_SIZE SZ_1M +#define MX25_AVIC_BASE_ADDR 0x68000000 +#define MX25_AVIC_SIZE SZ_1M + +#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) +#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) + +#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) +#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) + +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX25_UART2_BASE_ADDR 0x43f94000 +#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 +#define MX25_UART3_BASE_ADDR 0x5000c000 +#define MX25_UART4_BASE_ADDR 0x50008000 +#define MX25_UART5_BASE_ADDR 0x5002c000 + +#define MX25_CSPI3_BASE_ADDR 0x50004000 +#define MX25_CSPI2_BASE_ADDR 0x50010000 +#define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_SSI2_BASE_ADDR 0x50014000 +#define MX25_SSI1_BASE_ADDR 0x50034000 +#define MX25_NFC_BASE_ADDR 0xbb000000 +#define MX25_IIM_BASE_ADDR 0x53ff0000 +#define MX25_DRYICE_BASE_ADDR 0x53ffc000 +#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 +#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 +#define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define MX25_KPP_BASE_ADDR 0x43fa8000 +#define MX25_SDMA_BASE_ADDR 0x53fd4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) /* - * sanity check + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_L2CC_BASE 0x30000000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IOMUXC_BASE 0x43FAC000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_MAX_BASE 0x43F04000 -#define IMX_ESD_BASE 0xb8001000 -#define IMX_AIPS1_BASE 0x43F00000 -#define IMX_AIPS2_BASE 0x53F00000 -#define IMX_CCM_BASE 0x53F80000 -#define IMX_IIM_BASE 0x53FF0000 -#define IMX_OTG_BASE 0x53FF4000 -#define IMX_M3IF_BASE 0xB8003000 -#define IMX_NFC_BASE 0xBB000000 -#define IMX_FEC_BASE 0x50038000 -#define IMX_I2C1_BASE 0x43F80000 -#define IMX_CSPI1_BASE 0x43FA4000 +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) +#define MX25_CSI_BASE_ADDR 0x53ff8000 + +/* FIXME: Get rid of these */ +#define IMX_TIM1_BASE MX25_GPT1_BASE_ADDR +#define IMX_IOMUXC_BASE MX25_IOMUXC_BASE_ADDR +#define IMX_WDT_BASE MX25_WDOG_BASE_ADDR +#define IMX_CCM_BASE MX25_CCM_BASE_ADDR +#define IMX_ESD_BASE MX25_ESDCTL_BASE_ADDR /* * Clock Controller Module (CCM) @@ -82,26 +120,24 @@ /* * Adresses and ranges of the external chip select lines */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +#define MX25_CS0_BASE_ADDR 0xA0000000 +#define MX25_CS0_SIZE SZ_128M +#define MX25_CS1_BASE_ADDR 0xA8000000 +#define MX25_CS1_SIZE SZ_128M +#define MX25_CS2_BASE_ADDR 0xB0000000 +#define MX25_CS2_SIZE SZ_32M +#define MX25_CS3_BASE_ADDR 0xB2000000 +#define MX25_CS3_SIZE SZ_32M +#define MX25_CS4_BASE_ADDR 0xB4000000 +#define MX25_CS4_SIZE SZ_32M +#define MX25_CS5_BASE_ADDR 0xB6000000 +#define MX25_CS5_SIZE SZ_32M + +#define MX25_CSD0_BASE_ADDR 0x80000000 +#define MX25_CSD1_BASE_ADDR 0x90000000 + +#define MX25_ESDCTL_BASE_ADDR 0xb8001000 +#define MX25_WEIM_BASE_ADDR 0xb8002000 /* * Watchdog Registers @@ -113,14 +149,4 @@ /* important definition of some bits of WCR */ #define WCR_WDE 0x04 -/* IIM fuse definitions */ -#define IIM_BANK_SIZE 32 /* excluding alignment padding for each row */ -#define IIM_BANK0_BASE (IMX_IIM_BASE + 0x800) -#define IIM_BANK1_BASE (IMX_IIM_BASE + 0xc00) -#define IIM_BANK2_BASE (IMX_IIM_BASE + 0x1000) - -#define IIM_UID (IIM_BANK0_BASE + 0x20) -#define IIM_MAC_ADDR (IIM_BANK0_BASE + 0x68) - #endif /* __ASM_ARCH_MX25_REGS_H */ - diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h index 8686a9dfc3..5db1a3c3eb 100644 --- a/arch/arm/mach-imx/include/mach/imx27-regs.h +++ b/arch/arm/mach-imx/include/mach/imx27-regs.h @@ -1,70 +1,133 @@ #ifndef _IMX27_REGS_H #define _IMX27_REGS_H -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x0e000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x0f000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SDHC1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_SDHC2_BASE (0x14000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1d000 + IMX_IO_BASE) -#define IMX_SDHC3_BASE (0x1e000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_FB_BASE (0x21000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) -#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE) -#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) -#define IMX_MAX_BASE (0x3f000 + IMX_IO_BASE) - -#define IMX_NFC_BASE (0xd8000000) -#define IMX_ESD_BASE (0xd8001000) -#define IMX_WEIM_BASE (0xd8002000) -#define IMX_M3IF_BASE (0xd8003000) -#define IMX_PCMCIA_CTL_BASE (0xd8004000) - -#define PCMCIA_PIPR (IMX_PCMCIA_CTL_BASE + 0x00) -#define PCMCIA_PSCR (IMX_PCMCIA_CTL_BASE + 0x04) -#define PCMCIA_PER (IMX_PCMCIA_CTL_BASE + 0x08) -#define PCMCIA_PBR(x) (IMX_PCMCIA_CTL_BASE + 0x0c + ((x) << 2)) -#define PCMCIA_POR(x) (IMX_PCMCIA_CTL_BASE + 0x28 + ((x) << 2)) -#define PCMCIA_POFR(x) (IMX_PCMCIA_CTL_BASE + 0x44 + ((x) << 2)) -#define PCMCIA_PGCR (IMX_PCMCIA_CTL_BASE + 0x60) -#define PCMCIA_PGSR (IMX_PCMCIA_CTL_BASE + 0x64) +#define MX27_AIPI_BASE_ADDR 0x10000000 +#define MX27_AIPI_SIZE SZ_1M +#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) +#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) +#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) +#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) +#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) +#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) +#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) +#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) +#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) +#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) +#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) +#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) +#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) +#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) +#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) +#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) +#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) +#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) +#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) +#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) +#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) +#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) +#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) +#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) +#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) +#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) +#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) +#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) +#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) +#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) +#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) +#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) +#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) +#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) +#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) +#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) +#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) +#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) +#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) +#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) +#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) +#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) + +#define MX27_AVIC_BASE_ADDR 0x10040000 + +/* ROM patch */ +#define MX27_ROMP_BASE_ADDR 0x10041000 + +#define MX27_SAHB1_BASE_ADDR 0x80000000 +#define MX27_SAHB1_SIZE SZ_1M +#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) +#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) + +/* Memory regions and CS */ +#define MX27_CSD0_BASE_ADDR 0xa0000000 +#define MX27_CSD1_BASE_ADDR 0xb0000000 + +#define MX27_CS0_BASE_ADDR 0xc0000000 +#define MX27_CS1_BASE_ADDR 0xc8000000 +#define MX27_CS2_BASE_ADDR 0xd0000000 +#define MX27_CS3_BASE_ADDR 0xd2000000 +#define MX27_CS4_BASE_ADDR 0xd4000000 +#define MX27_CS5_BASE_ADDR 0xd6000000 + +/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ +#define MX27_X_MEMC_BASE_ADDR 0xd8000000 +#define MX27_X_MEMC_SIZE SZ_1M +#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) +#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) +#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) +#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) +#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) + +#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + +#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 + +/* IRAM */ +#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ + +/* FIXME: get rid of these */ +#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR +#define IMX_NFC_BASE MX27_NFC_BASE_ADDR +#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR +#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR + +#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00) +#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04) +#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08) +#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2)) +#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2)) +#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2)) +#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60) +#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64) /* AIPI */ -#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) -#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) -#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) -#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) +#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00) +#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04) +#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00) +#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04) /* System Control */ -#define CID __REG(IMX_SYSTEM_CTL_BASE + 0x0) /* Chip ID Register */ -#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ +#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */ +#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */ +#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */ +#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */ +#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ #define GPCR_BOOT_SHIFT 16 #define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) @@ -76,26 +139,20 @@ #define GPCR_BOOT_32BIT_CS0 6 #define GPCR_BOOT_8BIT_NAND_512 7 -/* Chip Select Registers */ -#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */ -#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */ -#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */ -#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ - #include "esdctl.h" /* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ +#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */ +#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */ +#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ +#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */ +#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */ +#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */ +#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */ +#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */ +#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */ #define CSCR_MPEN (1 << 0) #define CSCR_SPEN (1 << 1) @@ -221,22 +278,4 @@ #define ESDCFG_TWTR (1 << 20) #define ESDCFG_TXP(x) (((x) & 0x3) << 21) -#define IMX_CS0_BASE 0xC0000000 -#define IMX_CS1_BASE 0xC8000000 -#define IMX_CS2_BASE 0xD0000000 -#define IMX_CS3_BASE 0xD2000000 -#define IMX_CS4_BASE 0xD4000000 -#define IMX_CS5_BASE 0xD6000000 - -#define IMX_PCMCIA_MEM_BASE (0xdc000000) - -#ifndef __ASSEMBLY__ -static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional) -{ - CSxU(cs) = upper; - CSxL(cs) = lower; - CSxA(cs) = addional; -} -#endif /* __ASSEMBLY__ */ - #endif /* _IMX27_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h index e3473d4dea..57f65dad1e 100644 --- a/arch/arm/mach-imx/include/mach/imx31-regs.h +++ b/arch/arm/mach-imx/include/mach/imx31-regs.h @@ -19,79 +19,127 @@ #ifndef __ASM_ARCH_MX31_REGS_H #define __ASM_ARCH_MX31_REGS_H -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_OTG_BASE 0x43F88000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_RTC_BASE 0x53FD8000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IIM_BASE 0x5001C000 - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -/* - * Adresses and ranges of the external chip select lines - */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -#if 0 -#define IMX_IO_BASE 0x00200000 - -/* - * Register BASEs, based on OFFSETs - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define (0x01000 + IMX_IO_BASE) - (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) - (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) -#endif +#include <sizes.h> + +#define MX31_AIPS1_BASE_ADDR 0x43f00000 +#define MX31_AIPS1_SIZE SZ_1M +#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) +#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) +#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) +#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) +#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) +#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) +#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) +#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) +#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) +#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) +#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) +#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) +#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) +#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) +#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) +#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) +#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) +#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) +#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) +#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) + +#define MX31_SPBA0_BASE_ADDR 0x50000000 +#define MX31_SPBA0_SIZE SZ_1M +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) +#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) +#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) +#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) +#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) +#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) +#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) +#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) + +#define MX31_AIPS2_BASE_ADDR 0x53f00000 +#define MX31_AIPS2_SIZE SZ_1M +#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) +#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) +#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) +#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) +#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) +#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) +#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) +#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) +#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) +#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) +#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) +#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) +#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) +#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) +#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) +#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) +#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) +#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) +#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) +#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) +#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) + +#define MX31_ROMP_BASE_ADDR 0x60000000 +#define MX31_ROMP_SIZE SZ_1M + +#define MX31_AVIC_BASE_ADDR 0x68000000 +#define MX31_AVIC_SIZE SZ_1M + +#define MX31_IPU_MEM_BASE_ADDR 0x70000000 +#define MX31_CSD0_BASE_ADDR 0x80000000 +#define MX31_CSD1_BASE_ADDR 0x90000000 + +#define MX31_CS0_BASE_ADDR 0xa0000000 +#define MX31_CS0_SIZE SZ_128M + +#define MX31_CS1_BASE_ADDR 0xa8000000 +#define MX31_CS1_SIZE SZ_128M + +#define MX31_CS2_BASE_ADDR 0xb0000000 +#define MX31_CS2_SIZE SZ_32M + +#define MX31_CS3_BASE_ADDR 0xb2000000 +#define MX31_CS3_SIZE SZ_32M + +#define MX31_CS4_BASE_ADDR 0xb4000000 +#define MX31_CS4_SIZE SZ_32M + +#define MX31_CS5_BASE_ADDR 0xb6000000 +#define MX31_CS5_SIZE SZ_32M + +#define MX31_X_MEMC_BASE_ADDR 0xb8000000 +#define MX31_X_MEMC_SIZE SZ_64K +#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) +#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) +#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) +#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) +#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) +#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR + +#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + +#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +/* FIXME: Get rid of these */ +#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR +#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR +#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR +#define IMX_NFC_BASE MX31_NFC_BASE_ADDR +#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR /* * Clock Controller Module (CCM) */ -#define IMX_CCM_BASE 0x53f80000 #define CCM_CCMR 0x00 #define CCM_PDR0 0x04 #define CCM_PDR1 0x08 @@ -124,45 +172,15 @@ #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) #define PDR0_MCU_PODF(x) ((x) & 0x7) -#define IMX_ESD_BASE 0xb8001000 #include "esdctl.h" /* - * NFC Registers - */ -#define IMX_NFC_BASE (0xb8000000) - -/* - * Chip Select Registers - */ -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - -/* * ??????????? */ -#define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_SCI_EN (1<<0) - -#define WDOG_BASE 0x53FDC000 - /* * Signal Multiplexing (IOMUX) */ @@ -214,4 +232,3 @@ #define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) #endif /* __ASM_ARCH_MX31_REGS_H */ - diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 5a4ab90082..19f6389b95 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -19,39 +19,124 @@ #ifndef __ASM_ARCH_MX35_REGS_H #define __ASM_ARCH_MX35_REGS_H +#include <sizes.h> + +#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define MX35_IRAM_SIZE SZ_128K + +#define MX35_L2CC_BASE_ADDR 0x30000000 +#define MX35_L2CC_SIZE SZ_1M + +#define MX35_AIPS1_BASE_ADDR 0x43f00000 +#define MX35_AIPS1_SIZE SZ_1M +#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) +#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) +#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) +#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) +#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) +#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) +#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) +#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) +#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) +#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) +#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) +#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) +#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) +#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) +#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) +#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) + +#define MX35_SPBA0_BASE_ADDR 0x50000000 +#define MX35_SPBA0_SIZE SZ_1M +#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) +#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) +#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) +#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) +#define MX35_FEC_BASE_ADDR 0x50038000 +#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) + +#define MX35_AIPS2_BASE_ADDR 0x53f00000 +#define MX35_AIPS2_SIZE SZ_1M +#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) +#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) +#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) +#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) +#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) +#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) +#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) +#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) +#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) +#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) +#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) +#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) +#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) +#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) +#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) +#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) +#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) +#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) +#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) +#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) + +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) + +#define MX35_ROMP_BASE_ADDR 0x60000000 +#define MX35_ROMP_SIZE SZ_1M + +#define MX35_AVIC_BASE_ADDR 0x68000000 +#define MX35_AVIC_SIZE SZ_1M + /* - * sanity check + * Memory regions and CS */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_L2CC_BASE 0x30000000 -#define IMX_CLKCTL_BASE 0x43F0C000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IOMUXC_BASE 0x43FAC000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_MAX_BASE 0x43F04000 -#define IMX_ESD_BASE 0xb8001000 -#define IMX_AIPS1_BASE 0x43F00000 -#define IMX_AIPS2_BASE 0x53F00000 -#define IMX_CCM_BASE 0x53F80000 -#define IMX_IIM_BASE 0x53FF0000 -#define IMX_M3IF_BASE 0xB8003000 -#define IMX_NFC_BASE 0xBB000000 -#define IMX_FEC_BASE 0x50038000 -#define IMX_I2C1_BASE 0x43F80000 -#define IMX_I2C2_BASE 0x43F98000 -#define IMX_I2C3_BASE 0x43F84000 -#define IMX_CSPI1_BASE 0x43FA4000 -#define IMX_SDHC1_BASE 0x53FB4000 -#define IMX_SDHC2_BASE 0x53FB8000 -#define IMX_SDHC3_BASE 0x53FBC000 -#define IMX_IPU_BASE 0x53FC0000 -#define IMX_OTG_BASE 0x53FF4000 -#define IMX_WDOG_BASE 0x53fdc000 +#define MX35_IPU_MEM_BASE_ADDR 0x70000000 +#define MX35_CSD0_BASE_ADDR 0x80000000 +#define MX35_CSD1_BASE_ADDR 0x90000000 + +#define MX35_CS0_BASE_ADDR 0xa0000000 +#define MX35_CS1_BASE_ADDR 0xa8000000 +#define MX35_CS2_BASE_ADDR 0xb0000000 +#define MX35_CS3_BASE_ADDR 0xb2000000 + +#define MX35_CS4_BASE_ADDR 0xb4000000 +#define MX35_CS4_SIZE SZ_32M + +#define MX35_CS5_BASE_ADDR 0xb6000000 +#define MX35_CS5_SIZE SZ_32M + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MX35_X_MEMC_BASE_ADDR 0xb8000000 +#define MX35_X_MEMC_SIZE SZ_64K +#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) +#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) +#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) +#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) +#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR + +#define MX35_NFC_BASE_ADDR 0xbb000000 +#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +/* FIXME: Get rid of these */ +#define IMX_WDT_BASE MX35_WDOG_BASE_ADDR +#define IMX_TIM1_BASE MX35_GPT1_BASE_ADDR +#define IMX_ESD_BASE MX35_ESDCTL_BASE_ADDR +#define IMX_IOMUXC_BASE MX35_IOMUXC_BASE_ADDR +#define IMX_CCM_BASE MX35_CCM_BASE_ADDR +#define IMX_NFC_BASE MX35_NFC_BASE_ADDR /* * Clock Controller Module (CCM) @@ -88,28 +173,4 @@ #define PDR0_AUTO_CON (1 << 0) #define PDR0_PER_SEL (1 << 26) -/* - * Adresses and ranges of the external chip select lines - */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - #endif /* __ASM_ARCH_MX35_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h new file mode 100644 index 0000000000..8d572dc0bf --- /dev/null +++ b/arch/arm/mach-imx/include/mach/weim.h @@ -0,0 +1,20 @@ +#ifndef __MACH_WEIM_H +#define __MACH_WEIM_H + +void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional); + +void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional); + +void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional); + +void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, + unsigned additional); + +void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower); + +void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower); + +#endif /* __MACH_WEIM_H */ diff --git a/arch/arm/mach-imx/speed-imx1.c b/arch/arm/mach-imx/speed-imx1.c deleted file mode 100644 index 2b62f6168f..0000000000 --- a/arch/arm/mach-imx/speed-imx1.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * - * (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#include <common.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <init.h> -#include <driver.h> - -ulong imx_get_spllclk(void) -{ - return imx_decode_pll(SPCTL0, CONFIG_SYSPLL_CLK_FREQ); -} - -ulong imx_get_mpllclk(void) -{ - return imx_decode_pll(MPCTL0, CONFIG_SYSPLL_CLK_FREQ); -} - -ulong imx_get_fclk(void) -{ - return (( CSCR>>15)&1) ? imx_get_mpllclk()>>1 : imx_get_mpllclk(); -} - -ulong imx_get_hclk(void) -{ - u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - return imx_get_spllclk() / bclkdiv; -} - -ulong imx_get_bclk(void) -{ - return imx_get_hclk(); -} - -ulong imx_get_perclk1(void) -{ - return imx_get_spllclk() / (((PCDR) & 0xf)+1); -} - -ulong imx_get_perclk2(void) -{ - return imx_get_spllclk() / (((PCDR>>4) & 0xf)+1); -} - -ulong imx_get_perclk3(void) -{ - return imx_get_spllclk() / (((PCDR>>16) & 0x7f)+1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_get_perclk1(); -} - -void imx_dump_clocks(void) -{ - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("fclk: %10ld Hz\n", imx_get_fclk()); - printf("hclk: %10ld Hz\n", imx_get_hclk()); - printf("bclk: %10ld Hz\n", imx_get_bclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("uart: %10ld Hz\n", imx_get_uartclk()); - printf("gpt: %10ld Hz\n", imx_get_gptclk()); -} - diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c deleted file mode 100644 index b9ecd2fa70..0000000000 --- a/arch/arm/mach-imx/speed-imx21.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm-generic/errno.h> -#include <mach/imx-regs.h> -#include <mach/generic.h> -#include <mach/clock.h> -#include <init.h> - -#ifndef CLK32 -#define CLK32 32768 -#endif - -static ulong clk_in_32k(void) -{ - return 512 * CLK32; -} - -static ulong clk_in_26m(void) -{ - if (CSCR & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 173333333; - } else { - /* divide by 1 */ - return 26000000; - } -} - -ulong imx_get_mpllclk(void) -{ - ulong cscr = CSCR; - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(MPCTL0, fref); -} - -ulong imx_get_fclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 29) & 0x7) + 1; - - return fref / div; -} - -/* HCLK */ -ulong imx_get_armclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 10) & 0xF) + 1; - - return fref / div; -} - -ulong imx_get_spllclk(void) -{ - ulong cscr = CSCR; - ulong spctl0; - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - spctl0 = SPCTL0; - SPCTL0 = spctl0; - return imx_decode_pll(spctl0, fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return imx_get_mpllclk() / div; -} - -static ulong imx_get_nfcclk(void) -{ - ulong fref = imx_get_fclk(); - ulong div = ((PCDR0 >> 12) & 0xF) + 1; - return fref / div; -} - -ulong imx_get_perclk1(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_perclk2(void) -{ - return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1); -} - -ulong imx_get_perclk3(void) -{ - return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1); -} - -ulong imx_get_perclk4(void) -{ - return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_lcdclk(void) -{ - return imx_get_perclk3(); -} - -void imx_dump_clocks(void) -{ - uint32_t cid = CID; - - printf("chip id: [%08x]\n", cid); - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("fclk: %10ld Hz\n", imx_get_fclk()); - printf("nfcclk: %10ld Hz\n", imx_get_nfcclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("perclk4: %10ld Hz\n", imx_get_perclk4()); - printf("clkin26: %10ld Hz\n", clk_in_26m()); -} - -/* - * Set the divider of the CLKO pin (when CLK48DIV_CLKO is chosen). - * Returns the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - ulong pcdr; - - if (num != 1) - return -ENODEV; - - div--; - div &= 0x7; - - pcdr = PCDR0 & ~(7 << 5); - pcdr |= div << 5; - PCDR0 = pcdr; - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long ccsr; - - if (src < 0 || num != 1) { - return; - } - - ccsr = CCSR & ~0x1f; - ccsr |= src & 0x1f; - CCSR = ccsr; -} diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c deleted file mode 100644 index 39e68c85a4..0000000000 --- a/arch/arm/mach-imx/speed-imx25.c +++ /dev/null @@ -1,155 +0,0 @@ -#include <common.h> -#include <asm-generic/errno.h> -#include <mach/imx-regs.h> -#include <io.h> -#include <mach/clock.h> -#include <init.h> - -unsigned long imx_get_mpllclk(void) -{ - ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL); - return imx_decode_pll(mpctl, CONFIG_MX25_HCLK_FREQ); -} - -unsigned long imx_get_upllclk(void) -{ - ulong ppctl = readl(IMX_CCM_BASE + CCM_UPCTL); - return imx_decode_pll(ppctl, CONFIG_MX25_HCLK_FREQ); -} - -unsigned long imx_get_armclk(void) -{ - unsigned long rate, cctl; - - cctl = readl(IMX_CCM_BASE + CCM_CCTL); - rate = imx_get_mpllclk(); - - if (cctl & (1 << 14)) { - rate *= 3; - rate >>= 2; - } - - return rate / ((cctl >> 30) + 1); -} - -unsigned long imx_get_ahbclk(void) -{ - ulong cctl = readl(IMX_CCM_BASE + CCM_CCTL); - return imx_get_armclk() / (((cctl >> 28) & 0x3) + 1); -} - -unsigned long imx_get_ipgclk(void) -{ - return imx_get_ahbclk() / 2; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_perclk(int per) -{ - ulong ofs = (per & 0x3) * 8; - ulong reg = per & ~0x3; - ulong val = (readl(IMX_CCM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f; - ulong fref; - - if (readl(IMX_CCM_BASE + 0x64) & (1 << per)) - fref = imx_get_upllclk(); - else - fref = imx_get_ahbclk(); - - return fref / (val + 1); -} - -unsigned long imx_get_uartclk(void) -{ - return imx_get_perclk(15); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_lcdclk(void) -{ - return imx_get_perclk(7); -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_perclk(6); -} - -unsigned long imx_get_mmcclk(void) -{ - return imx_get_perclk(3); -} - -unsigned long imx_get_cspiclk(void) -{ - return imx_get_ipgclk(); -} - -void imx_dump_clocks(void) -{ - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("upll: %10ld Hz\n", imx_get_upllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("uart: %10ld Hz\n", imx_get_perclk(15)); - printf("gpt: %10ld Hz\n", imx_get_ipgclk()); - printf("nand: %10ld Hz\n", imx_get_perclk(8)); - printf("lcd: %10ld Hz\n", imx_get_perclk(7)); - printf("i2c: %10ld Hz\n", imx_get_perclk(6)); - printf("sdhc1: %10ld Hz\n", imx_get_perclk(3)); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - unsigned long mcr = readl(IMX_CCM_BASE + 0x64); - - if (num != 1) - return -ENODEV; - - div -= 1; - div &= 0x3f; - - mcr &= ~(0x3f << 24); - mcr |= div << 24; - - writel(mcr, IMX_CCM_BASE + 0x64); - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long mcr = readl(IMX_CCM_BASE + 0x64); - - if (num != 1) - return; - - if (src < 0) { - mcr &= ~(1 << 30); - writel(mcr, IMX_CCM_BASE + 0x64); - return; - } - - mcr |= 1 << 30; - mcr &= ~(0xf << 20); - mcr |= (src & 0xf) << 20; - - writel(mcr, IMX_CCM_BASE + 0x64); -} - diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c deleted file mode 100644 index 33ec4487b6..0000000000 --- a/arch/arm/mach-imx/speed-imx27.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm-generic/errno.h> -#include <mach/imx-regs.h> -#include <mach/generic.h> -#include <mach/clock.h> -#include <init.h> - -#ifndef CLK32 -#define CLK32 32000 -#endif - -static ulong clk_in_32k(void) -{ - return 1024 * CLK32; -} - -static ulong clk_in_26m(void) -{ - if (CSCR & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 173333333; - } else { - /* divide by 1 */ - return 26000000; - } -} - -ulong imx_get_mpllclk(void) -{ - ulong cscr = CSCR; - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(MPCTL0, fref); -} - -ulong imx_get_armclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL) && - (imx_silicon_revision() != IMX27_CHIP_REVISION_1_0)) - fref = (fref * 2) / 3; - - div = ((cscr >> 12) & 0x3) + 1; - - return fref / div; -} - -ulong imx_get_ahbclk(void) -{ - ulong cscr = CSCR; - ulong fref = imx_get_mpllclk(); - ulong div; - - if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0) - div = ((cscr >> 9) & 0xf) + 1; - else - div = ((cscr >> 8) & 0x3) + 1; - - return ((fref * 2) / 3) / div; -} - -ulong imx_get_ipgclk(void) -{ - ulong clk = imx_get_ahbclk(); - - return clk >> 1; -} - -ulong imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -ulong imx_get_spllclk(void) -{ - ulong cscr = CSCR; - ulong spctl0; - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - spctl0 = SPCTL0; - SPCTL0 = spctl0; - return imx_decode_pll(spctl0, fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - if (imx_silicon_revision() == IMX27_CHIP_REVISION_1_0) - return imx_get_mpllclk() / div; - else - return (imx_get_mpllclk() * 2) / (div * 3); -} - -ulong imx_get_perclk1(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_perclk2(void) -{ - return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1); -} - -ulong imx_get_perclk3(void) -{ - return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1); -} - -ulong imx_get_perclk4(void) -{ - return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_decode_perclk((PCDR1 & 0x3f) + 1); -} - -ulong imx_get_lcdclk(void) -{ - return imx_get_perclk3(); -} - -ulong fsl_get_i2cclk(void) -{ - return imx_get_ipgclk(); -} - -ulong imx_get_mmcclk(void) -{ - return imx_get_perclk2(); -} - -void imx_dump_clocks(void) -{ - uint32_t cid = CID; - - printf("chip id: [%d,%03x,%d,%03x]\n", - (cid >> 28) & 0xf, (cid >> 16) & 0xfff, - (cid >> 12) & 0xf, (cid >> 0) & 0xfff); - - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("spll: %10ld Hz\n", imx_get_spllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("perclk1: %10ld Hz\n", imx_get_perclk1()); - printf("perclk2: %10ld Hz\n", imx_get_perclk2()); - printf("perclk3: %10ld Hz\n", imx_get_perclk3()); - printf("perclk4: %10ld Hz\n", imx_get_perclk4()); - printf("clkin26: %10ld Hz\n", clk_in_26m()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("ipg: %10ld Hz\n", imx_get_ipgclk()); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - ulong pcdr; - - if (num != 1) - return -ENODEV; - - div--; - div &= 0x7; - - pcdr = PCDR0 & ~(7 << 22); - pcdr |= div << 22; - PCDR0 = pcdr; - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long ccsr; - - if (num != 1) - return; - - if (src < 0) { - PCDR0 &= ~(1 << 25); - return; - } - - ccsr = CCSR & ~0x1f; - ccsr |= src & 0x1f; - CCSR = ccsr; - - PCDR0 |= (1 << 25); -} - diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c deleted file mode 100644 index 64476b7c28..0000000000 --- a/arch/arm/mach-imx/speed-imx31.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <io.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <init.h> - -ulong imx_get_mpl_dpdgck_clk(void) -{ - ulong infreq; - - if ((readl(IMX_CCM_BASE + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; - else - infreq = CONFIG_MX31_HCLK_FREQ; - - return imx_decode_pll(readl(IMX_CCM_BASE + CCM_MPCTL), infreq); -} - -ulong imx_get_mcu_main_clk(void) -{ - /* For now we assume mpl_dpdgck_clk == mcu_main_clk - * which should be correct for most boards - */ - return imx_get_mpl_dpdgck_clk(); -} - -/** - * Calculate the current pixel clock speed (aka HSP or IPU) - * @return 0 on failure or current frequency in Hz - */ -ulong imx_get_lcdclk(void) -{ - ulong hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 11) & 0x03; - ulong base_clk = imx_get_mcu_main_clk(); - - return base_clk / (hsp_podf + 1); -} - -ulong imx_get_perclk1(void) -{ - u32 freq = imx_get_mcu_main_clk(); - u32 pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); - - freq /= ((pdr0 >> 3) & 0x7) + 1; - freq /= ((pdr0 >> 6) & 0x3) + 1; - - return freq; -} - -void imx_dump_clocks(void) -{ - ulong cpufreq = imx_get_mcu_main_clk(); - printf("mx31 cpu clock: %ldMHz\n",cpufreq / 1000000); - printf("ipg clock : %ldHz\n", imx_get_perclk1()); -} - -ulong imx_get_uartclk(void) -{ - return imx_get_perclk1(); -} - -ulong imx_get_gptclk(void) -{ - return imx_get_perclk1(); -} - diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c deleted file mode 100644 index a4e0120da5..0000000000 --- a/arch/arm/mach-imx/speed-imx35.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm-generic/errno.h> -#include <mach/imx-regs.h> -#include <io.h> -#include <mach/clock.h> -#include <mach/generic.h> -#include <init.h> - -unsigned long imx_get_mpllclk(void) -{ - ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL); - return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ); -} - -static unsigned long imx_get_ppllclk(void) -{ - ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL); - return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ); -} - -struct arm_ahb_div { - unsigned char arm, ahb, sel; -}; - -static struct arm_ahb_div clk_consumer[] = { - { .arm = 1, .ahb = 4, .sel = 0}, - { .arm = 1, .ahb = 3, .sel = 1}, - { .arm = 2, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 1, .sel = 0}, - { .arm = 1, .ahb = 5, .sel = 0}, - { .arm = 1, .ahb = 8, .sel = 0}, - { .arm = 1, .ahb = 6, .sel = 1}, - { .arm = 2, .ahb = 4, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, -}; - -static unsigned long imx_get_armclk(void) -{ - unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = imx_get_mpllclk(); - - /* consumer path is selected */ - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 3 / 4; - - return fref / aad->arm; -} - -unsigned long imx_get_ahbclk(void) -{ - unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); - struct arm_ahb_div *aad; - unsigned long fref = imx_get_mpllclk(); - - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 3 / 4; - - return fref / aad->ahb; -} - -unsigned long imx_get_ipgclk(void) -{ - ulong clk = imx_get_ahbclk(); - - return clk >> 1; -} - -static unsigned long get_3_3_div(unsigned long in) -{ - return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); -} - -static unsigned long get_6_div(unsigned long in) -{ - return ((in & 0x3f) + 1); -} - -static unsigned long imx_get_ipg_perclk(void) -{ - ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); - ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4); - ulong div; - ulong fref; - - if (pdr0 & PDR0_PER_SEL) { - /* perclk from arm high frequency clock and synched with AHB clki */ - fref = imx_get_armclk(); - div = get_3_3_div((pdr4 >> 16)); - } else { - /* perclk from AHB divided clock */ - fref = imx_get_ahbclk(); - div = ((pdr0 >> 12) & 0x7) + 1; - } - - return fref / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -/** - * Calculate the current pixel clock speed (aka HSP or IPU) - * @return 0 on failure or current frequency in Hz - */ -unsigned long imx_get_lcdclk(void) -{ - unsigned long hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 20) & 0x03; - unsigned long base_clk = imx_get_armclk(); - - if (base_clk > 400 * 1000 * 1000) { - switch(hsp_podf) { - case 0: - return base_clk >> 2; - case 1: - return base_clk >> 3; - case 2: - return base_clk / 3; - } - } else { - switch(hsp_podf) { - case 0: - case 2: - return base_clk / 3; - case 1: - return base_clk / 6; - } - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3); - unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4); - unsigned long div = get_3_3_div(pdr4 >> 10); - - if (pdr3 & (1 << 14)) - return imx_get_armclk() / div; - else - return imx_get_ppllclk() / div; -} - -/* mmc0 clk only */ -unsigned long imx_get_mmcclk(void) -{ - unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3); - unsigned long div = get_6_div(pdr3); - - if (pdr3 & (1 << 6)) - return imx_get_armclk() / div; - else - return imx_get_ppllclk() / div; -} - -ulong imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -ulong fsl_get_i2cclk(void) -{ - return imx_get_ipg_perclk(); -} - -unsigned long imx_get_cspiclk(void) -{ - return imx_get_ipgclk(); -} - -void imx_dump_clocks(void) -{ - printf("mpll: %10ld Hz\n", imx_get_mpllclk()); - printf("ppll: %10ld Hz\n", imx_get_ppllclk()); - printf("arm: %10ld Hz\n", imx_get_armclk()); - printf("gpt: %10ld Hz\n", imx_get_gptclk()); - printf("ahb: %10ld Hz\n", imx_get_ahbclk()); - printf("ipg: %10ld Hz\n", imx_get_ipgclk()); - printf("ipg_per: %10ld Hz\n", imx_get_ipg_perclk()); - printf("uart: %10ld Hz\n", imx_get_uartclk()); - printf("sdhc1: %10ld Hz\n", imx_get_mmcclk()); -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); - - if (num != 1) - return -ENODEV; - - div -= 1; - div &= 0x3f; - - cosr &= ~(0x3f << 10); - cosr |= div << 10; - - writel(cosr, IMX_CCM_BASE + CCM_COSR); - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); - - if (num != 1) - return; - - if (src < 0) { - cosr &= ~(1 << 5); - writel(cosr, IMX_CCM_BASE + CCM_COSR); - return; - } - - cosr |= 1 << 5; - cosr &= ~0x1f; - cosr &= ~(1 << 6); - cosr |= src & 0x1f; - - writel(cosr, IMX_CCM_BASE + CCM_COSR); -} - diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c deleted file mode 100644 index 3903afc821..0000000000 --- a/arch/arm/mach-imx/speed-imx51.c +++ /dev/null @@ -1,311 +0,0 @@ -#include <common.h> -#include <io.h> -#include <asm-generic/div64.h> -#include <asm-generic/errno.h> -#include <mach/imx51-regs.h> -#include <mach/clock.h> -#include <mach/clock-imx51_53.h> - -static u32 ccm_readl(u32 ofs) -{ - return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs); -} - -static void ccm_writel(u32 val, u32 ofs) -{ - writel(val, MX51_CCM_BASE_ADDR + ofs); -} - -static unsigned long ckil_get_rate(void) -{ - return 32768; -} - -static unsigned long osc_get_rate(void) -{ - return 24000000; -} - -static unsigned long fpm_get_rate(void) -{ - return ckil_get_rate() * 512; -} - -static unsigned long lp_apm_get_rate(void) -{ - if (ccm_readl(MX5_CCM_CCSR) & MX5_CCM_CCSR_LP_APM_SEL) - return fpm_get_rate(); - else - return osc_get_rate(); -} - -static unsigned long pll_get_rate(void __iomem *pllbase) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - u64 temp; - unsigned long parent_rate; - - dp_ctl = readl(pllbase + MX5_PLL_DP_CTL); - - if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - parent_rate = fpm_get_rate(); - else - parent_rate = osc_get_rate(); - - pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = readl(pllbase + MX5_PLL_DP_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_MFN); - } else { - dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN); - } - pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MX5_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64)ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static unsigned long pll1_main_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR); -} - -static unsigned long pll2_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR); -} - -static unsigned long pll3_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR); -} - -static unsigned long get_rate_select(int select, - unsigned long (* get_rate1)(void), - unsigned long (* get_rate2)(void), - unsigned long (* get_rate3)(void), - unsigned long (* get_rate4)(void)) -{ - switch (select) { - case 0: - return get_rate1 ? get_rate1() : 0; - case 1: - return get_rate2 ? get_rate2() : 0; - case 2: - return get_rate3 ? get_rate3() : 0; - case 3: - return get_rate4 ? get_rate4() : 0; - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; - - parent_rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -unsigned long imx_get_ahbclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 10) & 0x7) + 1; - - return pll2_sw_get_rate() / div; -} - -unsigned long imx_get_ipgclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 8) & 0x3) + 1; - - return imx_get_ahbclk() / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_mmcclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_usbclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - lp_apm_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_cspiclk(void) -{ - return 166000000; /* FIXME: bogus value */ -} - -/* - * Set the divider of the CLKO pin. Returns - * the new divider (which may be smaller - * than the desired one) - */ -int imx_clko_set_div(int num, int div) -{ - u32 ccosr = ccm_readl(MX5_CCM_CCOSR); - - div--; - - switch (num) { - case 1: - div &= 0x7; - ccosr &= ~(0x7 << 4); - ccosr |= div << 4; - ccm_writel(ccosr, MX5_CCM_CCOSR); - break; - case 2: - div &= 0x7; - ccosr &= ~(0x7 << 21); - ccosr |= div << 21; - ccm_writel(ccosr, MX5_CCM_CCOSR); - break; - default: - return -ENODEV; - } - - return div + 1; -} - -/* - * Set the clock source for the CLKO pin - */ -void imx_clko_set_src(int num, int src) -{ - u32 ccosr = ccm_readl(MX5_CCM_CCOSR); - - switch (num) { - case 1: - if (src < 0) { - ccosr &= ~(1 << 7); - break; - } - ccosr &= ~0xf; - ccosr |= src & 0xf; - ccosr |= 1 << 7; - break; - case 2: - if (src < 0) { - ccosr &= ~(1 << 24); - break; - } - ccosr &= ~(0x1f << 16); - ccosr |= (src & 0x1f) << 16; - ccosr |= 1 << 24; - break; - default: - return; - } - - ccm_writel(ccosr, MX5_CCM_CCOSR); -} - -void imx_dump_clocks(void) -{ - printf("pll1: %ld\n", pll1_main_get_rate()); - printf("pll2: %ld\n", pll2_sw_get_rate()); - printf("pll3: %ld\n", pll3_sw_get_rate()); - printf("lp_apm: %ld\n", lp_apm_get_rate()); - printf("uart: %ld\n", imx_get_uartclk()); - printf("ipg: %ld\n", imx_get_ipgclk()); - printf("fec: %ld\n", imx_get_fecclk()); - printf("gpt: %ld\n", imx_get_gptclk()); - printf("usb: %ld\n", imx_get_usbclk()); -} diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c deleted file mode 100644 index b1ba5fd1d2..0000000000 --- a/arch/arm/mach-imx/speed-imx53.c +++ /dev/null @@ -1,236 +0,0 @@ -#include <common.h> -#include <io.h> -#include <asm-generic/div64.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include "mach/clock-imx51_53.h" - -static u32 ccm_readl(u32 ofs) -{ - return readl(MX53_CCM_BASE_ADDR + ofs); -} - -static unsigned long ckil_get_rate(void) -{ - return 32768; -} - -static unsigned long osc_get_rate(void) -{ - return 24000000; -} - -static unsigned long fpm_get_rate(void) -{ - return ckil_get_rate() * 512; -} - -static unsigned long pll_get_rate(void __iomem *pllbase) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - u64 temp; - unsigned long parent_rate; - - dp_ctl = readl(pllbase + MX5_PLL_DP_CTL); - - if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - parent_rate = fpm_get_rate(); - else - parent_rate = osc_get_rate(); - - pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = readl(pllbase + MX5_PLL_DP_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_MFN); - } else { - dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP); - dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD); - dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN); - } - pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MX5_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64)ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static unsigned long pll1_main_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR); -} - -static unsigned long pll2_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR); -} - -static unsigned long pll3_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR); -} - -static unsigned long pll4_sw_get_rate(void) -{ - return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR); -} - -static unsigned long get_rate_select(int select, - unsigned long (* get_rate1)(void), - unsigned long (* get_rate2)(void), - unsigned long (* get_rate3)(void), - unsigned long (* get_rate4)(void)) -{ - switch (select) { - case 0: - return get_rate1 ? get_rate1() : 0; - case 1: - return get_rate2 ? get_rate2() : 0; - case 2: - return get_rate3 ? get_rate3() : 0; - case 3: - return get_rate4 ? get_rate4() : 0; - } - - return 0; -} - -unsigned long imx_get_uartclk(void) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; - - parent_rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - pll4_sw_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -unsigned long imx_get_ahbclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 10) & 0x7) + 1; - - return pll2_sw_get_rate() / div; -} - -unsigned long imx_get_ipgclk(void) -{ - u32 reg, div; - - reg = ccm_readl(MX5_CCM_CBCDR); - div = ((reg >> 8) & 0x3) + 1; - - return imx_get_ahbclk() / div; -} - -unsigned long imx_get_gptclk(void) -{ - return imx_get_ipgclk(); -} - -unsigned long imx_get_fecclk(void) -{ - return imx_get_ipgclk(); -} - -static unsigned long imx_get_ipg_perclk(void) -{ - u32 reg; - - reg = ccm_readl(MX5_CCM_CBCDR); - if (!(reg & MX5_CCM_CBCDR_PERIPH_CLK_SEL)) - return pll2_sw_get_rate(); - reg = ccm_readl(MX5_CCM_CBCMR); - switch ((reg & MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> - MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { - case 0: - return pll1_main_get_rate(); - case 1: - return pll3_sw_get_rate(); - /* case 2: - TODO : LP_APM */ - } - return 0; -} - -unsigned long fsl_get_i2cclk(void) -{ - return imx_get_ipg_perclk(); -} - -unsigned long imx_get_mmcclk(void) -{ - u32 reg, prediv, podf, rate; - - reg = ccm_readl(MX5_CCM_CSCMR1); - reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; - reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; - rate = get_rate_select(reg, - pll1_main_get_rate, - pll2_sw_get_rate, - pll3_sw_get_rate, - pll4_sw_get_rate); - - reg = ccm_readl(MX5_CCM_CSCDR1); - prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; - podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> - MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; - - return rate / (prediv * podf); -} - -unsigned long imx_get_cspiclk(void) -{ - return 166000000; /* FIXME: bogus value */ -} - -void imx_dump_clocks(void) -{ - printf("pll1: %ld\n", pll1_main_get_rate()); - printf("pll2: %ld\n", pll2_sw_get_rate()); - printf("pll3: %ld\n", pll3_sw_get_rate()); - printf("pll4: %ld\n", pll4_sw_get_rate()); - printf("uart: %ld\n", imx_get_uartclk()); - printf("ipg: %ld\n", imx_get_ipgclk()); - printf("fec: %ld\n", imx_get_fecclk()); - printf("gpt: %ld\n", imx_get_gptclk()); - printf("i2c: %ld\n", fsl_get_i2cclk()); -} diff --git a/arch/arm/mach-imx/speed-imx6.c b/arch/arm/mach-imx/speed-imx6.c deleted file mode 100644 index 645b2c9735..0000000000 --- a/arch/arm/mach-imx/speed-imx6.c +++ /dev/null @@ -1,404 +0,0 @@ -#include <common.h> -#include <asm/io.h> -#include <asm-generic/div64.h> -#include <mach/imx-regs.h> -#include <mach/clock-imx6.h> -#include <mach/imx6-anadig.h> - -enum pll_clocks { - CPU_PLL1, /* System PLL */ - BUS_PLL2, /* System Bus PLL*/ - USBOTG_PLL3, /* OTG USB PLL */ - AUD_PLL4, /* Audio PLL */ - VID_PLL5, /* Video PLL */ - MLB_PLL6, /* MLB PLL */ - USBHOST_PLL7, /* Host USB PLL */ - ENET_PLL8, /* ENET PLL */ -}; - -#define SZ_DEC_1M 1000000 - -/* Out-of-reset PFDs and clock source definitions */ -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - -#define AHB_CLK_ROOT 132000000 -#define IPG_CLK_ROOT 66000000 -#define ENET_FREQ_0 25000000 -#define ENET_FREQ_1 50000000 -#define ENET_FREQ_2 100000000 -#define ENET_FREQ_3 125000000 - -#define CONFIG_MX6_HCLK_FREQ 24000000 - -static u32 __decode_pll(enum pll_clocks pll, u32 infreq) -{ - u32 div; - - switch (pll) { - case CPU_PLL1: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_SYS) & - BM_ANADIG_PLL_SYS_DIV_SELECT; - return infreq * (div >> 1); - case BUS_PLL2: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_528) & - BM_ANADIG_PLL_528_DIV_SELECT; - return infreq * (20 + (div << 1)); - case USBOTG_PLL3: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_USB2_PLL_480_CTRL) & - BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT; - return infreq * (20 + (div << 1)); - case ENET_PLL8: - div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_ENET) & - BM_ANADIG_PLL_ENET_DIV_SELECT; - switch (div) { - default: - case 0: - return ENET_FREQ_0; - case 1: - return ENET_FREQ_1; - case 2: - return ENET_FREQ_2; - case 3: - return ENET_FREQ_3; - } - case AUD_PLL4: - case VID_PLL5: - case MLB_PLL6: - case USBHOST_PLL7: - default: - return 0; - } -} - -static u32 __get_mcu_main_clk(void) -{ - u32 reg, freq; - reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >> - MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ); - return freq / (reg + 1); -} - -static u32 __get_periph_clk(void) -{ - u32 reg; - reg = __REG(MXC_CCM_CBCDR); - if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { - reg = __REG(MXC_CCM_CBCMR); - switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >> - MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) { - case 0: - return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - case 1: - case 2: - return CONFIG_MX6_HCLK_FREQ; - default: - return 0; - } - } else { - reg = __REG(MXC_CCM_CBCMR); - switch ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) >> - MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) { - default: - case 0: - return __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - case 1: - return PLL2_PFD2_FREQ; - case 2: - return PLL2_PFD0_FREQ; - case 3: - return PLL2_PFD2_DIV_FREQ; - } - } -} - -static u32 __get_ipg_clk(void) -{ - u32 ahb_podf, ipg_podf; - - ahb_podf = __REG(MXC_CCM_CBCDR); - ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> - MXC_CCM_CBCDR_IPG_PODF_OFFSET; - ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET; - return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); -} - -u32 imx_get_gptclk(void) -{ - return __get_ipg_clk(); -} - -static u32 __get_ipg_per_clk(void) -{ - u32 podf; - u32 clk_root = __get_ipg_clk(); - - podf = __REG(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; - return clk_root / (podf + 1); -} - -u32 imx_get_uartclk(void) -{ - u32 freq = PLL3_80M, reg, podf; - - reg = __REG(MXC_CCM_CSCDR1); - podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; - freq /= (podf + 1); - - return freq; -} - -static u32 __get_cspi_clk(void) -{ - u32 freq = PLL3_60M, reg, podf; - - reg = __REG(MXC_CCM_CSCDR2); - podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> - MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - freq /= (podf + 1); - - return freq; -} - -static u32 __get_axi_clk(void) -{ - u32 clkroot; - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK) >> - MXC_CCM_CBCDR_AXI_PODF_OFFSET; - - if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { - if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - clkroot = PLL2_PFD2_FREQ; - else - clkroot = PLL3_PFD1_FREQ;; - } else - clkroot = __get_periph_clk(); - - return clkroot / (podf + 1); -} - -static u32 __get_ahb_clk(void) -{ - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ - >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; - - return __get_periph_clk() / (podf + 1); -} - -static u32 __get_emi_slow_clk(void) -{ - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >> - MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; - u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >> - MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; - - switch (emi_clk_sel) { - default: - case 0: - return __get_axi_clk() / (podf + 1); - case 1: - return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ) / - (podf + 1); - case 2: - return PLL2_PFD2_FREQ / (podf + 1); - case 3: - return PLL2_PFD0_FREQ / (podf + 1); - } -} - -static u32 __get_nfc_clk(void) -{ - u32 clkroot; - u32 cs2cdr = __REG(MXC_CCM_CS2CDR); - u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) \ - >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET; - u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) \ - >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET; - - switch ((cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >> - MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) { - default: - case 0: - clkroot = PLL2_PFD0_FREQ; - break; - case 1: - clkroot = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - break; - case 2: - clkroot = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - break; - case 3: - clkroot = PLL2_PFD2_FREQ; - break; - } - - return clkroot / (pred+1) / (podf+1); -} - -static u32 __get_ddr_clk(void) -{ - u32 cbcdr = __REG(MXC_CCM_CBCDR); - u32 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> - MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; - - return __get_periph_clk() / (podf + 1); -} - -static u32 __get_usdhc1_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc2_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc3_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -static u32 __get_usdhc4_clk(void) -{ - u32 clkroot; - u32 cscmr1 = __REG(MXC_CCM_CSCMR1); - u32 cscdr1 = __REG(MXC_CCM_CSCDR1); - u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> - MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; - - if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL) - clkroot = PLL2_PFD0_FREQ; - else - clkroot = PLL2_PFD2_FREQ; - - return clkroot / (podf + 1); -} - -u32 imx_get_mmcclk(void) -{ - return __get_usdhc3_clk(); -} - -u32 imx_get_fecclk(void) -{ - return __get_ipg_clk(); -} - -u32 imx_get_i2cclk(void) -{ - return __get_ipg_per_clk(); -} - -u32 imx_get_cspiclk(void) -{ - return __get_cspi_clk(); -} - -void imx_dump_clocks(void) -{ - u32 freq; - - freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll1: %d\n", freq); - freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll2: %d\n", freq); - freq = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll3: %d\n", freq); - freq = __decode_pll(ENET_PLL8, CONFIG_MX6_HCLK_FREQ); - printf("mx6q pll8: %d\n", freq); - printf("mcu main: %d\n", __get_mcu_main_clk()); - printf("periph: %d\n", __get_periph_clk()); - printf("i2c: %d\n", __get_ipg_per_clk()); - printf("ipg: %d\n", __get_ipg_clk()); - printf("ipg per: %d\n", __get_ipg_per_clk()); - printf("cspi: %d\n", __get_cspi_clk()); - printf("axi: %d\n", __get_axi_clk()); - printf("ahb: %d\n", __get_ahb_clk()); - printf("emi slow: %d\n", __get_emi_slow_clk()); - printf("nfc: %d\n", __get_nfc_clk()); - printf("ddr: %d\n", __get_ddr_clk()); - printf("usdhc1: %d\n", __get_usdhc1_clk()); - printf("usdhc2: %d\n", __get_usdhc2_clk()); - printf("usdhc3: %d\n", __get_usdhc3_clk()); - printf("usdhc4: %d\n", __get_usdhc4_clk()); -} - -void imx6_ipu_clk_enable(int di) -{ - u32 reg; - - if (di == 1) { - reg = readl(MXC_CCM_CCGR3); - reg |= 0xC033; - writel(reg, MXC_CCM_CCGR3); - } else { - reg = readl(MXC_CCM_CCGR3); - reg |= 0x300F; - writel(reg, MXC_CCM_CCGR3); - } - - reg = readl(MX6_ANATOP_BASE_ADDR + 0xF0); - reg &= ~0x00003F00; - reg |= 0x00001300; - writel(reg, MX6_ANATOP_BASE_ADDR + 0xF4); - - reg = readl(MXC_CCM_CS2CDR); - reg &= ~0x00007E00; - reg |= 0x00001200; - writel(reg, MXC_CCM_CS2CDR); - - reg = readl(MXC_CCM_CSCMR2); - reg |= 0x00000C00; - writel(reg, MXC_CCM_CSCMR2); - - reg = 0x0002A953; - writel(reg, MXC_CCM_CHSCDR); -} diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h index ade3139596..7fb664b334 100644 --- a/arch/arm/mach-mxs/include/mach/imx23-regs.h +++ b/arch/arm/mach-mxs/include/mach/imx23-regs.h @@ -15,13 +15,6 @@ #ifndef __ASM_ARCH_MX23_REGS_H #define __ASM_ARCH_MX23_REGS_H -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - #define IMX_MEMORY_BASE 0x40000000 #define MXS_APBH_BASE 0x80004000 #define MXS_BCH_BASE 0x8000a000 diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h index 16bf5f7a60..fa8edd7d4b 100644 --- a/arch/arm/mach-mxs/include/mach/imx28-regs.h +++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h @@ -13,13 +13,6 @@ #ifndef __ASM_ARCH_MX28_REGS_H #define __ASM_ARCH_MX28_REGS_H -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - #define IMX_SRAM_BASE 0x00000000 #define IMX_MEMORY_BASE 0x40000000 diff --git a/commands/Kconfig b/commands/Kconfig index 1561315633..cf4142008b 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -613,6 +613,14 @@ config CMD_USB help The usb command allows to rescan for USB devices. +config CMD_CLK + tristate + depends on COMMON_CLK + prompt "clock manipulation commands" + help + Say yes here to get clk_set_rate, clk_set_parent and clk_dump + commands to manipulate clocks on your system. + menuconfig CMD_WD bool depends on WATCHDOG diff --git a/commands/Makefile b/commands/Makefile index bd2dfaa735..610be55c6a 100644 --- a/commands/Makefile +++ b/commands/Makefile @@ -74,4 +74,5 @@ obj-$(CONFIG_CMD_BASENAME) += basename.o obj-$(CONFIG_CMD_DIRNAME) += dirname.o obj-$(CONFIG_CMD_READLINK) += readlink.o obj-$(CONFIG_CMD_LN) += ln.o +obj-$(CONFIG_CMD_CLK) += clk.o obj-$(CONFIG_CMD_TFTP) += tftp.o diff --git a/commands/clk.c b/commands/clk.c new file mode 100644 index 0000000000..241dc79c36 --- /dev/null +++ b/commands/clk.c @@ -0,0 +1,144 @@ +#include <common.h> +#include <command.h> +#include <getopt.h> +#include <linux/clk.h> +#include <linux/err.h> + +static int do_clk_enable(int argc, char *argv[]) +{ + struct clk *clk; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + clk = clk_lookup(argv[1]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + return clk_enable(clk); +} + +BAREBOX_CMD_HELP_START(clk_enable) +BAREBOX_CMD_HELP_USAGE("clk_enable <clk>\n") +BAREBOX_CMD_HELP_SHORT("enable <clk>\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_enable) + .cmd = do_clk_enable, + .usage = "enable a clock", + BAREBOX_CMD_HELP(cmd_clk_enable_help) +BAREBOX_CMD_END + +static int do_clk_disable(int argc, char *argv[]) +{ + struct clk *clk; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + clk = clk_lookup(argv[1]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + clk_disable(clk); + + return 0; +} + +BAREBOX_CMD_HELP_START(clk_disable) +BAREBOX_CMD_HELP_USAGE("clk_disable <clk>\n") +BAREBOX_CMD_HELP_SHORT("disable <clk>\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_disable) + .cmd = do_clk_disable, + .usage = "disable a clock", + BAREBOX_CMD_HELP(cmd_clk_disable_help) +BAREBOX_CMD_END + +static int do_clk_set_rate(int argc, char *argv[]) +{ + struct clk *clk; + unsigned long rate; + + if (argc != 3) + return COMMAND_ERROR_USAGE; + + clk = clk_lookup(argv[1]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate = simple_strtoul(argv[2], NULL, 0); + + return clk_set_rate(clk, rate); +} + +BAREBOX_CMD_HELP_START(clk_set_rate) +BAREBOX_CMD_HELP_USAGE("clk_set_rate <clk> <rate_hz>\n") +BAREBOX_CMD_HELP_SHORT("Set clock <clk> to <rate>\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_set_rate) + .cmd = do_clk_set_rate, + .usage = "set a clocks rate", + BAREBOX_CMD_HELP(cmd_clk_set_rate_help) +BAREBOX_CMD_END + +static int do_clk_dump(int argc, char *argv[]) +{ + int opt, verbose = 0; + + while ((opt = getopt(argc, argv, "v")) > 0) { + switch(opt) { + case 'v': + verbose = 1; + break; + default: + return -EINVAL; + + } + } + + clk_dump(verbose); + + return 0; +} + +BAREBOX_CMD_HELP_START(clk_dump) +BAREBOX_CMD_HELP_USAGE("clk_dump [-v]\n") +BAREBOX_CMD_HELP_OPT ("-v", "verbose\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_dump) + .cmd = do_clk_dump, + .usage = "show information about registered clocks", + BAREBOX_CMD_HELP(cmd_clk_dump_help) +BAREBOX_CMD_END + +static int do_clk_set_parent(int argc, char *argv[]) +{ + struct clk *clk, *parent; + + if (argc != 3) + return COMMAND_ERROR_USAGE; + + clk = clk_lookup(argv[1]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + parent = clk_lookup(argv[2]); + if (IS_ERR(parent)) + return PTR_ERR(parent); + + return clk_set_parent(clk, parent); +} + +BAREBOX_CMD_HELP_START(clk_set_parent) +BAREBOX_CMD_HELP_USAGE("clk_set_parent <clk> <parent>\n") +BAREBOX_CMD_HELP_SHORT("Set parent of <clk> to <parent>\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_set_parent) + .cmd = do_clk_set_parent, + .usage = "set a parent of a clock", + BAREBOX_CMD_HELP(cmd_clk_set_parent_help) +BAREBOX_CMD_END diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4168c8896e..66c1c465e8 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -2,3 +2,6 @@ config CLKDEV_LOOKUP bool select HAVE_CLK + +config COMMON_CLK + bool diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 07613fa172..39a75a4e4a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -1,2 +1,2 @@ - +obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o clk-mux.o obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c new file mode 100644 index 0000000000..58a7ea564c --- /dev/null +++ b/drivers/clk/clk-divider.c @@ -0,0 +1,98 @@ +/* + * clk-divider.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/err.h> + +struct clk_divider { + struct clk clk; + u8 shift; + u8 width; + void __iomem *reg; + const char *parent; +}; + +static int clk_divider_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *div = container_of(clk, struct clk_divider, clk); + unsigned int val, divval; + + if (rate > parent_rate) + rate = parent_rate; + if (!rate) + rate = 1; + + divval = DIV_ROUND_UP(parent_rate, rate); + + if (divval > (1 << div->width)) + divval = 1 << (div->width); + + divval--; + + val = readl(div->reg); + val &= ~(((1 << div->width) - 1) << div->shift); + val |= divval << div->shift; + writel(val, div->reg); + + return 0; +} + +static unsigned long clk_divider_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_divider *div = container_of(clk, struct clk_divider, clk); + unsigned int val; + + val = readl(div->reg) >> div->shift; + val &= (1 << div->width) - 1; + + val++; + + return parent_rate / val; +} + +struct clk_ops clk_divider_ops = { + .set_rate = clk_divider_set_rate, + .recalc_rate = clk_divider_recalc_rate, +}; + +struct clk *clk_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width) +{ + struct clk_divider *div = xzalloc(sizeof(*div)); + int ret; + + div->shift = shift; + div->reg = reg; + div->width = width; + div->parent = parent; + div->clk.ops = &clk_divider_ops; + div->clk.name = name; + div->clk.parent_names = &div->parent; + div->clk.num_parents = 1; + + ret = clk_register(&div->clk); + if (ret) { + free(div); + return ERR_PTR(ret); + } + + return &div->clk; +} diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c new file mode 100644 index 0000000000..52e7c16c49 --- /dev/null +++ b/drivers/clk/clk-fixed-factor.c @@ -0,0 +1,63 @@ +/* + * clk-fixed-factor.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/err.h> + +struct clk_fixed_factor { + struct clk clk; + int mult; + int div; + const char *parent; +}; + +static unsigned long clk_fixed_factor_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_fixed_factor *f = container_of(clk, struct clk_fixed_factor, clk); + + return (parent_rate / f->div) * f->mult; +} + +struct clk_ops clk_fixed_factor_ops = { + .recalc_rate = clk_fixed_factor_recalc_rate, +}; + +struct clk *clk_fixed_factor(const char *name, + const char *parent, unsigned int mult, unsigned int div) +{ + struct clk_fixed_factor *f = xzalloc(sizeof(*f)); + int ret; + + f->mult = mult; + f->div = div; + f->parent = parent; + f->clk.ops = &clk_fixed_factor_ops; + f->clk.name = name; + f->clk.parent_names = &f->parent; + f->clk.num_parents = 1; + + ret = clk_register(&f->clk); + if (ret) { + free(f); + return ERR_PTR(ret); + } + + return &f->clk; +} diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c new file mode 100644 index 0000000000..fa89cb2840 --- /dev/null +++ b/drivers/clk/clk-fixed.c @@ -0,0 +1,55 @@ +/* + * clk-fixed.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/err.h> + +struct clk_fixed { + struct clk clk; + unsigned long rate; +}; + +static unsigned long clk_fixed_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_fixed *fix = container_of(clk, struct clk_fixed, clk); + + return fix->rate; +} + +struct clk_ops clk_fixed_ops = { + .recalc_rate = clk_fixed_recalc_rate, +}; + +struct clk *clk_fixed(const char *name, int rate) +{ + struct clk_fixed *fix = xzalloc(sizeof *fix); + int ret; + + fix->rate = rate; + fix->clk.ops = &clk_fixed_ops; + fix->clk.name = name; + + ret = clk_register(&fix->clk); + if (ret) { + free(fix); + return ERR_PTR(ret); + } + + return &fix->clk; +} diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c new file mode 100644 index 0000000000..cb5f1a1a7b --- /dev/null +++ b/drivers/clk/clk-mux.c @@ -0,0 +1,77 @@ +/* + * clk-mux.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/err.h> + +struct clk_mux { + struct clk clk; + void __iomem *reg; + int shift; + int width; +}; + +static int clk_mux_get_parent(struct clk *clk) +{ + struct clk_mux *m = container_of(clk, struct clk_mux, clk); + int idx = readl(m->reg) >> m->shift & ((1 << m->width) - 1); + + return idx; +} + +static int clk_mux_set_parent(struct clk *clk, u8 idx) +{ + struct clk_mux *m = container_of(clk, struct clk_mux, clk); + u32 val; + + val = readl(m->reg); + val &= ~(((1 << m->width) - 1) << m->shift); + val |= idx << m->shift; + writel(val, m->reg); + + return 0; +} + +struct clk_ops clk_mux_ops = { + .get_parent = clk_mux_get_parent, + .set_parent = clk_mux_set_parent, +}; + +struct clk *clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, u8 num_parents) +{ + struct clk_mux *m = xzalloc(sizeof(*m)); + int ret; + + m->reg = reg; + m->shift = shift; + m->width = width; + m->clk.ops = &clk_mux_ops; + m->clk.name = name; + m->clk.parent_names = parents; + m->clk.num_parents = num_parents; + + ret = clk_register(&m->clk); + if (ret) { + free(m); + return ERR_PTR(ret); + } + + return &m->clk; +} diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c new file mode 100644 index 0000000000..bf61e5db94 --- /dev/null +++ b/drivers/clk/clk.c @@ -0,0 +1,224 @@ +/* + * clk.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <errno.h> +#include <linux/clk.h> +#include <linux/err.h> + +static LIST_HEAD(clks); + +static int clk_parent_enable(struct clk *clk) +{ + struct clk *parent = clk_get_parent(clk); + + if (!IS_ERR_OR_NULL(parent)) + return clk_enable(parent); + + return 0; +} + +static void clk_parent_disable(struct clk *clk) +{ + struct clk *parent = clk_get_parent(clk); + + if (!IS_ERR_OR_NULL(parent)) + clk_disable(parent); +} + +int clk_enable(struct clk *clk) +{ + int ret; + + if (!clk->enable_count) { + ret = clk_parent_enable(clk); + if (ret) + return ret; + + if (clk->ops->enable) { + ret = clk->ops->enable(clk); + if (ret) { + clk_parent_disable(clk); + return ret; + } + } + } + + clk->enable_count++; + + return 0; +} + +void clk_disable(struct clk *clk) +{ + if (!clk->enable_count) + return; + + clk->enable_count--; + + if (!clk->enable_count) { + if (clk->ops->disable) + clk->ops->disable(clk); + + clk_parent_disable(clk); + } +} + +unsigned long clk_get_rate(struct clk *clk) +{ + struct clk *parent; + unsigned long parent_rate = 0; + + parent = clk_get_parent(clk); + if (!IS_ERR_OR_NULL(parent)) + parent_rate = clk_get_rate(parent); + + if (clk->ops->recalc_rate) + return clk->ops->recalc_rate(clk, parent_rate); + + return parent_rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return clk_get_rate(clk); +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *parent; + unsigned long parent_rate = 0; + + parent = clk_get_parent(clk); + if (parent) + parent_rate = clk_get_rate(parent); + + if (clk->ops->set_rate) + return clk->ops->set_rate(clk, rate, parent_rate); + + return -ENOSYS; +} + +struct clk *clk_lookup(const char *name) +{ + struct clk *c; + + if (!name) + return ERR_PTR(-ENODEV); + + list_for_each_entry(c, &clks, list) { + if (!strcmp(c->name, name)) + return c; + } + + return ERR_PTR(-ENODEV); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int i; + + if (!clk->num_parents) + return -EINVAL; + if (!clk->ops->set_parent) + return -EINVAL; + + for (i = 0; i < clk->num_parents; i++) { + if (IS_ERR_OR_NULL(clk->parents[i])) + clk->parents[i] = clk_lookup(clk->parent_names[i]); + + if (!IS_ERR_OR_NULL(clk->parents[i])) + if (clk->parents[i] == parent) + break; + } + + if (i == clk->num_parents) + return -EINVAL; + + return clk->ops->set_parent(clk, i); +} + +struct clk *clk_get_parent(struct clk *clk) +{ + int idx; + + if (!clk->num_parents) + return ERR_PTR(-ENODEV); + + if (clk->num_parents != 1) { + if (!clk->ops->get_parent) + return ERR_PTR(-EINVAL); + + idx = clk->ops->get_parent(clk); + + if (idx >= clk->num_parents) + return ERR_PTR(-ENODEV); + } else { + idx = 0; + } + + if (IS_ERR_OR_NULL(clk->parents[idx])) + clk->parents[idx] = clk_lookup(clk->parent_names[idx]); + + return clk->parents[idx]; +} + +int clk_register(struct clk *clk) +{ + clk->parents = xzalloc(sizeof(struct clk *) * clk->num_parents); + + list_add_tail(&clk->list, &clks); + + return 0; +} + +static void dump_one(struct clk *clk, int verbose, int indent) +{ + struct clk *c; + + printf("%*s%s (rate %ld, %sabled)\n", indent * 4, "", clk->name, clk_get_rate(clk), + clk->enable_count ? "en" : "dis"); + if (verbose) { + + if (clk->num_parents > 1) { + int i; + printf("%*s`---- possible parents: ", indent * 4, ""); + for (i = 0; i < clk->num_parents; i++) + printf("%s ", clk->parent_names[i]); + printf("\n"); + } + } + + list_for_each_entry(c, &clks, list) { + struct clk *parent = clk_get_parent(c); + + if (parent == clk) { + dump_one(c, verbose, indent + 1); + } + } +} + +void clk_dump(int verbose) +{ + struct clk *c; + + list_for_each_entry(c, &clks, list) { + struct clk *parent = clk_get_parent(c); + + if (IS_ERR_OR_NULL(parent)) + dump_one(c, verbose, 0); + } +} diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c index 717fea5689..1ae822ffa6 100644 --- a/drivers/clk/clkdev.c +++ b/drivers/clk/clkdev.c @@ -62,6 +62,34 @@ static struct clk *clk_find(const char *dev_id, const char *con_id) return clk; } +static struct clk *clk_find_physbase(struct device_d *dev, const char *con_id) +{ + struct clk_lookup *p; + unsigned long start; + struct clk *clk = ERR_PTR(-ENOSYS); + + if (!dev || !dev->resource) + return ERR_PTR(-ENOSYS); + + start = dev->resource[0].start; + + list_for_each_entry(p, &clocks, node) { + if (p->physbase == ~0) + continue; + if (p->physbase != start) + continue; + if (p->con_id) { + if (!con_id || strcmp(p->con_id, con_id)) + continue; + return p->clk; + } + clk = p->clk; + } + + return clk; + +} + struct clk *clk_get_sys(const char *dev_id, const char *con_id) { struct clk *clk; @@ -77,6 +105,11 @@ EXPORT_SYMBOL(clk_get_sys); struct clk *clk_get(struct device_d *dev, const char *con_id) { const char *dev_id = dev ? dev_name(dev) : NULL; + struct clk *clk; + + clk = clk_find_physbase(dev, con_id); + if (!IS_ERR(clk)) + return clk; return clk_get_sys(dev_id, con_id); } @@ -90,6 +123,9 @@ EXPORT_SYMBOL(clk_put); void clkdev_add(struct clk_lookup *cl) { + if (cl->dev_id) + cl->physbase = ~0; + list_add_tail(&cl->node, &clocks); } EXPORT_SYMBOL(clkdev_add); @@ -97,6 +133,8 @@ EXPORT_SYMBOL(clkdev_add); void __init clkdev_add_table(struct clk_lookup *cl, size_t num) { while (num--) { + if (cl->dev_id) + cl->physbase = ~0; list_add_tail(&cl->node, &clocks); cl++; } @@ -120,6 +158,7 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, if (!cla) return NULL; + cla->cl.physbase = ~0; cla->cl.clk = clk; if (con_id) { strlcpy(cla->con_id, con_id, sizeof(cla->con_id)); @@ -166,3 +205,19 @@ void clkdev_drop(struct clk_lookup *cl) kfree(cl); } EXPORT_SYMBOL(clkdev_drop); + +int clkdev_add_physbase(struct clk *clk, unsigned long base, const char *id) +{ + struct clk_lookup *cl; + + cl = xzalloc(sizeof(*cl)); + + cl->clk = clk; + cl->con_id = id; + cl->physbase = base; + + clkdev_add(cl); + + return 0; +} +EXPORT_SYMBOL(clkdev_add_physbase); diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index eed104fb52..24bbc6b7cc 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -37,7 +37,7 @@ #include <malloc.h> #include <types.h> #include <xfuncs.h> - +#include <linux/clk.h> #include <linux/err.h> #include <io.h> @@ -101,6 +101,7 @@ static u16 i2c_clk_div[50][2] = { struct fsl_i2c_struct { void __iomem *base; + struct clk *clk; struct i2c_adapter adapter; unsigned int disable_delay; int stopped; @@ -109,6 +110,19 @@ struct fsl_i2c_struct { }; #define to_fsl_i2c_struct(a) container_of(a, struct fsl_i2c_struct, adapter) +#ifdef CONFIG_COMMON_CLK +static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl) +{ + return clk_get_rate(i2c_fsl->clk); +} + +#else +static inline unsigned long i2c_fsl_clk_get_rate(struct fsl_i2c_struct *i2c_fsl) +{ + return fsl_get_i2cclk(); +} +#endif + #ifdef CONFIG_I2C_DEBUG static void i2c_fsl_dump_reg(struct i2c_adapter *adapter) { @@ -344,7 +358,7 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl, int i; /* Divider value calculation */ - i2c_clk_rate = fsl_get_i2cclk(); + i2c_clk_rate = i2c_fsl_clk_get_rate(i2c_fsl); div = (i2c_clk_rate + rate - 1) / rate; if (div < i2c_clk_div[0][0]) i = 0; @@ -535,6 +549,11 @@ static int __init i2c_fsl_probe(struct device_d *pdev) i2c_fsl = kzalloc(sizeof(struct fsl_i2c_struct), GFP_KERNEL); +#ifdef CONFIG_COMMON_CLK + i2c_fsl->clk = clk_get(pdev, NULL); + if (IS_ERR(i2c_fsl->clk)) + return PTR_ERR(i2c_fsl->clk); +#endif /* Setup i2c_fsl driver structure */ i2c_fsl->adapter.master_xfer = i2c_fsl_xfer; i2c_fsl->adapter.nr = pdev->id; diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 599a639251..dccffc6eec 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -28,8 +28,9 @@ #include <mci.h> #include <clock.h> #include <io.h> +#include <linux/clk.h> +#include <linux/err.h> #include <asm/mmu.h> -#include <mach/clock.h> #include <mach/generic.h> #include <mach/esdhc.h> #include <gpio.h> @@ -70,6 +71,7 @@ struct fsl_esdhc_host { u32 no_snoop; unsigned long cur_clock; struct device_d *dev; + struct clk *clk; }; #define to_fsl_esdhc(mci) container_of(mci, struct fsl_esdhc_host, mci) @@ -354,7 +356,7 @@ static void set_sysctl(struct mci_host *mci, u32 clock) int div, pre_div; struct fsl_esdhc_host *host = to_fsl_esdhc(mci); struct fsl_esdhc __iomem *regs = host->regs; - int sdhc_clk = imx_get_mmcclk(); + int sdhc_clk = clk_get_rate(host->clk); u32 clk; if (clock < mci->f_min) @@ -516,11 +518,16 @@ static int fsl_esdhc_probe(struct device_d *dev) struct mci_host *mci; u32 caps; int ret; + unsigned long rate; struct esdhc_platform_data *pdata = dev->platform_data; host = xzalloc(sizeof(*host)); mci = &host->mci; + host->clk = clk_get(dev, NULL); + if (IS_ERR(host->clk)) + return PTR_ERR(host->clk); + host->dev = dev; host->regs = dev_request_mem_region(dev, 0); @@ -553,10 +560,11 @@ static int fsl_esdhc_probe(struct device_d *dev) host->mci.init = esdhc_init; host->mci.hw_dev = dev; - host->mci.f_min = imx_get_mmcclk() >> 12; + rate = clk_get_rate(host->clk); + host->mci.f_min = rate >> 12; if (host->mci.f_min < 200000) host->mci.f_min = 200000; - host->mci.f_max = imx_get_mmcclk(); + host->mci.f_max = rate; mci_register(&host->mci); diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c index 8a6547d87b..072ca93794 100644 --- a/drivers/mci/imx.c +++ b/drivers/mci/imx.c @@ -25,6 +25,8 @@ #include <clock.h> #include <init.h> #include <driver.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/clock.h> #include <io.h> @@ -103,6 +105,7 @@ struct mxcmci_regs { struct mxcmci_host { struct mci_host mci; struct mxcmci_regs *base; + struct clk *clk; int irq; int detect_irq; int dma; @@ -415,7 +418,7 @@ static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) { unsigned int divider; int prescaler = 0; - unsigned long clk_in = imx_get_mmcclk(); + unsigned long clk_in = clk_get_rate(host->clk); while (prescaler <= 0x800) { for (divider = 1; divider <= 0xF; divider++) { @@ -490,9 +493,14 @@ static int mxcmci_init(struct mci_host *mci, struct device_d *dev) static int mxcmci_probe(struct device_d *dev) { struct mxcmci_host *host; + unsigned long rate; host = xzalloc(sizeof(*host)); + host->clk = clk_get(dev, NULL); + if (IS_ERR(host->clk)) + return PTR_ERR(host->clk); + host->mci.send_cmd = mxcmci_request; host->mci.set_ios = mxcmci_set_ios; host->mci.init = mxcmci_init; @@ -503,8 +511,9 @@ static int mxcmci_probe(struct device_d *dev) host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - host->mci.f_min = imx_get_mmcclk() >> 7; - host->mci.f_max = imx_get_mmcclk() >> 1; + rate = clk_get_rate(host->clk); + host->mci.f_min = rate >> 7; + host->mci.f_max = rate >> 1; mci_register(&host->mci); diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 1aebee7056..b95c4f056e 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -24,6 +24,8 @@ #include <clock.h> #include <xfuncs.h> #include <linux/phy.h> +#include <linux/clk.h> +#include <linux/err.h> #include <asm/mmu.h> @@ -43,6 +45,19 @@ struct fec_frame { uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ }; +#ifdef CONFIG_COMMON_CLK +static inline unsigned long fec_clk_get_rate(struct fec_priv *fec) +{ + return clk_get_rate(fec->clk); +} +#else +static inline unsigned long fec_clk_get_rate(struct fec_priv *fec) +{ + return imx_get_fecclk(); +} +#endif + + /* * MII-interface related functions */ @@ -54,7 +69,7 @@ static int fec_miibus_read(struct mii_bus *bus, int phyAddr, int regAddr) uint32_t phy; /* convenient holder for the PHY */ uint64_t start; - writel(((imx_get_fecclk() >> 20) / 5) << 1, + writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1, fec->regs + FEC_MII_SPEED); /* * reading from any PHY's register is done by properly @@ -97,7 +112,7 @@ static int fec_miibus_write(struct mii_bus *bus, int phyAddr, uint32_t phy; /* convenient holder for the PHY */ uint64_t start; - writel(((imx_get_fecclk() >> 20) / 5) << 1, + writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1, fec->regs + FEC_MII_SPEED); reg = regAddr << FEC_MII_DATA_RA_SHIFT; @@ -290,7 +305,7 @@ static int fec_init(struct eth_device *dev) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel(((imx_get_fecclk() >> 20) / 5) << 1, + writel(((fec_clk_get_rate(fec) >> 20) / 5) << 1, fec->regs + FEC_MII_SPEED); } @@ -612,6 +627,7 @@ static int fec_probe(struct device_d *dev) struct eth_device *edev; struct fec_priv *fec; void *base; + int ret; #ifdef CONFIG_ARCH_IMX27 PCCR0 |= PCCR0_FEC_EN; #endif @@ -628,6 +644,14 @@ static int fec_probe(struct device_d *dev) edev->set_ethaddr = fec_set_hwaddr; edev->parent = dev; + if (IS_ENABLED(CONFIG_COMMON_CLK)) { + fec->clk = clk_get(dev, NULL); + if (IS_ERR(fec->clk)) { + ret = PTR_ERR(fec->clk); + goto err_free; + } + } + fec->regs = dev_request_mem_region(dev, 0); /* Reset chip. */ @@ -682,6 +706,10 @@ static int fec_probe(struct device_d *dev) eth_register(edev); return 0; + +err_free: + free(fec); + return ret; } static void fec_remove(struct device_d *dev) diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h index d10385a531..d147dca113 100644 --- a/drivers/net/fec_imx.h +++ b/drivers/net/fec_imx.h @@ -138,6 +138,7 @@ struct fec_priv { u32 phy_flags; struct mii_bus miibus; void (*phy_init)(struct phy_device *dev); + struct clk *clk; }; /** diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 61ceb48c91..a7119405c2 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -16,12 +16,13 @@ #include <common.h> #include <mach/imx-regs.h> -#include <mach/clock.h> #include <driver.h> #include <init.h> #include <malloc.h> #include <notifier.h> #include <io.h> +#include <linux/err.h> +#include <linux/clk.h> #define URXD0 0x0 /* Receiver Register */ #define URTX0 0x40 /* Transmitter Register */ @@ -170,16 +171,17 @@ struct imx_serial_priv { int baudrate; struct notifier_block notify; void __iomem *regs; + struct clk *clk; }; -static int imx_serial_reffreq(void __iomem *regs) +static int imx_serial_reffreq(struct imx_serial_priv *priv) { ulong rfdiv; - rfdiv = (readl(regs + UFCR) >> 7) & 7; + rfdiv = (readl(priv->regs + UFCR) >> 7) & 7; rfdiv = rfdiv < 6 ? 6 - rfdiv : 7; - return imx_get_uartclk() / rfdiv; + return clk_get_rate(priv->clk) / rfdiv; } /* @@ -209,7 +211,7 @@ static int imx_serial_init_port(struct console_device *cdev) writel(0xa81, regs + UFCR); #ifdef ONEMS - writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS); + writel(imx_serial_reffreq(priv) / 1000, regs + ONEMS); #endif /* Enable FIFOs */ @@ -291,7 +293,7 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate) /* Set the numerator value minus one of the BRM ratio */ writel((baudrate / 100) - 1, regs + UBIR); /* Set the denominator value minus one of the BRM ratio */ - writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR); + writel((imx_serial_reffreq(priv) / 1600) - 1, regs + UBMR); writel(ucr1, regs + UCR1); @@ -316,11 +318,18 @@ static int imx_serial_probe(struct device_d *dev) struct console_device *cdev; struct imx_serial_priv *priv; uint32_t val; + int ret; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; dev->priv = priv; + priv->clk = clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + ret = PTR_ERR(priv->clk); + goto err_free; + } + priv->regs = dev_request_mem_region(dev, 0); cdev->dev = dev; cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR; @@ -343,6 +352,11 @@ static int imx_serial_probe(struct device_d *dev) clock_register_client(&priv->notify); return 0; + +err_free: + free(priv); + + return ret; } static void imx_serial_remove(struct device_d *dev) diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 8551f73afa..71fac3de3b 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -21,10 +21,12 @@ #include <xfuncs.h> #include <io.h> #include <errno.h> +#include <malloc.h> #include <gpio.h> #include <mach/spi.h> #include <mach/generic.h> -#include <mach/clock.h> +#include <linux/clk.h> +#include <linux/err.h> #define CSPI_0_0_RXDATA 0x00 #define CSPI_0_0_TXDATA 0x04 @@ -128,6 +130,7 @@ struct imx_spi { struct spi_master master; int *cs_array; void __iomem *regs; + struct clk *clk; unsigned int (*xchg_single)(struct imx_spi *imx, u32 data); void (*chipselect)(struct spi_device *spi, int active); @@ -276,7 +279,7 @@ static void cspi_0_7_chipselect(struct spi_device *spi, int is_active) return; } - reg |= spi_imx_clkdiv_2(imx_get_cspiclk(), spi->max_speed_hz) << + reg |= spi_imx_clkdiv_2(clk_get_rate(imx->clk), spi->max_speed_hz) << CSPI_0_7_CTRL_DR_SHIFT; reg |= (spi->bits_per_word - 1) << CSPI_0_7_CTRL_BL_SHIFT; @@ -381,7 +384,7 @@ static void cspi_2_3_chipselect(struct spi_device *spi, int is_active) ctrl |= CSPI_2_3_CTRL_MODE(cs); /* set clock speed */ - ctrl |= cspi_2_3_clkdiv(imx_get_cspiclk(), spi->max_speed_hz); + ctrl |= cspi_2_3_clkdiv(clk_get_rate(imx->clk), spi->max_speed_hz); /* set chip select to use */ ctrl |= CSPI_2_3_CTRL_CS(cs); @@ -524,6 +527,7 @@ static int imx_spi_probe(struct device_d *dev) struct imx_spi *imx; struct spi_imx_master *pdata = dev->platform_data; enum imx_spi_devtype version; + int ret; imx = xzalloc(sizeof(*imx)); @@ -532,6 +536,7 @@ static int imx_spi_probe(struct device_d *dev) master->setup = imx_spi_setup; master->transfer = imx_spi_transfer; + if (pdata) { master->num_chipselect = pdata->num_chipselect; imx->cs_array = pdata->chipselect; @@ -540,6 +545,12 @@ static int imx_spi_probe(struct device_d *dev) imx_spi_dt_probe(imx); } + imx->clk = clk_get(dev, NULL); + if (IS_ERR(imx->clk)) { + ret = PTR_ERR(imx->clk); + goto err_free; + } + #ifdef CONFIG_DRIVER_SPI_IMX_0_0 if (cpu_is_mx27()) version = SPI_IMX_VER_0_0; @@ -562,6 +573,11 @@ static int imx_spi_probe(struct device_d *dev) spi_register_master(master); return 0; + +err_free: + free(imx); + + return ret; } static __maybe_unused struct of_device_id imx_spi_dt_ids[] = { diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 5e5244d367..3f8fd33416 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -27,10 +27,12 @@ #include <errno.h> #include <asm-generic/div64.h> #include <mach/imx-ipu-fb.h> -#include <mach/clock.h> +#include <linux/clk.h> +#include <linux/err.h> struct ipu_fb_info { void __iomem *regs; + struct clk *clk; void (*enable)(int enable); @@ -480,7 +482,7 @@ static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt) * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz */ pixel_clk = PICOS2KHZ(mode->pixclock) * 1000UL; - div = imx_get_lcdclk() * 16 / pixel_clk; + div = clk_get_rate(fbi->clk) * 16 / pixel_clk; if (div < 0x40) { /* Divider less than 4 */ dev_dbg(&info->dev, @@ -986,6 +988,10 @@ static int imxfb_probe(struct device_d *dev) fbi = xzalloc(sizeof(*fbi)); info = &fbi->info; + fbi->clk = clk_get(dev, NULL); + if (IS_ERR(fbi->clk)) + return PTR_ERR(fbi->clk); + fbi->regs = dev_request_mem_region(dev, 0); fbi->dev = dev; fbi->enable = pdata->enable; diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 29b1fc523d..9406b36e71 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -22,9 +22,10 @@ #include <malloc.h> #include <errno.h> #include <init.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/imx-regs.h> #include <asm-generic/div64.h> -#include <mach/clock.h> #define LCDC_SSA 0x00 @@ -138,6 +139,7 @@ struct imxfb_rgb { struct imxfb_info { void __iomem *regs; + struct clk *clk; u_int pcr; u_int pwmr; @@ -341,7 +343,7 @@ static int imxfb_activate_var(struct fb_info *info) writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), fbi->regs + LCDC_CPOS); - lcd_clk = imx_get_lcdclk(); + lcd_clk = clk_get_rate(fbi->clk); tmp = mode->pixclock * (unsigned long long)lcd_clk; @@ -564,6 +566,10 @@ static int imxfb_probe(struct device_d *dev) fbi = xzalloc(sizeof(*fbi)); info = &fbi->info; + fbi->clk = clk_get(dev, NULL); + if (IS_ERR(fbi->clk)) + return PTR_ERR(fbi->clk); + fbi->mode = pdata->mode; fbi->regs = dev_request_mem_region(dev, 0); fbi->pcr = pdata->mode->pcr; diff --git a/include/linux/clk.h b/include/linux/clk.h index 1478c97381..e9031dd17a 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -155,4 +155,46 @@ struct clk *clk_get_sys(const char *dev_id, const char *con_id); int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, struct device_d *dev); +#ifdef CONFIG_COMMON_CLK +struct clk_ops { + int (*enable)(struct clk *clk); + void (*disable)(struct clk *clk); + int (*is_enabled)(struct clk *clk); + unsigned long (*recalc_rate)(struct clk *clk, + unsigned long parent_rate); + long (*round_rate)(struct clk *clk, unsigned long, + unsigned long *); + int (*set_parent)(struct clk *clk, u8 index); + int (*get_parent)(struct clk *clk); + int (*set_rate)(struct clk *clk, unsigned long, + unsigned long); +}; + +struct clk { + const struct clk_ops *ops; + int enable_count; + struct list_head list; + const char *name; + const char **parent_names; + int num_parents; + + struct clk **parents; +}; + +struct clk *clk_fixed(const char *name, int rate); +struct clk *clk_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width); +struct clk *clk_fixed_factor(const char *name, + const char *parent, unsigned int mult, unsigned int div); +struct clk *clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, u8 num_parents); + +int clk_register(struct clk *clk); + +struct clk *clk_lookup(const char *name); + +void clk_dump(int verbose); + +#endif + #endif diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h index d2eca99b57..d2f0d8972e 100644 --- a/include/linux/clkdev.h +++ b/include/linux/clkdev.h @@ -19,6 +19,7 @@ struct device_d; struct clk_lookup { struct list_head node; + unsigned long physbase; const char *dev_id; const char *con_id; struct clk *clk; @@ -33,6 +34,8 @@ void clkdev_drop(struct clk_lookup *cl); void clkdev_add_table(struct clk_lookup *, size_t); int clk_add_alias(const char *, const char *, char *, struct device_d *); +int clkdev_add_physbase(struct clk *clk, unsigned long base, const char *id); + #define CLKDEV_DEV_ID(_id, _clk) \ { \ .dev_id = _id, \ diff --git a/include/linux/err.h b/include/linux/err.h index e0d8d2d33a..19fb70dc08 100644 --- a/include/linux/err.h +++ b/include/linux/err.h @@ -34,6 +34,11 @@ static inline long IS_ERR(const void *ptr) return IS_ERR_VALUE((unsigned long)ptr); } +static inline long __must_check IS_ERR_OR_NULL(const void *ptr) +{ + return !ptr || IS_ERR_VALUE((unsigned long)ptr); +} + /** * ERR_CAST - Explicitly cast an error-valued pointer to another pointer type * @ptr: The pointer to cast. |