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authorSascha Hauer <s.hauer@pengutronix.de>2017-02-02 12:08:32 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-02-06 07:41:56 +0100
commitc82e1f90d2fa1ebfbeaf0f765ee974b31d273b1c (patch)
treebdbbf08939d3af3b9e1ce4e18371495d9113e674
parent75cb02078e0353c968b9c8cb71c6d02e597dc137 (diff)
downloadbarebox-c82e1f90d2fa1ebfbeaf0f765ee974b31d273b1c.tar.gz
clk: i.MX7: setup ethernet clocks
Reparent ethernet clocks so that they can be used by the fec driver. The values are the same as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/imx/clk-imx7.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 6bf1234..d3a036c 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -844,6 +844,17 @@ static int imx7_clk_setup(void)
/* set uart module clock's parent clock source that must be great then 80MHz */
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
+ clk_set_parent(clks[IMX7D_ENET1_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
+ clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
+ clk_set_parent(clks[IMX7D_ENET2_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
+ clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
+
+ clk_set_rate(clks[IMX7D_PLL_SYS_PFD4_CLK], 392000000);
+ clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD4_CLK]);
+ clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 197000000);
+ clk_set_rate(clks[IMX7D_ENET1_TIME_ROOT_CLK], 25000000);
+ clk_set_rate(clks[IMX7D_ENET2_TIME_ROOT_CLK], 25000000);
+
return 0;
}
postcore_initcall(imx7_clk_setup);