ARM: socfpga: add support for reflex achilles board

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

9 files changed, 341 insertions, 0 deletions

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 250ccb8889..bcd94a0569 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK)			+= sama5d4ek/
 obj-$(CONFIG_MACH_SCB9328)			+= scb9328/
 obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK)		+= altera-socdk/
 obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES)		+= ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES)	+= reflex-achilles/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC)	+= terasic-de0-nano-soc/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT)	+= terasic-sockit/
 obj-$(CONFIG_MACH_SOLIDRUN_CUBOX)		+= solidrun-cubox/
diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile
new file mode 100644
index 0000000000..6b42141153
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
new file mode 100644
index 0000000000..12994177cc
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -0,0 +1,48 @@
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <debug_ll.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include "pll-config-arria10.c"
+#include "pinmux-config-arria10.c"
+#include <mach/generic.h>
+
+extern char __dtb_socfpga_arria10_achilles_start[];
+
+static noinline void achilles_entry(void)
+{
+	void *fdt;
+
+	arm_early_mmu_cache_invalidate();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+	puts_ll("lowlevel init done\n");
+
+	arria10_ddr_calibration_sequence();
+
+	puts_ll("SDRAM setup done\n");
+
+	fdt = __dtb_socfpga_arria10_achilles_start - get_runtime_offset();
+
+	barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0xffe00000 + SZ_256K - SZ_32K - SZ_4K - 16);
+
+	achilles_entry();
+}
diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
new file mode 100644
index 0000000000..246838a228
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
@@ -0,0 +1,102 @@
+#include <mach/arria10-pinmux.h>
+
+static uint32_t pinmux[] = {
+[arria10_pinmux_shared_io_q4_12] = 8,
+[arria10_pinmux_shared_io_q4_11] = 8,
+[arria10_pinmux_shared_io_q4_10] = 8,
+[arria10_pinmux_shared_io_q4_9] = 8,
+[arria10_pinmux_shared_io_q4_8] = 8,
+[arria10_pinmux_shared_io_q4_6] = 8,
+[arria10_pinmux_shared_io_q4_7] = 8,
+[arria10_pinmux_shared_io_q4_5] = 8,
+[arria10_pinmux_shared_io_q4_4] = 8,
+[arria10_pinmux_shared_io_q4_3] = 8,
+[arria10_pinmux_shared_io_q4_2] = 8,
+[arria10_pinmux_shared_io_q4_1] = 8,
+[arria10_pinmux_shared_io_q3_12] = 8,
+[arria10_pinmux_shared_io_q3_11] = 8,
+[arria10_pinmux_shared_io_q3_10] = 8,
+[arria10_pinmux_shared_io_q3_8] = 8,
+[arria10_pinmux_shared_io_q3_9] = 8,
+[arria10_pinmux_shared_io_q3_7] = 8,
+[arria10_pinmux_shared_io_q3_6] = 8,
+[arria10_pinmux_shared_io_q3_5] = 8,
+[arria10_pinmux_shared_io_q3_4] = 8,
+[arria10_pinmux_shared_io_q3_3] = 8,
+[arria10_pinmux_shared_io_q3_2] = 8,
+[arria10_pinmux_shared_io_q3_1] = 8,
+[arria10_pinmux_shared_io_q2_12] = 8,
+[arria10_pinmux_shared_io_q2_10] = 8,
+[arria10_pinmux_shared_io_q2_11] = 8,
+[arria10_pinmux_shared_io_q2_9] = 8,
+[arria10_pinmux_shared_io_q2_8] = 8,
+[arria10_pinmux_shared_io_q2_7] = 8,
+[arria10_pinmux_shared_io_q2_6] = 8,
+[arria10_pinmux_shared_io_q2_5] = 8,
+[arria10_pinmux_shared_io_q2_4] = 8,
+[arria10_pinmux_shared_io_q2_3] = 8,
+[arria10_pinmux_shared_io_q2_2] = 8,
+[arria10_pinmux_shared_io_q2_1] = 8,
+[arria10_pinmux_shared_io_q1_12] = 10,
+[arria10_pinmux_shared_io_q1_11] = 10,
+[arria10_pinmux_shared_io_q1_10] = 1,
+[arria10_pinmux_shared_io_q1_9] = 1,
+[arria10_pinmux_shared_io_q1_8] = 1,
+[arria10_pinmux_shared_io_q1_7] = 1,
+[arria10_pinmux_shared_io_q1_6] = 0,
+[arria10_pinmux_shared_io_q1_5] = 0,
+[arria10_pinmux_shared_io_q1_4] = 13,
+[arria10_pinmux_shared_io_q1_3] = 13,
+[arria10_pinmux_shared_io_q1_2] = 13,
+[arria10_pinmux_shared_io_q1_1] = 13,
+[arria10_pinmux_dedicated_io_4] = 8,
+[arria10_pinmux_dedicated_io_5] = 8,
+[arria10_pinmux_dedicated_io_6] = 8,
+[arria10_pinmux_dedicated_io_7] = 8,
+[arria10_pinmux_dedicated_io_8] = 8,
+[arria10_pinmux_dedicated_io_9] = 8,
+[arria10_pinmux_dedicated_io_10] = 10,
+[arria10_pinmux_dedicated_io_11] = 10,
+[arria10_pinmux_dedicated_io_12] = 8,
+[arria10_pinmux_dedicated_io_13] = 8,
+[arria10_pinmux_dedicated_io_14] = 8,
+[arria10_pinmux_dedicated_io_15] = 8,
+[arria10_pinmux_dedicated_io_16] = 15,
+[arria10_pinmux_dedicated_io_17] = 15,
+[arria10_pincfg_dedicated_io_bank] = 0x101,
+[arria10_pincfg_dedicated_io_1] = 0xb080a,
+[arria10_pincfg_dedicated_io_2] = 0xb080a,
+[arria10_pincfg_dedicated_io_3] = 0xb080a,
+[arria10_pincfg_dedicated_io_4] = 0xa282a,
+[arria10_pincfg_dedicated_io_5] = 0xa282a,
+[arria10_pincfg_dedicated_io_6] = 0xa282a,
+[arria10_pincfg_dedicated_io_7] = 0xa282a,
+[arria10_pincfg_dedicated_io_8] = 0xa282a,
+[arria10_pincfg_dedicated_io_9] = 0xa282a,
+[arria10_pincfg_dedicated_io_10] = 0x90000,
+[arria10_pincfg_dedicated_io_11] = 0x90000,
+[arria10_pincfg_dedicated_io_12] = 0xa282a,
+[arria10_pincfg_dedicated_io_13] = 0xa282a,
+[arria10_pincfg_dedicated_io_14] = 0xa282a,
+[arria10_pincfg_dedicated_io_15] = 0xa282a,
+[arria10_pincfg_dedicated_io_16] = 0xa282a,
+[arria10_pincfg_dedicated_io_17] = 0xa282a,
+[arria10_pinmux_rgmii0_usefpga] = 0,
+[arria10_pinmux_rgmii1_usefpga] = 0,
+[arria10_pinmux_rgmii2_usefpga] = 0,
+[arria10_pinmux_nand_usefpga] = 0,
+[arria10_pinmux_qspi_usefpga] = 0,
+[arria10_pinmux_sdmmc_usefpga] = 0,
+[arria10_pinmux_spim0_usefpga] = 1,
+[arria10_pinmux_spim1_usefpga] = 0,
+[arria10_pinmux_spis0_usefpga] = 0,
+[arria10_pinmux_spis1_usefpga] = 0,
+[arria10_pinmux_uart0_usefpga] = 0,
+[arria10_pinmux_uart1_usefpga] = 0,
+[arria10_pinmux_i2c0_usefpga] = 0,
+[arria10_pinmux_i2c1_usefpga] = 0,
+[arria10_pinmux_i2cemac0_usefpga] = 0,
+[arria10_pinmux_i2cemac1_usefpga] = 0,
+[arria10_pinmux_i2cemac2_usefpga] = 0,
+};
+
diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
new file mode 100644
index 0000000000..94d596606e
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
@@ -0,0 +1,54 @@
+#include <mach/arria10-clock-manager.h>
+
+static struct arria10_mainpll_cfg mainpll_cfg = {
+	.cntr15clk_cnt = 900,
+	.cntr2clk_cnt = 900,
+	.cntr3clk_cnt = 900,
+	.cntr4clk_cnt = 900,
+	.cntr5clk_cnt = 900,
+	.cntr6clk_cnt = 7,
+	.cntr7clk_cnt = 900,
+	.cntr7clk_src = 0,
+	.cntr8clk_cnt = 900,
+	.cntr9clk_cnt = 900,
+	.cntr9clk_src = 0,
+	.mpuclk_cnt = 0,
+	.mpuclk_src = 0,
+	.nocclk_cnt = 0,
+	.nocclk_src = 0,
+	.nocdiv_csatclk = 2,
+	.nocdiv_cspdbgclk = 0,
+	.nocdiv_cstraceclk = 0,
+	.nocdiv_l4mainclk = 2,
+	.nocdiv_l4mpclk = 2,
+	.nocdiv_l4spclk = 2,
+	.vco0_psrc = 0,
+	.vco1_denom = 1,
+	.vco1_numer = 127,
+	.mpuclk = 0x3840001,
+	.nocclk = 0x3840003,
+};
+
+static struct arria10_perpll_cfg perpll_cfg = {
+	.cntr2clk_cnt = 5,
+	.cntr2clk_src = 1,
+	.cntr3clk_cnt = 900,
+	.cntr3clk_src = 1,
+	.cntr4clk_cnt = 14,
+	.cntr4clk_src = 1,
+	.cntr5clk_cnt = 374,
+	.cntr5clk_src = 1,
+	.cntr6clk_cnt = 900,
+	.cntr6clk_src = 0,
+	.cntr7clk_cnt = 900,
+	.cntr8clk_cnt = 900,
+	.cntr8clk_src = 0,
+	.cntr9clk_cnt = 900,
+	.emacctl_emac0sel = 0,
+	.emacctl_emac1sel = 0,
+	.emacctl_emac2sel = 0,
+	.gpiodiv_gpiodbclk = 32000,
+	.vco0_psrc = 0,
+	.vco1_denom = 1,
+	.vco1_numer = 119,
+};
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e8ad43bfd8..96e54d815f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -65,6 +65,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+pbl-dtb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
new file mode 100644
index 0000000000..dd991318e2
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+#include <arm/socfpga_arria10.dtsi>
+
+/ {
+	model = "Reflex SOCFPGA Arria 10 Achilles";
+	compatible = "reflex,achilles", "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		linux,stdout-path = &uart0;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0xc0000000>;
+	};
+
+	soc {
+		clkmgr@ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+
+				cb_intosc_hs_div2_clk {
+					clock-frequency = <0>;
+				};
+				cb_intosc_ls_clk {
+					clock-frequency = <60000000>;
+				};
+				f2s_free_clk {
+					clock-frequency = <200000000>;
+				};
+			};
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	phy-addr = <0x00fffff0>; /* probe for phy addr */
+
+	/*
+	 * These skews assume the user's FPGA design is adding 600ps of delay
+	 * for TX_CLK on Arria 10.
+	 *
+	 * All skews are offset since hardware skew values for the ksz9031
+	 * range from a negative skew to a positive skew.
+	 * See the micrel-ksz90x1.txt Documentation file for details.
+	 */
+	txd0-skew-ps = <0>; /* -420ps */
+	txd1-skew-ps = <0>; /* -420ps */
+	txd2-skew-ps = <0>; /* -420ps */
+	txd3-skew-ps = <0>; /* -420ps */
+	rxd0-skew-ps = <420>; /* 0ps */
+	rxd1-skew-ps = <420>; /* 0ps */
+	rxd2-skew-ps = <420>; /* 0ps */
+	rxd3-skew-ps = <420>; /* 0ps */
+	txen-skew-ps = <0>; /* -420ps */
+	txc-skew-ps = <1860>; /* 960ps */
+	rxdv-skew-ps = <420>; /* 0ps */
+	rxc-skew-ps = <1680>; /* 780ps */
+	max-frame-size = <3800>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	tempsensor: ti,tmp102@0x48 {
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+
+	rtc: nxp,pcf8563@0x51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+
+	eeprom: at24@0x54 {
+		compatible = "at24";
+		reg = <0x54>;
+		bytelen = <256>;
+		pagesize = <16>;
+	};
+};
+
+&mmc {
+	supports-highspeed;
+	broken-cd;
+	bus-width = <1>;
+	status = "okay";
+};
+
+&uart0 {
+	reg-io-width = <4>;
+	status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0a33e88644..caff566bdc 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,6 +33,11 @@ config MACH_SOCFPGA_EBV_SOCRATES
 	select ARCH_SOCFPGA_CYCLONE5
 	bool "EBV Socrates"
 
+config MACH_SOCFPGA_REFLEX_ACHILLES
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+	select ARCH_SOCFPGA_ARRIA10
+	bool "Reflex Achilles"
+
 config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
 	select HAVE_DEFAULT_ENVIRONMENT_NEW
 	select ARCH_SOCFPGA_CYCLONE5
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index a764b1a5fe..60b98d1ef2 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -30,6 +30,10 @@ pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc
 FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
 socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
 
+pblx-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles
+FILE_barebox-socfpga-achilles.img = start_socfpga_achilles.pblx.socfpgaimg
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles.img
+
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
 FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
 socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img