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authorAlexander Kurz <akurz@blala.de>2017-06-08 20:41:34 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-06-13 09:27:14 +0200
commit46078f8d9917164a148cd2ad156e7e061505f8d4 (patch)
tree6e814db951553dc88e90fef2a05dd05521dddf29
parent8b1b75441d415de7c73b6f68dd2e29b7e0ead9fb (diff)
downloadbarebox-46078f8d9917164a148cd2ad156e7e061505f8d4.tar.gz
barebox-46078f8d9917164a148cd2ad156e7e061505f8d4.tar.xz
ARM: i.MX6 Wandboard: dont do MMDC Write Leveling Calibration
The hardware requirements to perform a write leveling calibration are not fulfilled by the Wandboard modules. IMX6DQRM ยง44.11.6 "Write leveling Calibration" Note2 states that the first bit of each data byte group (D0, D8, ..., D56) from memory must be connected to the same data bus bit on the controller, which is not given on the Wandboard modules, resulting in unpredictable calib results and breaking the WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD. Remove this calibration and use the MPWLDECTRL defaults. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/boards/technexion-wandboard/lowlevel.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c
index d3eb9a03e9..ff5ae6d510 100644
--- a/arch/arm/boards/technexion-wandboard/lowlevel.c
+++ b/arch/arm/boards/technexion-wandboard/lowlevel.c
@@ -276,7 +276,6 @@ static unsigned long wandboard_dram_init(void)
__udelay(100);
- mmdc_do_write_level_calibration();
mmdc_do_dqs_calibration();
#ifdef DEBUG
mmdc_print_calibration_results();