diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-27 12:59:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-27 13:03:24 +0200 |
| commit | a27f3df9fea104a97ef4b96dd01f6fd4938487d1 (patch) | |
| tree | d8ae7d27aa4b25943b974285c8e653f313a6ec8e | |
| parent | ed4b062f0f2cfadff8733fe66ed9f4e5cd599fee (diff) | |
| download | barebox-a27f3df9fea104a97ef4b96dd01f6fd4938487d1.tar.gz barebox-a27f3df9fea104a97ef4b96dd01f6fd4938487d1.tar.xz | |
ARM: omap: phytec-phycore-omap4460: Fix compiler warning
Use IS_ENABLED() rather than #ifdef to get rid of unused variable
warning.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/phytec-phycore-omap4460/lowlevel.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index 71ab793354..02297adb95 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -96,19 +96,19 @@ static void noinline pcm049_init_lowlevel(void) set_muxconf_regs(); -#ifdef CONFIG_1024MB_DDR2RAM - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); - writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE + - EMIF_LPDDR2_MODE_REG_CONFIG); - density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) & - LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT; - if (density == LPDDR2_2G) - omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); - else if (density == LPDDR2_4G) - omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core); -#else - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); -#endif + if (IS_ENABLED(CONFIG_1024MB_DDR2RAM)) { + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); + writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE + + EMIF_LPDDR2_MODE_REG_CONFIG); + density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) & + LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT; + if (density == LPDDR2_2G) + omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); + else if (density == LPDDR2_4G) + omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core); + } else { + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); + } /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ if (rev < OMAP4460_ES1_0) |