diff options
authorPhilipp Zabel <>2017-07-11 11:30:50 +0200
committerLucas Stach <>2017-07-12 16:51:45 +0200
commite667f820eb373f221c9c220341178fe5e869d15a (patch)
parent06c1f19cb3bc38d3d725bb0b2acabfd55e6e5882 (diff)
i.MX: clk-pllv3: Initially disable PLL_BYPASS bit
Commit cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") overreached a bit by removing the code that disables the PLL_BYPASS bit for all architectures instead of making an exception for Vybrid and i.MX6SL. This causes the USB controller on i.MX6Q to run at bypass frequency and fail: barebox@Boundary Devices i.MX6 Quad Nitrogen6x Board:/ usb usb: USB: scanning bus for devices... usb: Bus 001 Device 001: ID 0000:0000 EHCI Host Controller imx-usb 2184200.usb: port(0) reset error This patch adds code to unconditionally disable the PLL_BYPASS bit initially, when the PLL clocks are registered. Cc: Andrey Smirnov <> Cc: Sascha Hauer <> Fixes: cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") Signed-off-by: Philipp Zabel <> Signed-off-by: Lucas Stach <>
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 0e55a63..44642e8 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -370,6 +370,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
struct clk_pllv3 *pll;
const struct clk_ops *ops;
int ret;
+ u32 val;
pll = xzalloc(sizeof(*pll));
@@ -414,6 +415,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
pll->clk.parent_names = &pll->parent;
pll->clk.num_parents = 1;
+ val = readl(pll->base);
+ val &= ~BM_PLL_BYPASS;
+ writel(val, pll->base);
ret = clk_register(&pll->clk);
if (ret) {