Merge branch 'for-next/socfpga'

7 files changed, 76 insertions, 29 deletions

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index b3a7f69ffe..7789c9d3b5 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,27 +1,8 @@
 / {
-	chosen {
-		environment@0 {
-			compatible = "barebox,environment";
-			device-path = &mmc, "partname:1";
-			file-path = "barebox.env";
-		};
-	};
-
 	aliases {
 		mmc0 = &mmc;
 	};
 };
-&osc2 {
-	clock-frequency = <0>;
-};
-
-&f2s_periph_ref_clk {
-	clock-frequency = <0>;
-};
-
-&f2s_sdram_ref_clk {
-	clock-frequency = <0>;
-};
 
 &watchdog0 {
 	resets = <&rst L4WD0_RESET>;
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index 087fc71e60..8854ade434 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -24,6 +24,12 @@
 
 	chosen {
 		stdout-path = &uart0;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
 	};
 
 	leds: gpio-leds {
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index f93ac105c4..dfb6273cae 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -21,6 +21,14 @@
 / {
 	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
 	compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
+	};
 };
 
 &qspi {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 7cb9b96005..8830afeb9a 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -24,5 +24,11 @@
 
 	chosen {
 		stdout-path = &uart0;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
 	};
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index ea7e6cc102..93253af7ec 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -21,6 +21,12 @@
 / {
 	chosen {
 		stdout-path = &uart0;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
 	};
 
 	aliases {
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c
index 0b022afd30..33f89148f0 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -32,6 +32,7 @@
 #include <xfuncs.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/math64.h>
 
 #include <io.h>
 #include <i2c/i2c.h>
@@ -75,6 +76,7 @@
 #define DW_IC_TX_TL			0x3c
 #define DW_IC_CLR_INTR			0x40
 #define DW_IC_CLR_TX_ABRT		0x54
+#define DW_IC_SDA_HOLD			0x7c
 
 #define DW_IC_ENABLE			0x6c
 #define DW_IC_ENABLE_ENABLE		(1 << 0)
@@ -90,6 +92,8 @@
 #define DW_IC_ENABLE_STATUS		0x9c
 #define DW_IC_ENABLE_STATUS_IC_EN	(1 << 0)
 
+#define DW_IC_COMP_VERSION		0xf8
+#define DW_IC_SDA_HOLD_MIN_VERS		0x3131312A
 #define DW_IC_COMP_TYPE			0xfc
 #define DW_IC_COMP_TYPE_VALUE		0x44570140
 
@@ -99,10 +103,15 @@
 #define DW_TIMEOUT_TX			(2 * MSECOND)
 #define DW_TIMEOUT_RX			(2 * MSECOND)
 
+#define DW_IC_SDA_HOLD_RX_SHIFT		16
+#define DW_IC_SDA_HOLD_RX_MASK		GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
+
+
 struct dw_i2c_dev {
 	void __iomem *base;
 	struct clk *clk;
 	struct i2c_adapter adapter;
+	u32 sda_hold_time;
 };
 
 static inline struct dw_i2c_dev *to_dw_i2c_dev(struct i2c_adapter *a)
@@ -202,6 +211,7 @@ i2c_dw_scl_lcnt(uint32_t ic_clk, uint32_t tLOW, uint32_t tf, int offset)
 static void i2c_dw_setup_timings(struct dw_i2c_dev *dw)
 {
 	uint32_t hcnt, lcnt;
+	u32 reg;
 
 	const uint32_t sda_falling_time = 300; /* ns */
 	const uint32_t scl_falling_time = 300; /* ns */
@@ -234,6 +244,36 @@ static void i2c_dw_setup_timings(struct dw_i2c_dev *dw)
 
 	writel(hcnt, dw->base + DW_IC_FS_SCL_HCNT);
 	writel(lcnt, dw->base + DW_IC_FS_SCL_LCNT);
+
+	/* Configure SDA Hold Time if required */
+	reg = readl(dw->base + DW_IC_COMP_VERSION);
+	if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
+		u32 ht;
+		int ret;
+
+		ret = of_property_read_u32(dw->adapter.dev.device_node,
+					   "i2c-sda-hold-time-ns", &ht);
+		if (ret) {
+			/* Keep previous hold time setting if no one set it */
+			dw->sda_hold_time = readl(dw->base + DW_IC_SDA_HOLD);
+		} else if (ht) {
+			dw->sda_hold_time = div_u64((u64)input_clock_khz * ht + 500000,
+						    1000000);
+		}
+
+		/*
+		 * Workaround for avoiding TX arbitration lost in case I2C
+		 * slave pulls SDA down "too quickly" after falling egde of
+		 * SCL by enabling non-zero SDA RX hold. Specification says it
+		 * extends incoming SDA low to high transition while SCL is
+		 * high but it apprears to help also above issue.
+		 */
+		if (!(dw->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
+			dw->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
+
+		dev_dbg(&dw->adapter.dev, "adjust SDA hold time.\n");
+		writel(dw->sda_hold_time, dw->base + DW_IC_SDA_HOLD);
+	}
 }
 
 static int i2c_dw_wait_for_bits(struct dw_i2c_dev *dw, uint32_t offset,
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 9214197e62..dd081ee84f 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -22,12 +22,12 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
-#define NR_BANKS		4
+#define BANK_INCREMENT		4
+#define NR_BANKS		8
 
 struct socfpga_reset_data {
 	spinlock_t			lock;
 	void __iomem			*membase;
-	u32				modrst_offset;
 	struct reset_controller_dev	rcdev;
 };
 
@@ -44,9 +44,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
-	writel(reg | BIT(offset), data->membase + data->modrst_offset +
-				 (bank * NR_BANKS));
+	reg = readl(data->membase + (bank * BANK_INCREMENT));
+	writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
 	spin_unlock_irqrestore(&data->lock, flags);
 
 	return 0;
@@ -66,9 +65,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
-	writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
-				  (bank * NR_BANKS));
+	reg = readl(data->membase + (bank * BANK_INCREMENT));
+	writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
@@ -85,6 +83,7 @@ static int socfpga_reset_probe(struct device_d *dev)
 	struct socfpga_reset_data *data;
 	struct resource *res;
 	struct device_node *np = dev->device_node;
+	u32 modrst_offset;
 
 	data = xzalloc(sizeof(*data));
 
@@ -93,10 +92,11 @@ static int socfpga_reset_probe(struct device_d *dev)
 	if (IS_ERR(data->membase))
 		return PTR_ERR(data->membase);
 
-	if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
+	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
 		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
-		data->modrst_offset = 0x10;
+		modrst_offset = 0x10;
 	}
+	data->membase += modrst_offset;
 
 	spin_lock_init(&data->lock);