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| author | Juergen Borleis <jbe@pengutronix.de> | 2018-02-21 16:39:10 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-02-22 09:07:42 +0100 |
| commit | 645e06e3584279826206c816c23ab739e82d64ac (patch) | |
| tree | 6fa6432cd0fc0368f74eeede5e73cdc297658ed2 | |
| parent | eed8a41c5b9198572e4dd66dfd6379ec8650e872 (diff) | |
| download | barebox-645e06e3584279826206c816c23ab739e82d64ac.tar.gz barebox-645e06e3584279826206c816c23ab739e82d64ac.tar.xz | |
ARM/i.MX53: fix SDRAM setup routines
Fix setup of the SDRAM's MR0 register: 'val' gets overwritten by the chip
select decision and nothing is written to the MR0 register.
This fix is required since some i.MX53 based platforms still use this
software setup routine to configure their SDRAMs.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/esdctl-v4.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/esdctl-v4.c b/arch/arm/mach-imx/esdctl-v4.c index 0652b492ec..6de4a8d6e7 100644 --- a/arch/arm/mach-imx/esdctl-v4.c +++ b/arch/arm/mach-imx/esdctl-v4.c @@ -191,9 +191,9 @@ void imx_esdctlv4_start_ddr3_sdram(int cs) ESDCTL_V4_DDR3_REG_MR0 | val_cs1; if (cs) - val = ESDCTL_V4_ESDSCR_DLL_RST1; + val |= ESDCTL_V4_ESDSCR_DLL_RST1; else - val = ESDCTL_V4_ESDSCR_DLL_RST0; + val |= ESDCTL_V4_ESDSCR_DLL_RST0; writel(val, base + ESDCTL_V4_ESDSCR); |