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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-08 15:36:38 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-23 07:43:28 +0100 |
commit | 2ebb5ba8d0fde2e07cfd6356a80f1989b4136632 (patch) | |
tree | fc48927474b2cd43762d3c6ce4c8a8bc74df6fc5 | |
parent | bc0ee90816dfc38355d4839ef50938a0daf95578 (diff) | |
download | barebox-2ebb5ba8d0fde2e07cfd6356a80f1989b4136632.tar.gz barebox-2ebb5ba8d0fde2e07cfd6356a80f1989b4136632.tar.xz |
ARM: aarch64: mmu: Fix disabling the MMU
Do it as U-Boot: Disable MMU first, then flush caches and finally
invalidate tlbs. I wish I could reference some document instead of
U-Boot code, but I haven't found anything.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/cpu/mmu_64.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 165ff5bac6..6606405b21 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -329,12 +329,9 @@ void mmu_disable(void) cr = get_cr(); cr &= ~(CR_M | CR_C); - tlb_invalidate(); - - dsb(); - isb(); - set_cr(cr); + v8_flush_dcache_all(); + tlb_invalidate(); dsb(); isb(); |