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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-15 12:40:47 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-04-04 07:44:27 +0200 |
commit | 686cf3c05672821e949333feade826972af2d307 (patch) | |
tree | 5ff3b02751ac0f39ea5673dc446744244b8ba89e | |
parent | 4b57aae26c0ada3139ccb1011bdcbd88dc7e1a91 (diff) | |
download | barebox-686cf3c05672821e949333feade826972af2d307.tar.gz barebox-686cf3c05672821e949333feade826972af2d307.tar.xz |
ARM: create separate mmu_64.h file
cpu/mmu.h has nothing in common for the 32bit and 64bit variant. Make it
two separate files.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/cpu/mmu.h | 47 | ||||
-rw-r--r-- | arch/arm/cpu/mmu_64.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/mmu_64.h | 37 |
3 files changed, 38 insertions, 48 deletions
diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h index 5803cb6a83..79ebc80d7d 100644 --- a/arch/arm/cpu/mmu.h +++ b/arch/arm/cpu/mmu.h @@ -1,53 +1,6 @@ #ifndef __ARM_MMU_H #define __ARM_MMU_H -#ifdef CONFIG_CPU_64v8 - -#ifndef __ASSEMBLY__ - -static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr) -{ - asm volatile("dsb sy"); - if (el == 1) { - asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); - asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); - } else if (el == 2) { - asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); - asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); - } else if (el == 3) { - asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); - asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); - } else { - hang(); - } - asm volatile("isb"); -} - -static inline uint64_t get_ttbr(int el) -{ - uint64_t val; - if (el == 1) { - asm volatile("mrs %0, ttbr0_el1" : "=r" (val)); - } else if (el == 2) { - asm volatile("mrs %0, ttbr0_el2" : "=r" (val)); - } else if (el == 3) { - asm volatile("mrs %0, ttbr0_el3" : "=r" (val)); - } else { - hang(); - } - - return val; -} - -void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb); - -#endif - -#endif /* CONFIG_CPU_64v8 */ - #ifdef CONFIG_MMU void __mmu_cache_on(void); void __mmu_cache_off(void); diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 094bc0ac62..7f29ae7623 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -32,7 +32,7 @@ #include <memory.h> #include <asm/system_info.h> -#include "mmu.h" +#include "mmu_64.h" #define CACHED_MEM (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_OUTER_SHARE | \ diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h new file mode 100644 index 0000000000..cc01db0db9 --- /dev/null +++ b/arch/arm/cpu/mmu_64.h @@ -0,0 +1,37 @@ + +static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr) +{ + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); + } else { + hang(); + } + asm volatile("isb"); +} + +static inline uint64_t get_ttbr(int el) +{ + uint64_t val; + if (el == 1) { + asm volatile("mrs %0, ttbr0_el1" : "=r" (val)); + } else if (el == 2) { + asm volatile("mrs %0, ttbr0_el2" : "=r" (val)); + } else if (el == 3) { + asm volatile("mrs %0, ttbr0_el3" : "=r" (val)); + } else { + hang(); + } + + return val; +} |