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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-04-06 20:55:10 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-04-06 20:55:10 +0200 |
| commit | aa45c51b965d907ab79f777500e616338fe7de31 (patch) | |
| tree | ecc4dd3ad304fa7b9d7de7a6ee7378b341b2edd5 | |
| parent | eec2e9b2433983c775a692295a3c06799a9811d4 (diff) | |
| parent | 6eb2ba6f1b206bb7d688036a28c98eb4a89be781 (diff) | |
| download | barebox-aa45c51b965d907ab79f777500e616338fe7de31.tar.gz barebox-aa45c51b965d907ab79f777500e616338fe7de31.tar.xz | |
Merge branch 'for-next/imx'
43 files changed, 1572 insertions, 353 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst index 704aa027b6..9b1eb82d41 100644 --- a/Documentation/boards/imx.rst +++ b/Documentation/boards/imx.rst @@ -48,6 +48,63 @@ The images can also always be started second stage:: bootm /mnt/tftp/barebox-freescale-imx51-babbage.img +Information about the ``imx-image`` tool +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The imx-image tool can be used to generate imximages from raw binaries. +It requires an configuration file describing how to setup the SDRAM on +a particular board. This mainly consists of a poke table. The recognized +options in this file are: + +Header: + ++----------------+--------------------------------------------------------------+ +| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6 | ++----------------+--------------------------------------------------------------+ +| loadaddr <adr> | The address the binary is uploaded to | ++----------------+--------------------------------------------------------------+ +| dcdofs <ofs> | The offset of the image header in the image. This should be: | +| | * ``0x400``: MMC/SD, NAND, serial ROM, PATA, SATA | +| | * ``0x1000``: NOR Flash | +| | * ``0x100``: OneNAND | ++----------------+--------------------------------------------------------------+ + +Memory manipulation: + ++------------------------------------+-----------------------------------------+ +| wm 8 <addr> <value> | write <value> into byte <addr> | ++------------------------------------+-----------------------------------------+ +| wm 16 <addr> <value> | write <value> into short <addr> | ++------------------------------------+-----------------------------------------+ +| wm 32 <addr> <value> | write <value> into word <addr> | ++------------------------------------+-----------------------------------------+ +| set_bits <width> <addr> <value> | set set bits in <value> in <addr> | ++------------------------------------+-----------------------------------------+ +| clear_bits <width> <addr> <value> | clear set bits in <value> in <addr> | ++------------------------------------+-----------------------------------------+ +| nop | do nothing (just waste time) | ++------------------------------------+-----------------------------------------+ + +<width> can be of 8, 16 or 32. + +Checking conditions: + ++------------------------------------+-----------------------------------------+ +| check <width> <cond> <addr> <mask> | Poll until condition becomes true. | +| | with <cond> being one of: | +| | * ``until_all_bits_clear`` | +| | * ``until_all_bits_set`` | +| | * ``until_any_bit_clear`` | +| | * ``until_any_bit_set`` | ++------------------------------------+-----------------------------------------+ + +Some notes about the mentioned *conditions*. + + - ``until_all_bits_clear`` waits until ``(*addr & mask) == 0`` is true + - ``until_all_bits_set`` waits until ``(*addr & mask) == mask`` is true + - ``until_any_bit_clear`` waits until ``(*addr & mask) != mask`` is true + - ``until_any_bit_set`` waits until ``(*addr & mask) != 0`` is true. + Internal Boot Mode Through Internal RAM(IRAM) --------------------------------------------- diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac97de1e83..5db67b9db8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -257,8 +257,6 @@ imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX25) += $(boarddir)/eukrea_cpuimx25/flash-heade imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX35) += $(boarddir)/eukrea_cpuimx35/flash-header.imxcfg imxcfg-$(CONFIG_MACH_PCM043) += $(boarddir)/phytec-phycore-imx35/flash-header.imxcfg imxcfg-$(CONFIG_MACH_KINDLE3) += $(boarddir)/kindle3/flash-header.imxcfg -imxcfg-$(CONFIG_TX53_REV_1011) += $(boarddir)/karo-tx53/flash-header-tx53-rev1011.imxcfg -imxcfg-$(CONFIG_TX53_REV_XX30) += $(boarddir)/karo-tx53/flash-header-tx53-revxx30.imxcfg ifneq ($(imxcfg-y),) CFG_barebox.imximg := $(imxcfg-y) KBUILD_IMAGE := barebox.imximg diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index ca187ccb89..30f4c299f1 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ obj-$(CONFIG_MACH_KINDLE3) += kindle3/ +obj-$(CONFIG_MACH_KONTRON_SAMX6I) += kontron-samx6i/ obj-$(CONFIG_MACH_LENOVO_IX4_300D) += lenovo-ix4-300d/ obj-$(CONFIG_MACH_LUBBOCK) += lubbock/ obj-$(CONFIG_MACH_MAINSTONE) += mainstone/ diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index d54b3ea851..7aa5dd8d45 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -72,7 +72,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7306 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 -check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 +check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 @@ -80,4 +80,4 @@ wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 -check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 +check 32 until_any_bit_set MX7_DDRC_STAT 0x1 diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg index fd4861153f..83ed2dc065 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -68,7 +68,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 -check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 +check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 @@ -79,4 +79,4 @@ wm 32 0x30384130 0x00000002 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f -check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 +check 32 until_any_bit_set MX7_DDRC_STAT 0x1 diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg index 01ffc6998a..8dd62be210 100644 --- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg +++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg @@ -65,7 +65,7 @@ CHECKPOINT(2) /* * Wait for PLLs to lock */ -check 32 while_any_bit_clear 0x40050030 0x80000000 +check 32 until_any_bit_set 0x40050030 0x80000000 CHECKPOINT(3) @@ -240,7 +240,7 @@ wm 32 0x400ae000 0x00000601 CHECKPOINT(7) -check 32 while_any_bit_clear 0x400ae140 0x100 +check 32 until_any_bit_set 0x400ae140 0x100 CHECKPOINT(8) @@ -268,11 +268,11 @@ CHECKPOINT(8) * against that pattern */ wm 32 0x80000000 0xa5a5a5a5 -check 32 while_any_bit_clear 0x80000000 0xa5a5a5a5 +check 32 until_any_bit_set 0x80000000 0xa5a5a5a5 wm 32 0x400ae000 0x00000600 wm 32 0x400ae000 0x00000601 -check 32 while_any_bit_clear 0x400ae140 0x100 +check 32 until_any_bit_set 0x400ae140 0x100 -CHECKPOINT(9)
\ No newline at end of file +CHECKPOINT(9) diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index 51b534d01f..9f1485ad0b 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -41,223 +41,55 @@ #include <io.h> #include <asm/mmu.h> -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, -}; - -static iomux_v3_cfg_t tx53_pads[] = { - /* UART1 */ - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - - /* setup FEC PHY pins for GPIO function */ - MX53_PAD_FEC_REF_CLK__GPIO1_23, - MX53_PAD_FEC_MDC__GPIO1_31, - MX53_PAD_FEC_MDIO__GPIO1_22, - MX53_PAD_FEC_RXD0__GPIO1_27, - MX53_PAD_FEC_RXD1__GPIO1_26, - MX53_PAD_FEC_RX_ER__GPIO1_24, - MX53_PAD_FEC_TX_EN__GPIO1_28, - MX53_PAD_FEC_TXD0__GPIO1_30, - MX53_PAD_FEC_TXD1__GPIO1_29, - MX53_PAD_FEC_CRS_DV__GPIO1_25, - - /* FEC PHY reset */ - MX53_PAD_PATA_DA_0__GPIO7_6, - /* FEC PHY power */ - MX53_PAD_EIM_D20__GPIO3_20, - - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - - /* SD1_CD */ - MX53_PAD_EIM_D24__GPIO3_24, - - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, -}; - -#define TX53_SD1_CD IMX_GPIO_NR(3, 24) - -static struct esdhc_platform_data tx53_sd1_data = { - .cd_gpio = TX53_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, - .caps = MMC_CAP_4_BIT_DATA, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#define FEC_POWER_GPIO IMX_GPIO_NR(3, 20) -#define FEC_RESET_GPIO IMX_GPIO_NR(7, 6) - -static struct tx53_fec_gpio_setup { - iomux_v3_cfg_t pad; - unsigned gpio:9, - dir:1, - level:1; -} tx53_fec_gpios[] = { - { MX53_PAD_PATA_DA_0__GPIO7_6, FEC_RESET_GPIO, 1, 0, }, /* PHY reset */ - { MX53_PAD_EIM_D20__GPIO3_20, FEC_POWER_GPIO, 1, 1, }, /* PHY power enable */ - { MX53_PAD_FEC_REF_CLK__GPIO1_23, IMX_GPIO_NR(1, 23), 0, }, /* ENET_CLK */ - { MX53_PAD_FEC_MDC__GPIO1_31, IMX_GPIO_NR(1, 31), 1, 0, }, /* MDC */ - { MX53_PAD_FEC_MDIO__GPIO1_22, IMX_GPIO_NR(1, 22), 1, 0, }, /* MDIO */ - { MX53_PAD_FEC_RXD0__GPIO1_27, IMX_GPIO_NR(1, 27), 1, 1, }, /* Mode0/RXD0 */ - { MX53_PAD_FEC_RXD1__GPIO1_26, IMX_GPIO_NR(1, 26), 1, 1, }, /* Mode1/RXD1 */ - { MX53_PAD_FEC_RX_ER__GPIO1_24, IMX_GPIO_NR(1, 24), 0, }, /* RX_ER */ - { MX53_PAD_FEC_TX_EN__GPIO1_28, IMX_GPIO_NR(1, 28), 1, 0, }, /* TX_EN */ - { MX53_PAD_FEC_TXD0__GPIO1_30, IMX_GPIO_NR(1, 30), 1, 0, }, /* TXD0 */ - { MX53_PAD_FEC_TXD1__GPIO1_29, IMX_GPIO_NR(1, 29), 1, 0, }, /* TXD1 */ - { MX53_PAD_FEC_CRS_DV__GPIO1_25, IMX_GPIO_NR(1, 25), 1, 1, }, /* Mode2/CRS_DV */ -}; - -static iomux_v3_cfg_t tx53_fec_pads[] = { - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, -}; - -static inline void tx53_fec_init(void) -{ - int i; - - /* Configure LAN8700 pads as GPIO and set up - * necessary strap options for PHY - */ - for (i = 0; i < ARRAY_SIZE(tx53_fec_gpios); i++) { - struct tx53_fec_gpio_setup *gs = &tx53_fec_gpios[i]; - - if (gs->dir) - gpio_direction_output(gs->gpio, gs->level); - else - gpio_direction_input(gs->gpio); - - mxc_iomux_v3_setup_pad(gs->pad); - } - - /* - *Turn on phy power, leave in reset state - */ - gpio_set_value(FEC_POWER_GPIO, 1); - - /* - * Wait some time to let the phy activate the internal regulator - */ - mdelay(10); - - /* - * Deassert reset, phy latches the rest of bootstrap pins - */ - gpio_set_value(FEC_RESET_GPIO, 1); - - /* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with - * the external RESET signal) which is deactivated 21ms after - * power on and latches the strap options. - * Delay for 22ms to ensure, that the internal POR is inactive - * before reconfiguring the strap pins. - */ - mdelay(22); - - /* - * The phy is ready, now configure imx51 pads for fec operation - */ - mxc_iomux_v3_setup_multiple_pads(tx53_fec_pads, - ARRAY_SIZE(tx53_fec_pads)); -} - static int tx53_devices_init(void) { - imx53_iim_register_fec_ethaddr(); - tx53_fec_init(); - imx53_add_fec(&fec_info); - imx53_add_mmc0(&tx53_sd1_data); - imx53_add_nand(&nand_info); - - armlinux_set_architecture(MACH_TYPE_TX53); - - /* rev xx30 can boot from nand or USB */ - imx53_bbu_internal_nand_register_handler("nand-xx30", - BBU_HANDLER_FLAG_DEFAULT, SZ_512K); - - /* rev 1011 can boot from MMC/SD, other bootsource currently unknown */ - imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", 0); + const char *envdev; + uint32_t flag_nand = 0; + uint32_t flag_mmc = 0; - return 0; -} + if (!of_machine_is_compatible("karo,tx53")) + return 0; -device_initcall(tx53_devices_init); - -static int tx53_part_init(void) -{ - const char *envdev; + barebox_set_model("Ka-Ro TX53"); + barebox_set_hostname("tx53"); switch (bootsource_get()) { case BOOTSOURCE_MMC: - devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + devfs_add_partition("mmc0", 0x00000, SZ_512K, + DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("mmc0", SZ_512K, SZ_1M, + DEVFS_PARTITION_FIXED, "env0"); envdev = "MMC"; + flag_mmc |= BBU_HANDLER_FLAG_DEFAULT; break; case BOOTSOURCE_NAND: default: - devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); + devfs_add_partition("nand0", 0x00000, 0x80000, + DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x80000, 0x100000, DEVFS_PARTITION_FIXED, "env_raw"); + devfs_add_partition("nand0", 0x80000, 0x100000, + DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); envdev = "NAND"; + flag_nand |= BBU_HANDLER_FLAG_DEFAULT; break; } - printf("Using environment in %s\n", envdev); + armlinux_set_architecture(MACH_TYPE_TX53); - return 0; -} -late_initcall(tx53_part_init); + /* rev xx30 can boot from nand or USB */ + imx53_bbu_internal_nand_register_handler("nand-xx30", + flag_nand, SZ_512K); -static int tx53_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); + /* rev 1011 can boot from MMC/SD, other bootsource currently unknown */ + imx53_bbu_internal_mmc_register_handler("mmc-1011", + "/dev/mmc0", flag_mmc); - if (!IS_ENABLED(CONFIG_TX53_REV_XX30)) + if (of_machine_is_compatible("karo,tx53-1011")) imx53_init_lowlevel(1000); - barebox_set_model("Ka-Ro TX53"); - barebox_set_hostname("tx53"); + printf("Using environment in %s\n", envdev); - imx53_add_uart0(); return 0; } -console_initcall(tx53_console_init); +device_initcall(tx53_devices_init); diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg new file mode 100644 index 0000000000..6962abd5e6 --- /dev/null +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg @@ -0,0 +1,177 @@ +loadaddr 0x71000000 +soc imx53 +dcdofs 0x400 + +wm 32 0x53fa8004 0x00194005 /* set LDO to 1.3V */ + +/* "AXI/DDR FREQ" fuse seems programmed to 1, so the SDRAM runs at 333 MHz */ +/* "BT_Freq" fuse seems unprogrammed and 0, so the CPU core runs at 800 MHz */ + +/* re-program the PLL2 for the SDRAM clock prior signal calibration */ + +wm 32 0x63F84000 0x00001232 /* MX5_PLL_DP_CTL */ +wm 32 0x63F84004 0x00000002 /* MX5_PLL_DP_CONFIG */ +wm 32 0x63F84008 0x00000081 /* MX5_PLL_DP_OP */ +wm 32 0x63F8401c 0x00000081 /* MX5_PLL_DP_HFS_OP */ +wm 32 0x63F8400c 0x00000002 /* MX5_PLL_DP_MFD */ +wm 32 0x63F84020 0x00000002 /* MX5_PLL_DP_HFS_MFD */ +wm 32 0x63F84010 0x00000001 /* MX5_PLL_DP_MFN */ +wm 32 0x63F84024 0x00000001 /* MX5_PLL_DP_HFS_MFN */ +wm 32 0x63F84000 0x00001232 /* MX5_PLL_DP_CTL */ +/* wait until PLL has locked again */ +check 32 until_all_bits_set 0x63F84000 0x00000001 + +wm 32 0x53fa8340 0x00000011 /* GPIO_17 => RESET_OUT */ +wm 32 0x63fd800c 0x00000000 /* M4IF: MUX NFC signals on WEIM TODO */ +/* Setup clock tree */ +wm 32 0x53fd4014 0x00888944 /* CBCDR for SDRAM clock > 333 AXI_A: /1, AXI_B: /2 */ +wm 32 0x53fd4018 0x00016154 /* CBCMR SDRAM Controller uses AXI_A */ +/* peripherals */ +wm 32 0x53fd401c 0xa6a2a020 /* CSCMR1 */ +wm 32 0x53fd4020 0xb6b12f0a /* CSCMR2 */ +wm 32 0x53fd4024 0x00080b18 /* CSCDR1 */ + +wm 32 0x53fa8724 0x00000000 /* DDR_TYPE: DDR3 */ +wm 32 0x53fa86f4 0x00000000 /* DDRMODE_CTL */ +wm 32 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +wm 32 0x53fa86fc 0x00000080 /* GRP_DDRPKE */ +wm 32 0x53fa8710 0x00000000 /* GRP_DDRHYS */ +wm 32 0x53fa8708 0x00000040 /* GRP_DDRPK */ + +wm 32 0x53fa8584 0x00300000 /* DQM0 */ +wm 32 0x53fa8594 0x00300000 /* DQM1 */ +wm 32 0x53fa8560 0x00300000 /* DQM2 */ +wm 32 0x53fa8554 0x00300000 /* DQM3 */ + +wm 32 0x53fa857c 0x00b00040 /* SDQS0 */ +wm 32 0x53fa8590 0x00b00040 /* SDQS1 */ +wm 32 0x53fa8568 0x00b00040 /* SDQS2 */ +wm 32 0x53fa8558 0x00b00040 /* SDQS3 */ + +wm 32 0x53fa8580 0x00300040 /* SDODT0 */ +wm 32 0x53fa8578 0x00300000 /* SDCLK0 */ + +wm 32 0x53fa8564 0x00300040 /* SDODT1 */ +wm 32 0x53fa8570 0x00300000 /* SDCLK1 */ + +wm 32 0x53fa858c 0x000000c0 /* SDCKE0 */ +wm 32 0x53fa855c 0x000000c0 /* SDCKE1 */ + +wm 32 0x53fa8574 0x00300000 /* DRAM_CAS */ +wm 32 0x53fa8588 0x00300000 /* DRAM_RAS */ + +wm 32 0x53fa86f0 0x00300000 /* GRP_ADDDS */ +wm 32 0x53fa8720 0x00300000 /* GRP_CTLDS */ +wm 32 0x53fa8718 0x00300000 /* GRP_B0DS */ +wm 32 0x53fa871c 0x00300000 /* GRP_B1DS */ +wm 32 0x53fa8728 0x00300000 /* GRP_B2DS */ +wm 32 0x53fa872c 0x00300000 /* GRP_B3DS */ + +/* calibration defaults */ +wm 32 0x63fd904c 0x001f001f +wm 32 0x63fd9050 0x001f001f +wm 32 0x63fd907c 0x011e011e +wm 32 0x63fd9080 0x011f0120 +wm 32 0x63fd9088 0x3a393d3b +wm 32 0x63fd9090 0x3f3f3f3f + +wm 32 0x63fd9018 0x00000740 +wm 32 0x63fd9000 0x83190000 +wm 32 0x63fd900c 0x3f435333 +wm 32 0x63fd9010 0x926e8a63 +wm 32 0x63fd9014 0x01ff00db + +wm 32 0x63fd902c 0x000026d2 +wm 32 0x63fd9030 0x00430f24 +wm 32 0x63fd9008 0x1b333030 +wm 32 0x63fd9004 0x0002006d + +/* use the SDRAM controller for specific accesses into the SDRAM */ +wm 32 0x63fd901c 0x00008000 /* CON_REQ -> aquire AXI bus */ +check 32 until_all_bits_set 0x63fd901c 0x00004000 /* wait for acknowledge */ + +/* Setup SDRAM's MR0..3 at CS0 */ +wm 32 0x63fd901c 0x004080b2 /* MRS: MR2 */ +wm 32 0x63fd901c 0x000080b3 /* MRS: MR3 */ +wm 32 0x63fd901c 0x000480b1 /* MRS: MR1 */ +wm 32 0x63fd901c 0x052080b0 /* MRS: MR0 */ + +/* no memory at CS1 */ + +wm 32 0x63fd9020 0x0000c000 /* disable refresh during calibration */ +wm 32 0x63fd9058 0x00022222 + +wm 32 0x63fd90d0 0x00000003 /* select default compare pattern for calibration */ + +/* ZQ calibration */ +wm 32 0x63fd901c 0x04008010 /* precharge all */ +wm 32 0x63fd901c 0x00008040 /* MRS: ZQ calibration */ +wm 32 0x63fd9040 0x0539002b /* Force ZQ calibration */ +check 32 until_all_bits_clear 0x63fd9040 0x00010000 /* wait until ZQ calibration is done */ + +/* DQS calibration */ +wm 32 0x63fd901c 0x04008010 /* precharge all */ +wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */ +wm 32 0x63fd907c 0x90000000 /* reset RD fifo and start DQS calib. */ + +check 32 until_all_bits_clear 0x63fd907c 0x90000000 /* wait until DQS calibration is done */ +wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */ + +/* WR DL calibration */ +wm 32 0x63fd901c 0x00008000 +wm 32 0x63fd901c 0x04008010 /* precharge all */ +wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */ +wm 32 0x63fd90a4 0x00000010 /* start WR DL calibration */ + +check 32 until_all_bits_clear 0x63fd90a4 0x00000010 /* wait until WR DL calibration is done */ +wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */ + +/* RD DL calibration */ +wm 32 0x63fd901c 0x04008010 /* precharge all */ +wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */ +wm 32 0x63fd90a0 0x00000010 /* start WR DL calibration */ + +check 32 until_all_bits_clear 0x63fd90a0 0x00000010 /* wait until RD DL calibration is done */ +wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */ + +wm 32 0x63fd9020 0x00001800 /* refresh interval: 4 cycles every 64kHz period */ +wm 32 0x63fd9004 0x0002556d + +/* DDR calibration done */ +wm 32 0x63fd901c 0x00000000 + +/* setup NFC pads */ + +/* MUX_SEL */ +wm 32 0x53fa819c 0x00000000 /* EIM_DA0 */ +wm 32 0x53fa81a0 0x00000000 /* EIM_DA1 */ +wm 32 0x53fa81a4 0x00000000 /* EIM_DA2 */ +wm 32 0x53fa81a8 0x00000000 /* EIM_DA3 */ +wm 32 0x53fa81ac 0x00000000 /* EIM_DA4 */ +wm 32 0x53fa81b0 0x00000000 /* EIM_DA5 */ +wm 32 0x53fa81b4 0x00000000 /* EIM_DA6 */ +wm 32 0x53fa81b8 0x00000000 /* EIM_DA7 */ +wm 32 0x53fa81dc 0x00000000 /* WE_B */ +wm 32 0x53fa81e0 0x00000000 /* RE_B */ +wm 32 0x53fa8228 0x00000000 /* CLE */ +wm 32 0x53fa822c 0x00000000 /* ALE */ +wm 32 0x53fa8230 0x00000000 /* WP_B */ +wm 32 0x53fa8234 0x00000000 /* RB0 */ +wm 32 0x53fa8238 0x00000000 /* CS0 */ + +/* PAD_CTL */ +wm 32 0x53fa84ec 0x000000e4 /* EIM_DA0 */ +wm 32 0x53fa84f0 0x000000e4 /* EIM_DA1 */ +wm 32 0x53fa84f4 0x000000e4 /* EIM_DA2 */ +wm 32 0x53fa84f8 0x000000e4 /* EIM_DA3 */ +wm 32 0x53fa84fc 0x000000e4 /* EIM_DA4 */ +wm 32 0x53fa8500 0x000000e4 /* EIM_DA5 */ +wm 32 0x53fa8504 0x000000e4 /* EIM_DA6 */ +wm 32 0x53fa8508 0x000000e4 /* EIM_DA7 */ +wm 32 0x53fa852c 0x00000004 /* NANDF_WE_B */ +wm 32 0x53fa8530 0x00000004 /* NANDF_RE_B */ +wm 32 0x53fa85a0 0x00000004 /* NANDF_CLE_B */ +wm 32 0x53fa85a4 0x00000004 /* NANDF_ALE_B */ +wm 32 0x53fa85a8 0x000000e4 /* NANDF_WE_B */ +wm 32 0x53fa85ac 0x000000e4 /* NANDF_RB0 */ +wm 32 0x53fa85b0 0x00000004 /* NANDF_CS0 */ diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg index aec88ad59b..2b47d63bd4 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg @@ -3,9 +3,9 @@ soc imx53 dcdofs 0x400 wm 32 0x53fd4068 0xffcc0fff wm 32 0x53fd406c 0x000fffc3 -wm 32 0x53fd4070 0x033c0000 +wm 32 0x53fd4070 0x0f3c0000 wm 32 0x53fd4074 0x00000000 -wm 32 0x53fd4078 0x00000000 +wm 32 0x53fd4078 0x00000c00 wm 32 0x53fd407c 0x00fff033 wm 32 0x53fd4080 0x0f00030f wm 32 0x53fd4084 0xfff00000 @@ -68,29 +68,29 @@ wm 32 0x63fd90d0 0x00000003 wm 32 0x63fd901c 0x04008010 wm 32 0x63fd901c 0x00008040 wm 32 0x63fd9040 0x0539002b -check 32 while_all_bits_set 0x63fd9040 0x00010000 +check 32 until_all_bits_clear 0x63fd9040 0x00010000 wm 32 0x63fd901c 0x00048033 wm 32 0x63fd901c 0x00848231 wm 32 0x63fd901c 0x00000000 wm 32 0x63fd9048 0x00000001 -check 32 while_all_bits_set 0x63fd9048 0x00000001 +check 32 until_all_bits_clear 0x63fd9048 0x00000001 wm 32 0x63fd901c 0x00048031 wm 32 0x63fd901c 0x00008033 wm 32 0x63fd901c 0x04008010 wm 32 0x63fd901c 0x00048033 wm 32 0x63fd907c 0x90000000 -check 32 while_all_bits_set 0x63fd907c 0x90000000 +check 32 until_all_bits_clear 0x63fd907c 0x90000000 wm 32 0x63fd901c 0x00008033 wm 32 0x63fd901c 0x00000000 wm 32 0x63fd901c 0x04008010 wm 32 0x63fd901c 0x00048033 wm 32 0x63fd90a4 0x00000010 -check 32 while_all_bits_set 0x63fd90a4 0x00000010 +check 32 until_all_bits_clear 0x63fd90a4 0x00000010 wm 32 0x63fd901c 0x00008033 wm 32 0x63fd901c 0x04008010 wm 32 0x63fd901c 0x00048033 wm 32 0x63fd90a0 0x00000010 -check 32 while_all_bits_set 0x63fd90a0 0x00000010 +check 32 until_all_bits_clear 0x63fd90a0 0x00000010 wm 32 0x63fd901c 0x00008033 wm 32 0x63fd901c 0x00000000 wm 32 0x53fa8004 0x00194005 diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c index 9f584fa256..cb324b2007 100644 --- a/arch/arm/boards/karo-tx53/lowlevel.c +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -1,23 +1,68 @@ #include <common.h> +#include <debug_ll.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <mach/imx5.h> #include <mach/imx53-regs.h> #include <mach/esdctl.h> #include <mach/generic.h> +#include <asm/cache.h> -void __naked barebox_arm_reset_vector(void) +extern char __dtb_imx53_tx53_xx30_start[]; +extern char __dtb_imx53_tx53_1011_start[]; + +static inline void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX53_UART1_BASE_ADDR); + + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x270); + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x274); + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x878); + + imx53_ungate_all_peripherals(); + imx53_uart_setup(uart); + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static void __imx53_tx53_init(int is_xx30) { + void *fdt; + void *fdt_blob_fixed_offset = __dtb_imx53_tx53_1011_start; + + arm_early_mmu_cache_invalidate(); imx5_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + barrier(); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); - /* - * For the TX53 rev 8030 the SDRAM setup is not stable without - * the proper PLL setup. It will crash once we enable the MMU, - * so do the PLL setup here. - */ - if (IS_ENABLED(CONFIG_TX53_REV_XX30)) + if (is_xx30) { imx53_init_lowlevel_early(800); + fdt_blob_fixed_offset = __dtb_imx53_tx53_xx30_start; + } + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); - imx53_barebox_entry(NULL); + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + + imx53_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx53_tx53_xx30_samsung, r0, r1, r2) +{ + __imx53_tx53_init(1); +} + +ENTRY_FUNCTION(start_imx53_tx53_xx30, r0, r1, r2) +{ + __imx53_tx53_init(1); +} + +ENTRY_FUNCTION(start_imx53_tx53_1011, r0, r1, r2) +{ + __imx53_tx53_init(0); } diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg index b5c59e3c3c..7e244edfd3 100644 --- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg @@ -1,12 +1,12 @@ /* MDMISC mirroring interleaved (row/bank/col) */ wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63 @@ -34,7 +34,7 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001 -check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e @@ -62,11 +62,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000 -check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000 +check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 @@ -81,16 +81,16 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 @@ -98,4 +98,4 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00001006 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P1_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index c58ef4e35a..3f6578e19c 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -92,11 +92,11 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x83190000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -117,7 +117,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -126,14 +126,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index 56cb3292a9..165b69fb19 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -119,11 +119,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4 wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd @@ -145,7 +145,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -159,19 +159,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index 4eaca00fc7..fc00de957c 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -128,11 +128,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 -check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -155,7 +155,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -169,18 +169,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg index e6b6098973..fae10423c5 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg @@ -21,7 +21,7 @@ wm 32 0x63f8001c 0x00000080 wm 32 0x63f80020 0x00000002 wm 32 0x63f80024 0x00000001 wm 32 0x63f80000 0x00001232 -check 8 while_any_bit_clear 0x63f80000 0x01 +check 8 until_any_bit_set 0x63f80000 0x01 # Switch pll1_sw_clk to pll1 wm 32 0x53fd400c 0x00000000 @@ -38,7 +38,7 @@ wm 32 0x53FD4098 0x80000004 # CCM DDR div 4 / 200MHz wm 32 0x53fd4098 0x80000004 -check 32 while_all_bits_set 0x53fd408c 0x00000004 +check 32 until_all_bits_clear 0x53fd408c 0x00000004 # IOMUX wm 32 0x53fa8490 0x00180000 @@ -163,4 +163,4 @@ wm 32 0x1400025c 0x00102201 # start DDR wm 32 0x14000000 0x00000101 -check 32 while_any_bit_clear 0x140000a8 0x00000010 +check 32 until_any_bit_set 0x140000a8 0x00000010 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg index ffceac34b5..94436a7b54 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg @@ -22,7 +22,7 @@ wm 32 0x63f8001c 0x00000080 wm 32 0x63f80020 0x000000b3 wm 32 0x63f80024 0x000000b4 wm 32 0x63f80000 0x00001236 -check 8 while_any_bit_clear 0x63f80000 0x01 +check 8 until_any_bit_set 0x63f80000 0x01 # Switch pll1_sw_clk to pll1 wm 32 0x53fd400c 0x00000000 @@ -39,7 +39,7 @@ wm 32 0x53FD4098 0x80000004 # CCM DDR div 3 / 266MHz wm 32 0x53fd4098 0x80000003 -check 32 while_all_bits_set 0x53fd408c 0x00000004 +check 32 until_all_bits_clear 0x53fd408c 0x00000004 # IOMUX wm 32 0x53fa86ac 0x04000000 @@ -173,4 +173,4 @@ wm 32 0x1400025c 0x00100b01 # start DDR wm 32 0x14000000 0x00000501 -check 32 while_any_bit_clear 0x140000a8 0x00000010 +check 32 until_any_bit_set 0x140000a8 0x00000010 diff --git a/arch/arm/boards/kontron-samx6i/Makefile b/arch/arm/boards/kontron-samx6i/Makefile new file mode 100644 index 0000000000..816962241a --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o mem.o +lwl-y += lowlevel.o mem.o diff --git a/arch/arm/boards/kontron-samx6i/board.c b/arch/arm/boards/kontron-samx6i/board.c new file mode 100644 index 0000000000..01826b67d2 --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/board.c @@ -0,0 +1,103 @@ +/* + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define pr_fmt(fmt) "samx6i: " fmt + +#include <malloc.h> +#include <envfs.h> +#include <environment.h> +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <of.h> +#include <mach/bbu.h> +#include <mach/esdctl.h> + +#include <asm/armlinux.h> + +resource_size_t samx6i_get_size(void); + +/* + * On this board the SDRAM size is always configured by pin selection. + */ +static int samx6i_sdram_fixup(void) +{ + if (!(of_machine_is_compatible("kontron,imx6q-samx6i") || + of_machine_is_compatible("kontron,imx6dl-samx6i"))) + return 0; + + imx_esdctl_disable(); + + return 0; +} +postcore_initcall(samx6i_sdram_fixup); + +static int samx6i_mem_init(void) +{ + resource_size_t size = 0; + + if (!(of_machine_is_compatible("kontron,imx6q-samx6i") || + of_machine_is_compatible("kontron,imx6dl-samx6i"))) + return 0; + + size = samx6i_get_size(); + if (size) + arm_add_mem_device("ram0", 0x10000000, size); + + return 0; +} +mem_initcall(samx6i_mem_init); + +static int samx6i_devices_init(void) +{ + int ret; + char *environment_path, *envdev; + int flag_spi = 0, flag_mmc = 0; + + if (!(of_machine_is_compatible("kontron,imx6q-samx6i") || + of_machine_is_compatible("kontron,imx6dl-samx6i"))) + return 0; + + barebox_set_hostname("samx6i"); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + environment_path = basprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); + envdev = "MMC"; + flag_mmc = BBU_HANDLER_FLAG_DEFAULT; + break; + default: + environment_path = basprintf("/chosen/environment-spinor"); + envdev = "SPI NOR flash"; + flag_spi = BBU_HANDLER_FLAG_DEFAULT; + break; + } + + ret = of_device_enable_path(environment_path); + if (ret < 0) + pr_warn("Failed to enable environment partition '%s' (%d)\n", + environment_path, ret); + free(environment_path); + + pr_notice("Using environment in %s\n", envdev); + + imx6_bbu_internal_spi_i2c_register_handler("m25p80", + "/dev/m25p0.bootloader", + flag_spi); + + imx6_bbu_internal_mmc_register_handler("mmc3", + "/dev/mmc3.bootloader", + flag_mmc); + + return 0; +} +device_initcall(samx6i_devices_init); diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg new file mode 100644 index 0000000000..9906617083 --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg @@ -0,0 +1,102 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0774 0x000c0000 +wm 32 0x020e0754 0x00000000 + +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 + +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e0494 0x000c0030 +wm 32 0x020e04a4 0x00003000 +wm 32 0x020e04a8 0x00003000 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00003030 +wm 32 0x020e04b8 0x00003030 +wm 32 0x020e076c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000038 +wm 32 0x020e04c0 0x00000038 +wm 32 0x020e04c4 0x00000038 +wm 32 0x020e04c8 0x00000038 +wm 32 0x020e04cc 0x00000038 +wm 32 0x020e04d0 0x00000038 +wm 32 0x020e04d4 0x00000038 +wm 32 0x020e04d8 0x00000038 + +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000030 +wm 32 0x020e0770 0x00000030 +wm 32 0x020e0778 0x00000030 +wm 32 0x020e077c 0x00000030 +wm 32 0x020e0780 0x00000030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e0470 0x00000030 +wm 32 0x020e0474 0x00000030 +wm 32 0x020e0478 0x00000030 +wm 32 0x020e047c 0x00000030 +wm 32 0x020e0480 0x00000030 +wm 32 0x020e0484 0x00000030 +wm 32 0x020e0488 0x00000030 +wm 32 0x020e048c 0x000C0030 + +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b080c 0x0040003c +wm 32 0x021b0810 0x0032003e + +wm 32 0x021b083c 0x42350231 +wm 32 0x021b0840 0x021a0218 +wm 32 0x021b0848 0x4b4b4e49 +wm 32 0x021b0850 0x3f3f3035 + +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + + +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 + +wm 32 0x021b0004 0x0002002d +wm 32 0x021b0008 0x00333030 +wm 32 0x021b000c 0x696d5323 +wm 32 0x021b0010 0xb66e8c63 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x006d0e21 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b0000 0x84190000 +wm 32 0x021b001c 0x04008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x07208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00022227 +wm 32 0x021b4818 0x00022227 +wm 32 0x021b0004 0x0002556d +wm 32 0x021b4004 0x00011006 +wm 32 0x021b001c 0x00000000 + +wm 32 0x020e0010 0xf00000ff + +wm 32 0x020e0018 0x00070007 +wm 32 0x020e001c 0x00070007 diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg new file mode 100644 index 0000000000..7e6ffd7983 --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg @@ -0,0 +1,118 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 + +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 + +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 + +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 + +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 + +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 + +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 + +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 + +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 + +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000C0000 + +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 + +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +wm 32 0x021b0018 0x00081740 + +wm 32 0x021b001c 0x00008000 +wm 32 0x021b000c 0x898E7975 +wm 32 0x021b0010 0xFF538E64 +wm 32 0x021b0014 0x01FF00DD +wm 32 0x021b002c 0x000026D2 + +wm 32 0x021b0030 0x005B0E21 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b0004 0x00025576 +/* CS0_END = 4GB */ +wm 32 0x021b0040 0x0000007F + +wm 32 0x021b0000 0x841A0000 + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x09408030 + +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xA1390003 +wm 32 0x021b4800 0xA1390003 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00022227 +wm 32 0x021b4818 0x00022227 + +wm 32 0x021b083c 0x42740304 +wm 32 0x021b0840 0x026e0265 +wm 32 0x021b483c 0x02750306 +wm 32 0x021b4840 0x02720244 +wm 32 0x021b0848 0x463d4041 +wm 32 0x021b4848 0x42413c47 +wm 32 0x021b0850 0x37414441 +wm 32 0x021b4850 0x4633473b + +wm 32 0x021b080c 0x0025001f +wm 32 0x021b0810 0x00290027 + +wm 32 0x021b480c 0x001f002b +wm 32 0x021b4810 0x000f0029 + +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 + +wm 32 0x021b001c 0x00000000 +wm 32 0x021b0404 0x00011006 + +/* enable AXI cache for VDOA/VPU/IPU */ +wm 32 0x020e0010 0xF00000FF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c new file mode 100644 index 0000000000..4113ddbb40 --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/lowlevel.c @@ -0,0 +1,66 @@ +/* + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <debug_ll.h> +#include <common.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/sections.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <mach/imx6.h> +#include <mach/esdctl.h> + +resource_size_t samx6i_get_size(void); + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x4, iomuxbase + 0x016c); + + imx6_ungate_all_peripherals(); + imx6_uart_setup_ll(); + + putc_ll('>'); +} + +static void __noreturn start_imx6_samx6i_common(void *fdt_blob_fixed_offset) +{ + void *fdt; + resource_size_t size = 0; + + size = samx6i_get_size(); + + imx6_cpu_lowlevel_init(); + arm_setup_stack(0x00920000 - 8); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + + barebox_arm_entry(0x10000000, size, fdt); +} + +extern char __dtb_imx6dl_samx6i_start[]; +extern char __dtb_imx6q_samx6i_start[]; + +ENTRY_FUNCTION(start_imx6q_samx6i, r0, r1, r2) +{ + start_imx6_samx6i_common(__dtb_imx6q_samx6i_start); +} + +ENTRY_FUNCTION(start_imx6dl_samx6i, r0, r1, r2) +{ + start_imx6_samx6i_common(__dtb_imx6dl_samx6i_start); +} diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c new file mode 100644 index 0000000000..ab9969e32c --- /dev/null +++ b/arch/arm/boards/kontron-samx6i/mem.c @@ -0,0 +1,85 @@ +/* + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/sizes.h> +#include <common.h> +#include <mach/iomux-mx6.h> +#include <mach/imx-gpio.h> +#include <mach/imx6.h> + +#define PCBVERSION_PIN IMX_GPIO_NR(2, 2) +#define PCBID0_PIN IMX_GPIO_NR(6, 7) +#define PCBID1_PIN IMX_GPIO_NR(6, 9) + +#define MX6S_PAD_NANDF_CLE__GPIO_6_7 \ + IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0) +#define MX6S_PAD_NANDF_WP_B__GPIO_6_9 \ + IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0) +#define MX6S_PAD_NANDF_D2__GPIO_2_2 \ + IOMUX_PAD(0x028c, 0x0674, 5, 0x0000, 0, 0) + +resource_size_t samx6i_get_size(void) +{ + resource_size_t size = 0; + int ver, id0, id1; + int cpu_type = __imx6_cpu_type(); + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *gpio6 = IOMEM(MX6_GPIO6_BASE_ADDR); + void __iomem *gpio2 = IOMEM(MX6_GPIO2_BASE_ADDR); + + if (cpu_type == IMX6_CPUTYPE_IMX6D || + cpu_type == IMX6_CPUTYPE_IMX6Q) { + imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_CLE__GPIO_6_7); + imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_WP_B__GPIO_6_9); + imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_D2__GPIO_2_2); + } else if (cpu_type == IMX6_CPUTYPE_IMX6S || + cpu_type == IMX6_CPUTYPE_IMX6DL) { + imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_CLE__GPIO_6_7); + imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_WP_B__GPIO_6_9); + imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_D2__GPIO_2_2); + }; + + imx6_gpio_direction_input(gpio6, 6); + imx6_gpio_direction_input(gpio6, 9); + imx6_gpio_direction_input(gpio2, 2); + + ver = imx6_gpio_val(gpio2, 2); + id0 = imx6_gpio_val(gpio6, 7); + id1 = imx6_gpio_val(gpio6, 9); + + if (cpu_type == IMX6_CPUTYPE_IMX6D || + cpu_type == IMX6_CPUTYPE_IMX6Q) { + if (ver) + size = SZ_1G; + else if (id0 && id1) + size = SZ_2G; + else if (id0) + size = SZ_2G; + else if (id1) + size = SZ_1G; + else + size = SZ_512M; + } else if (cpu_type == IMX6_CPUTYPE_IMX6S || + cpu_type == IMX6_CPUTYPE_IMX6DL) { + if (ver) + size = SZ_512M; + if (id0 && id1) + size = SZ_2G; + else if (id0) + size = SZ_1G; + else if (id1) + size = SZ_512M; + else + size = SZ_128M; + } + + return size; +} diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index 6c256e8fc5..6e08b6c1b1 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -65,7 +65,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 -check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 +check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 @@ -75,4 +75,4 @@ wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f -check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 +check 32 until_any_bit_set MX7_DDRC_STAT 0x1 diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index 177f4e8bdc..bb858907a4 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -45,7 +45,7 @@ CHECKPOINT(2) /* * Wait for PLLs to lock */ -check 32 while_any_bit_clear 0x40050030 0x80000000 +check 32 until_any_bit_set 0x40050030 0x80000000 CHECKPOINT(3) @@ -218,26 +218,26 @@ wm 32 0x400ae000 0x00000601 CHECKPOINT(7) -check 32 while_any_bit_clear 0x400ae140 0x100 -# check 32 while_any_bit_clear 0x400ae42c 0x1 -# check 32 while_any_bit_clear 0x400ae46c 0x1 -# check 32 while_any_bit_clear 0x400ae4ac 0x1 +check 32 until_any_bit_set 0x400ae140 0x100 +# check 32 until_any_bit_set 0x400ae42c 0x1 +# check 32 until_any_bit_set 0x400ae46c 0x1 +# check 32 until_any_bit_set 0x400ae4ac 0x1 CHECKPOINT(8) wm 32 0x80000000 0xa5a5a5a5 -check 32 while_any_bit_clear 0x80000000 0xa5a5a5a5 +check 32 until_any_bit_set 0x80000000 0xa5a5a5a5 wm 32 0x400ae000 0x00000600 wm 32 0x400ae000 0x00000601 -check 32 while_any_bit_clear 0x400ae140 0x100 -# check 32 while_any_bit_clear 0x400ae42c 0x1 -# check 32 while_any_bit_clear 0x400ae46c 0x1 -# check 32 while_any_bit_clear 0x400ae4ac 0x1 +check 32 until_any_bit_set 0x400ae140 0x100 +# check 32 until_any_bit_set 0x400ae42c 0x1 +# check 32 until_any_bit_set 0x400ae46c 0x1 +# check 32 until_any_bit_set 0x400ae4ac 0x1 /* wm 32 0x3f040000 0xf0 - check 32 while_any_bit_clear 0x3f040000 0x0f */ + check 32 until_any_bit_set 0x3f040000 0x0f */ CHECKPOINT(9) diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 62d623806c..426bc04651 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -10,7 +10,9 @@ CONFIG_MACH_GUF_VINCELL=y CONFIG_MACH_GUF_VINCELL_XLOAD=y CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y +CONFIG_MACH_TX53=y CONFIG_MACH_PHYTEC_SOM_IMX6=y +CONFIG_MACH_KONTRON_SAMX6I=y CONFIG_MACH_DFI_FS700_M60=y CONFIG_MACH_GUF_SANTARO=y CONFIG_MACH_REALQ7=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0526a6f407..e60e0ea0c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -19,6 +19,7 @@ pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o +pbl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o @@ -28,6 +29,8 @@ pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o pbl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o +pbl-dtb-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \ + imx6dl-samx6i.dtb.o pbl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o pbl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o diff --git a/arch/arm/dts/imx53-tx53-1011.dts b/arch/arm/dts/imx53-tx53-1011.dts new file mode 100644 index 0000000000..e9b1b3a221 --- /dev/null +++ b/arch/arm/dts/imx53-tx53-1011.dts @@ -0,0 +1,13 @@ +/dts-v1/; +#include <arm/imx53-tx53.dtsi> + +/ { + model = "Ka-Ro electronics TX53 module"; + compatible = "karo,tx53-1011", "karo,tx53", "fsl,imx53"; + + chosen { + stdout-path = &uart1; + }; + + sgtl5000: dummy { }; +}; diff --git a/arch/arm/dts/imx53-tx53-xx30.dts b/arch/arm/dts/imx53-tx53-xx30.dts new file mode 100644 index 0000000000..b9d1c65a2a --- /dev/null +++ b/arch/arm/dts/imx53-tx53-xx30.dts @@ -0,0 +1,13 @@ +/dts-v1/; +#include <arm/imx53-tx53.dtsi> + +/ { + model = "Ka-Ro electronics TX53 module"; + compatible = "karo,tx53-xx30", "karo,tx53", "fsl,imx53"; + + chosen { + stdout-path = &uart1; + }; + + sgtl5000: dummy { }; +}; diff --git a/arch/arm/dts/imx6dl-samx6i.dts b/arch/arm/dts/imx6dl-samx6i.dts new file mode 100644 index 0000000000..d688b9c6ca --- /dev/null +++ b/arch/arm/dts/imx6dl-samx6i.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6dl.dtsi" +#include "imx6qdl-smarc-samx6i.dtsi" + +/ { + model = "Kontron sAMX6i"; + compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-samx6i.dts b/arch/arm/dts/imx6q-samx6i.dts new file mode 100644 index 0000000000..83f19bcaf8 --- /dev/null +++ b/arch/arm/dts/imx6q-samx6i.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6q.dtsi" +#include "imx6qdl-smarc-samx6i.dtsi" + +/ { + model = "Kontron sAMX6i"; + compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi new file mode 100644 index 0000000000..31a12fe268 --- /dev/null +++ b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi @@ -0,0 +1,509 @@ +/* + * Copyright 2017 (C) Priit Laes <plaes@plaes.org> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + linux,stdout-path = &uart2; + + environment-spinor { + compatible = "barebox,environment"; + device-path = &flash_bareboxenv; + status = "disabled"; + }; + + environment-sd4 { + compatible = "barebox,environment"; + device-path = &usdhc4_bareboxenv; + status = "disabled"; + }; + }; + + reg_3v3_s5: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v8_s5: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3_s0: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v0_s0: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "V_1V0_S0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + i2c_pfuze: i2c-gpio-0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio_0>; + sda-gpios = <&gpio1 28 0>; + scl-gpios = <&gpio1 30 0>; + #address-cells = <1>; + #size-cells = <0>; + i2c-gpio,delay-us = <2>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_smarc>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c_pfuze { + pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + /* Looks unused by pfuze100 driver */ + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_v_core_s0: sw1ab { + regulator-name = "V_CORE_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vddsoc_s0: sw1c { + regulator-name = "V_VDDSOC_S0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v15_s0: sw2 { + regulator-name = "V_3V15_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* sw3a/b is used in dual mode, but driver does not + * support it? Although, there's no need to control + * DDR power - so just leaving dummy entries for sw3a + * and sw3b for now. + */ + sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v8_s0: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* Regulator for USB */ + reg_5v0_s0: swbst { + regulator-name = "V_5V0_S0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* Per schematics, of all VGEN's, only VGEN5 has some + * usage ... but even that - over DNI resistor + */ + vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + reg_2v5_s0: vgen5 { + regulator-name = "V_2V5_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio3 24 0>, <&gpio3 29 0>, <&gpio3 25 0>; + status = "okay"; + + flash: m25p80@0 { + compatible = "winbond,w25q16dw", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x0c0000>; + }; + + flash_bareboxenv: partition@c0000 { + label = "environment"; + reg = <0x0c0000 0x010000>; + }; + + partition@d0000 { + label = "user"; + reg = <0x0d0000 0x130000>; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_smarc>; + fsl,uart-has-rtscts; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_smarc>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_smarc>; + fsl,uart-has-rtscts; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_smarc>; +}; + +&usbotg { + /* + * no 'imx6-usb-charger-detection' + * since USB_OTG_CHD_B pin is not wired + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5v0_s0>; + status = "okay"; +}; + +&usdhc4 { + /* Internal eMMC, optional on some boards */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x0 0xe0000>; + }; + + usdhc4_bareboxenv: partition@e0000 { + label = "environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_boot>; + + pinctrl_boot: boot { + fsl,pins = < + /* GPIOS for version and id detection */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1-smarc { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; + + pinctrl_flexcan2: flexcan2-smarc { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + + pinctrl_enet_smarc: fecgrp-smarc { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_i2c_gpio_0: i2c-gpio-0-smarc { + fsl,pins = < + /* SCL GPIO */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 + /* SDA GPIO */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3-smarc { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ecspi4: ecspi4-smarc { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x80000000 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x80000000 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x80000000 + MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x80000000 + + /* In hardware, ECSPI4's SS0,SS1,SS3 are wired. + But spi-imx driver support only continuous + numbering, and only can use GPIOs (and not + ECSPI's hardware SS) for CS. So linux view + of CS numbers differs from hw view, and + pins are configured as GPIOs */ + + /* physical - CS2, in linux - CS0, either internal flash or SMARC CS0 */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000 + /* physical - CS0, in linux - CS1, either SMARC CS0 or not-connected */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 + /* physical - CS3, in linux - CS2, SMARC CS1 */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 + >; + }; + + pinctrl_pcie: pcie-smarc { + fsl,pins = < + /* RST_PCIE_A# */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 + /* PCIE_WAKE# */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x80000000 + >; + }; + + pinctrl_uart1_smarc: uart1grp-smarc { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2_smarc: uart2grp-smarc { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4_smarc: uart4grp-smarc { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5_smarc: uart5grp-smarc { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotg-grp-smarc { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 + /* TODO: Comment out power and OC gpio's for now, since + * these are not used by driver + */ + /* USB power */ + // MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000 + /* USB OC */ + // MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp-smarc { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index eb135c3f53..9052a94ea0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -289,11 +289,21 @@ config MACH_FREESCALE_MX53_VMX53 Say Y here if you are using the Voipac Technologies X53-DMM-668 module equipped with a Freescale i.MX53 Processor +config MACH_TX53 + bool "Ka-Ro TX53" + select ARCH_IMX53 + help + Say Y here if you are using the Ka-Ro tx53 board + config MACH_PHYTEC_SOM_IMX6 bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" select ARCH_IMX6 select ARCH_IMX6UL +config MACH_KONTRON_SAMX6I + bool "Kontron sAMX6i" + select ARCH_IMX6 + config MACH_DFI_FS700_M60 bool "DFI i.MX6 FS700 M60 Q7 Board" select ARCH_IMX6 @@ -606,12 +616,6 @@ config MACH_FREESCALE_MX53_SMD bool "Freescale i.MX53 SMD" select ARCH_IMX53 -config MACH_TX53 - bool "Ka-Ro TX53" - select ARCH_IMX53 - help - Say Y here if you are using the Ka-Ro tx53 board - endchoice # ---------------------------------------------------------- @@ -685,19 +689,6 @@ endchoice endif -if MACH_TX53 - -choice - prompt "TX53 board revision" -config TX53_REV_1011 - bool "1011" -config TX53_REV_XX30 - bool "8030 / 1030" - -endchoice - -endif - endmenu menu "i.MX specific settings" diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h index 5e673beef9..891c33a3f4 100644 --- a/arch/arm/mach-imx/include/mach/imx-gpio.h +++ b/arch/arm/mach-imx/include/mach/imx-gpio.h @@ -8,15 +8,21 @@ * regular gpio functions outside of lowlevel code! */ -static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *dr, - int gpio, int value) +static inline void imx_gpio_direction(void __iomem *gdir, void __iomem *dr, + int gpio, int out, int value) { uint32_t val; val = readl(gdir); - val |= 1 << gpio; + if (out) + val |= 1 << gpio; + else + val &= ~(1 << gpio); writel(val, gdir); + if (!out) + return; + val = readl(dr); if (value) val |= 1 << gpio; @@ -28,7 +34,7 @@ static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *d static inline void imx1_gpio_direction_output(void *base, int gpio, int value) { - imx_gpio_direction_output(base + 0x0, base + 0x1c, gpio, value); + imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 1, value); } #define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) @@ -36,7 +42,7 @@ static inline void imx1_gpio_direction_output(void *base, int gpio, int value) static inline void imx31_gpio_direction_output(void *base, int gpio, int value) { - imx_gpio_direction_output(base + 0x4, base + 0x0, gpio, value); + imx_gpio_direction(base + 0x4, base + 0x0, gpio, 1, value); } #define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) @@ -45,4 +51,34 @@ static inline void imx31_gpio_direction_output(void *base, int gpio, int value) #define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) #define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +static inline void imx1_gpio_direction_input(void *base, int gpio, int value) +{ + imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 0, 0); +} + +#define imx21_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) +#define imx27_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) + +static inline void imx31_gpio_direction_input(void *base, int gpio) +{ + imx_gpio_direction(base + 0x4, base + 0x0, gpio, 0, 0); +} + +#define imx25_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx35_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx51_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx53_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx6_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio) + +#define imx1_gpio_val(base, gpio) readl(base + 0x1c) & (1 << gpio) ? 1 : 0 +#define imx21_gpio_val(base, gpio) imx1_gpio_val(base, gpio) +#define imx27_gpio_val(base, gpio) imx1_gpio_val(base, gpio) + +#define imx31_gpio_val(base, gpio) readl(base) & (1 << gpio) ? 1 : 0 +#define imx25_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx35_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx51_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx53_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx6_gpio_val(base, gpio) imx31_gpio_val(base, gpio) + #endif /* __MACH_IMX_GPIO_H */ diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c index b79c8c3016..1025c9d173 100644 --- a/drivers/clk/imx/clk-imx7.c +++ b/drivers/clk/imx/clk-imx7.c @@ -676,7 +676,7 @@ static int imx7_ccm_probe(struct device_d *dev) clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); - clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); + clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); @@ -751,7 +751,8 @@ static int imx7_ccm_probe(struct device_d *dev) clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); - clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0); + clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0); + clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0); clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "osc", base + 0x4680, 0); clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usbphy1_clk", "osc", base + 0x46a0, 0); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index c46c2614d9..71c6f459ad 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -80,6 +80,13 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent, return clk_gate2(name, parent, reg, shift, 0x3, 0); } +static inline struct clk *imx_clk_gate2_shared2(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_gate2(name, parent, reg, shift, 0x3, + CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +} + static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) { diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index b84c0f7985..79f25109f9 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -17,6 +17,7 @@ #include <dma/apbh-dma.h> #include <stmp-device.h> +#include <linux/clk.h> #include <linux/list.h> #include <linux/err.h> #include <common.h> @@ -55,6 +56,7 @@ enum mxs_dma_id { struct apbh_dma { void __iomem *regs; + struct clk *clk; enum mxs_dma_id id; }; @@ -606,6 +608,17 @@ static int apbh_dma_probe(struct device_d *dev) apbh->id = id; + apbh->clk = clk_get(dev, NULL); + if (IS_ERR(apbh->clk)) + return PTR_ERR(apbh->clk); + + ret = clk_enable(apbh->clk); + if (ret) { + dev_err(dev, "Failed to enable clock: %s\n", + strerror(ret)); + return ret; + } + ret = stmp_reset_block(apbh->regs, 0); if (ret) return ret; diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c index f9ca06c62b..69afaa2ba9 100644 --- a/drivers/video/tc358767.c +++ b/drivers/video/tc358767.c @@ -1258,6 +1258,7 @@ static int tc_filter_videomodes(struct tc_data *tc, struct display_timings *timi } while (1); free(timings->modes); + timings->num_modes = 0; timings->modes = NULL; if (!num_modes) { diff --git a/images/Makefile.imx b/images/Makefile.imx index 5e0043f1f0..ac46d51c59 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -139,6 +139,21 @@ CFG_start_imx53_mba53_1gib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53- FILE_barebox-tq-mba53-1gib.img = start_imx53_mba53_1gib.pblx.imximg image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-1gib.img +pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30_samsung +CFG_start_imx53_tx53_xx30_samsung.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg +FILE_barebox-tx53-xx30-samsung.img = start_imx53_tx53_xx30_samsung.pblx.imximg +image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30-samsung.img + +pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30 +CFG_start_imx53_tx53_xx30.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30.imxcfg +FILE_barebox-tx53-xx30.img = start_imx53_tx53_xx30.pblx.imximg +image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30.img + +pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_1011 +CFG_start_imx53_tx53_1011.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-rev1011.imxcfg +FILE_barebox-tx53-1011.img = start_imx53_tx53_1011.pblx.imximg +image-$(CONFIG_MACH_TX53) += barebox-tx53-1011.img + # ----------------------- i.MX6 based boards --------------------------- pblx-$(CONFIG_MACH_REALQ7) += start_imx6_realq7 CFG_start_imx6_realq7.pblx.imximg = $(board)/datamodul-edm-qmx6/flash-header.imxcfg @@ -455,6 +470,16 @@ CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img +pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6q_samx6i +CFG_start_imx6q_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-quad.imxcfg +FILE_barebox-imx6q-samx6i.img = start_imx6q_samx6i.pblx.imximg +image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6q-samx6i.img + +pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6dl_samx6i +CFG_start_imx6dl_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-duallite.imxcfg +FILE_barebox-imx6dl-samx6i.img = start_imx6dl_samx6i.pblx.imximg +image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6dl-samx6i.img + pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64 CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg diff --git a/include/linux/clk.h b/include/linux/clk.h index 081a859729..c6465b1c90 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -323,6 +323,7 @@ struct clk *clk_register_composite(const char *name, struct device_node; struct of_phandle_args; +struct of_device_id; #if defined(CONFIG_COMMON_CLK_OF_PROVIDER) diff --git a/scripts/imx/README b/scripts/imx/README index b5cdb487a0..d573d3a6be 100644 --- a/scripts/imx/README +++ b/scripts/imx/README @@ -7,34 +7,12 @@ The imx-usb-loader tool is used to upload and start i.MX images. These are images containing a DCD (Device Configuration Data) table. To generate these images from raw binaries use the imx-image tool. -imx-image ---------- +Refer the i.MX related documentation about the DCD source files and their +content. -The imx-image tool can be used to generate imximages from raw binaries. -It requires an configuration file describing how to setup the SDRAM on -a particular board. This mainly consists of a poke table. The recognized -options in this file are: +Example for a DCD source file: -soc <soctype> soctype can be one of imx35, imx51, imx53, imx6 -loadaddr <adr> The address the binary is uploaded to -dcdofs <ofs> The offset of the image header in the image. This should be: - 0x400 - MMC/SD, NAND, serial ROM, PATA, SATA - 0x1000 - NOR Flash - 0x100 - OneNAND -wm 8 <adr> <value> do a byte memory write -wm 16 <adr> <value> do a short memory write -wm 32 <adr> <value> do a word memory write -check <width> <cond> <addr> <mask> Poll until condition becomes true. - with <cond> being one of: - while_all_bits_clear, - while_all_bits_set, - while_any_bit_clear, - while_any_bit_set -set_bits <width> <addr> <bits> set <bits> in register <addr> -clear_bits <width> <addr> <bits> clear <bits> in register <addr> -nop do nothing - -the i.MX SoCs support a wide range of fancy things doing with the flash header. +The i.MX SoCs support a wide range of fancy things doing with the flash header. We limit ourselves to a very simple case, that is the flash header has a fixed size of 0x1000 bytes. The application is expected right thereafter, so if you specify a loadaddr of 0x80000000 in the config file, the first 0x1000 bytes diff --git a/scripts/imx/imx-usb-loader.c b/scripts/imx/imx-usb-loader.c index 6052343e00..43dde8b7f2 100644 --- a/scripts/imx/imx-usb-loader.c +++ b/scripts/imx/imx-usb-loader.c @@ -935,10 +935,10 @@ static int do_dcd_v2_cmd_check(const unsigned char *dcd) } switch ((check->param & 0xf8) >> 3) { - case check_all_bits_clear: - case check_all_bits_set: - case check_any_bit_clear: - case check_any_bit_set: + case until_all_bits_clear: + case until_all_bits_set: + case until_any_bit_clear: + case until_any_bit_set: cond = (check->param & 0xf8) >> 3; break; default: @@ -966,20 +966,20 @@ static int do_dcd_v2_cmd_check(const unsigned char *dcd) data &= mask; switch (cond) { - case check_all_bits_clear: - if (data != 0) + case until_all_bits_clear: + if (data == 0) return 0; break; - case check_all_bits_set: - if (data != mask) + case until_all_bits_set: + if (data == mask) return 0; break; - case check_any_bit_clear: - if (data == mask) + case until_any_bit_clear: + if (data != mask) return 0; break; - case check_any_bit_set: - if (data == 0) + case until_any_bit_set: + if (data != 0) return 0; break; } diff --git a/scripts/imx/imx.c b/scripts/imx/imx.c index 809d8a7f71..fb6ac001e2 100644 --- a/scripts/imx/imx.c +++ b/scripts/imx/imx.c @@ -69,10 +69,10 @@ struct command { }; static const char *check_cmds[] = { - "while_all_bits_clear", /* while ((*address & mask) == 0); */ - "while_all_bits_set" , /* while ((*address & mask) == mask); */ - "while_any_bit_clear", /* while ((*address & mask) != mask); */ - "while_any_bit_set", /* while ((*address & mask) != 0); */ + "until_all_bits_clear", /* until ((*address & mask) == 0) { }; */ + "until_any_bit_clear", /* until ((*address & mask) != mask) { }; */ + "until_all_bits_set", /* until ((*address & mask) == mask) { }; */ + "until_any_bit_set", /* until ((*address & mask) != 0) { }; */ }; static void do_cmd_check_usage(void) @@ -81,10 +81,10 @@ static void do_cmd_check_usage(void) "usage: check <width> <cmd> <addr> <mask>\n" "<width> access width in bytes [1|2|4]\n" "with <cmd> one of:\n" - "while_all_bits_clear: while ((*addr & mask) == 0)\n" - "while_all_bits_set: while ((*addr & mask) == mask)\n" - "while_any_bit_clear: while ((*addr & mask) != mask)\n" - "while_any_bit_set: while ((*addr & mask) != 0)\n"); + "until_all_bits_clear: while ((*addr & mask) == 0)\n" + "until_all_bits_set: while ((*addr & mask) == mask)\n" + "until_any_bit_clear: while ((*addr & mask) != mask)\n" + "until_any_bit_set: while ((*addr & mask) != 0)\n"); } static int do_cmd_check(struct config_data *data, int argc, char *argv[]) diff --git a/scripts/imx/imx.h b/scripts/imx/imx.h index f32ae52abf..c7677f81a4 100644 --- a/scripts/imx/imx.h +++ b/scripts/imx/imx.h @@ -105,10 +105,10 @@ struct imx_dcd_v2_check { } __attribute__((packed)); enum imx_dcd_v2_check_cond { - check_all_bits_clear = 0, - check_all_bits_set = 1, - check_any_bit_clear = 2, - check_any_bit_set = 3, + until_all_bits_clear = 0, /* until ((*address & mask) == 0) { ...} */ + until_any_bit_clear = 1, /* until ((*address & mask) != mask) { ...} */ + until_all_bits_set = 2, /* until ((*address & mask) == mask) { ...} */ + until_any_bit_set = 3, /* until ((*address & mask) != 0) { ...} */ } __attribute__((packed)); int parse_config(struct config_data *data, const char *filename); |