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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-04-26 22:49:41 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-08 12:26:00 +0200 |
| commit | 3533b0eb122b8c307047880c186db41414d8a0ac (patch) | |
| tree | 6e69f685332905c2d83beb8104af37de4344a14a | |
| parent | 318a2347a779d498aa88849efc3850cebf92af5c (diff) | |
| download | barebox-3533b0eb122b8c307047880c186db41414d8a0ac.tar.gz barebox-3533b0eb122b8c307047880c186db41414d8a0ac.tar.xz | |
ARM: i.MX51: Replace expicit casts with IOMEM
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/imx51.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index ffe6a7c651..13444ccdbb 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -43,7 +43,7 @@ static int imx51_silicon_revision(void) static void imx51_ipu_mipi_setup(void) { - void __iomem *hsc_addr = (void __iomem *)MX51_MIPI_HSC_BASE_ADDR; + void __iomem *hsc_addr = IOMEM(MX51_MIPI_HSC_BASE_ADDR); u32 val; /* setup MIPI module to legacy mode */ @@ -97,7 +97,7 @@ int imx51_devices_init(void) */ static void imx51_setup_pll800_bug(void) { - void __iomem *base = (void *)MX51_PLL1_BASE_ADDR; + void __iomem *base = IOMEM(MX51_PLL1_BASE_ADDR); u32 dp_config; volatile int i; @@ -132,7 +132,7 @@ static void imx51_setup_pll800_bug(void) void imx51_init_lowlevel(unsigned int cpufreq_mhz) { - void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR; + void __iomem *ccm = IOMEM(MX51_CCM_BASE_ADDR); u32 r; int rev = imx51_silicon_revision(); @@ -167,30 +167,30 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz) switch (cpufreq_mhz) { case 600: - imx5_setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR); + imx5_setup_pll_600(IOMEM(MX51_PLL1_BASE_ADDR)); break; default: /* Default maximum 800MHz */ if (rev <= IMX_CHIP_REV_3_0) imx51_setup_pll800_bug(); else - imx5_setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR); + imx5_setup_pll_800(IOMEM(MX51_PLL1_BASE_ADDR)); break; } - imx5_setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR); + imx5_setup_pll_665(IOMEM(MX51_PLL3_BASE_ADDR)); /* Switch peripheral to PLL 3 */ writel(0x000010C0, ccm + MX5_CCM_CBCMR); writel(0x13239145, ccm + MX5_CCM_CBCDR); - imx5_setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR); + imx5_setup_pll_665(IOMEM(MX51_PLL2_BASE_ADDR)); /* Switch peripheral to PLL2 */ writel(0x19239145, ccm + MX5_CCM_CBCDR); writel(0x000020C0, ccm + MX5_CCM_CBCMR); - imx5_setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR); + imx5_setup_pll_216(IOMEM(MX51_PLL3_BASE_ADDR)); /* Set the platform clock dividers */ writel(0x00000125, MX51_ARM_BASE_ADDR + 0x14); |