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| author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2018-05-28 23:44:00 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-31 17:17:54 +0200 |
| commit | b086bf35dc8b1fc02bca67979e1a3420d21768c6 (patch) | |
| tree | 0cd87f5601a33a27b955e8f3f1ddb5bc6a252fac | |
| parent | 34706cb1f6faa5077201ee3cb809711ccbdd5c0d (diff) | |
| download | barebox-b086bf35dc8b1fc02bca67979e1a3420d21768c6.tar.gz barebox-b086bf35dc8b1fc02bca67979e1a3420d21768c6.tar.xz | |
dove: fix bit layout of DOVE_CPU_CTRL register
While creating the previous patch I checked the cpu's reference manual
to see what the affected registers actually do and noticed that bits
of the DOVE_CPU_CTRL actually used by the code doesn't match the bits
described as AHBSlaveBase in the manual.
I'm not aware of any effect (neither positive nor negative) of this
patch.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-mvebu/common.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index e951bc0627..83aeb41ae2 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -219,8 +219,8 @@ void __naked __noreturn dove_barebox_entry(void *boarddata) * The AXI units internal space base starts at the same address as the * DDR controller. */ - val = readl(DOVE_CPU_CTRL) & 0xffff0000; - val |= ((unsigned long)DOVE_SDRAM_BASE & 0xffff0000) >> 16; + val = readl(DOVE_CPU_CTRL) & 0xfff007ff; + val |= ((unsigned long)DOVE_SDRAM_BASE & 0xff800000) >> 12; writel(val, DOVE_CPU_CTRL); barebox_arm_entry(0, dove_memory_find(), boarddata); |