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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-06-12 11:47:56 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-06-13 09:56:21 +0200 |
| commit | 1a73f92dd0928305c5f693c9d80e98bb408b9514 (patch) | |
| tree | e27d5d031115f2b8857e027a791291724be434b8 | |
| parent | 96aac9a3a6a64450b82a2295c1ec147b92215487 (diff) | |
| download | barebox-1a73f92dd0928305c5f693c9d80e98bb408b9514.tar.gz barebox-1a73f92dd0928305c5f693c9d80e98bb408b9514.tar.xz | |
VFxxx: Reconcile shared DDR IOMUX DCD with schematic
The only differential signals coming out of DDRMC to the memory chip
are CLK, DQS0 and DQS1. There rest of the pins are not, so there
should be no reason to configure them as such.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg index 64f97aacd9..742275b92f 100644 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg @@ -31,26 +31,26 @@ wm 32 VF610_PAD_DDR_BA1__DDR_BA_1 VF610_DDR_PAD_CTRL wm 32 VF610_PAD_DDR_BA0__DDR_BA_0 VF610_DDR_PAD_CTRL wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B VF610_DDR_PAD_CTRL wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL_1 wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0 VF610_DDR_PAD_CTRL -wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL_1 -wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL_1 +wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1 VF610_DDR_PAD_CTRL_1 wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0 VF610_DDR_PAD_CTRL_1 wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B VF610_DDR_PAD_CTRL |