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authorAndrey Smirnov <andrew.smirnov@gmail.com>2018-06-12 11:47:59 -0700
committerSascha Hauer <s.hauer@pengutronix.de>2018-06-13 09:56:21 +0200
commit96b673d03d1321cc3896bfe4b4d0733647ea14f8 (patch)
tree2da053244da0015bbd6ab5ee0188215e5a5a3a75
parent81d38cdce8492274913d0682e5ed7427d1fa3242 (diff)
downloadbarebox-96b673d03d1321cc3896bfe4b4d0733647ea14f8.tar.gz
barebox-96b673d03d1321cc3896bfe4b4d0733647ea14f8.tar.xz
VFxxx: DCD: Remove CR97, CR98 and CR99
There's no point enabling write leveling DQS adjustement, while setting offsets for both slices to zero. This code is effectively a no-op, so drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
index cce4c6de7d..956cc5c58b 100644
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
+++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
@@ -107,9 +107,6 @@ wm 32 DDRMC_CR88 0x00040000
wm 32 DDRMC_CR89 0x00000002
wm 32 DDRMC_CR91 0x00020000
wm 32 DDRMC_CR96 0x00002819
-wm 32 DDRMC_CR97 0x01000000
-wm 32 DDRMC_CR98 0x00000000
-wm 32 DDRMC_CR99 0x00000000
wm 32 DDRMC_CR102 0x00010100
wm 32 DDRMC_CR105 0x00000000
wm 32 DDRMC_CR106 0x00000004