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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2018-09-28 12:42:06 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-10-02 09:23:01 +0200 |
| commit | 45d2ef9e310396d808f9ec7f89c3f3b1772a8630 (patch) | |
| tree | b9f7cc9c3dc4c80eda4159259d73ae53f715e216 | |
| parent | 01c291a03b9262f90ebed4a0068ff47433a0fa6b (diff) | |
| download | barebox-45d2ef9e310396d808f9ec7f89c3f3b1772a8630.tar.gz barebox-45d2ef9e310396d808f9ec7f89c3f3b1772a8630.tar.xz | |
ARM: dts: socfpga: achilles: enable second ethernet port
The Reflex Achilles has 2 ethernet ports. Enable the second one, too.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/dts/socfpga_arria10_achilles.dts | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts index 908e929d9e..176e06df12 100644 --- a/arch/arm/dts/socfpga_arria10_achilles.dts +++ b/arch/arm/dts/socfpga_arria10_achilles.dts @@ -174,6 +174,27 @@ status = "okay"; }; +&gmac2 { + phy-mode = "rgmii"; + phy-addr = <0x3>; + + status = "okay"; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; +}; + &i2c0 { status = "okay"; |