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authorRouven Czerwinski <r.czerwinski@pengutronix.de>2019-04-30 05:15:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-05-06 08:31:16 +0200
commita73850bd76d0d7f29ac1bb6648bd5efc2e418a76 (patch)
tree2b86f6726135191542aa343dc7e6810847f0a711
parentea569a0afd6a2e9a84418cd18ddeaeefaa5eae39 (diff)
downloadbarebox-a73850bd76d0d7f29ac1bb6648bd5efc2e418a76.tar.gz
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ARM: imx: disable IPU QoS setup for correct SoCs
The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL"), but instead it bails at the Solo, not the SX and SL. The original intent was most probably to add an exception for the i.MX6 Solo as well, so everything else is skipped, including the SX, SL and now the UL and ULL. Fix the code to reflect this. On the SX, SL, UL, ULL, this now avoids writes to memory, which isn't described in the datasheets. On the S, it now configures the QoS settings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/imx6.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 01b4274ed3..e898be9ab5 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -117,7 +117,7 @@ static void imx6_setup_ipu_qos(void)
uint32_t val;
if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
- !cpu_mx6_is_mx6dl() && cpu_mx6_is_mx6s())
+ !cpu_mx6_is_mx6dl() && !cpu_mx6_is_mx6s())
return;
val = readl(iomux + IOMUXC_GPR4);