Merge branch 'for-next/stm32'

20 files changed, 827 insertions, 56 deletions

diff --git a/Documentation/boards/stm32mp.rst b/Documentation/boards/stm32mp.rst
index f93ec04eb0..6d97b0d6d4 100644
--- a/Documentation/boards/stm32mp.rst
+++ b/Documentation/boards/stm32mp.rst
@@ -81,3 +81,13 @@ pulled down and BOOT0 and BOOT2 are connected to a 2P DIP switch::
  BOOT2 | O --O |
  BOOT0 | N --O |  <---- DFU on UART and USB OTG
        +-------+
+
+Boot status indicator
+---------------------
+
+The ROM code on the first Cortex-A7 core pulses the PA13 pad.
+An error LED on this pad can be used to indicate boot status:
+
+* **Boot Failure:** LED lights bright
+* **UART/USB Boot:** LED blinks fast
+* **Debug access:** LED lights weak
diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
index f15ae0b4af..9cd5b4ee1f 100644
--- a/arch/arm/boards/stm32mp157c-dk2/board.c
+++ b/arch/arm/boards/stm32mp157c-dk2/board.c
@@ -6,17 +6,6 @@
 #include <mach/stm32.h>
 #include <mach/bbu.h>
 
-static int dk2_mem_init(void)
-{
-	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
-		return 0;
-
-	arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M);
-
-	return 0;
-}
-mem_initcall(dk2_mem_init);
-
 static int dk2_postcore_init(void)
 {
 	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
index 566ace79c9..7261d7a8bc 100644
--- a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
+++ b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
@@ -1,19 +1,26 @@
 // SPDX-License-Identifier: GPL-2.0+
 #include <common.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/stm32.h>
+#include <mach/entry.h>
 #include <debug_ll.h>
 
 extern char __dtb_z_stm32mp157c_dk2_start[];
 
+static void setup_uart(void)
+{
+	/* first stage has set up the UART, so nothing to do here */
+	putc_ll('>');
+}
+
 ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2)
 {
 	void *fdt;
 
-	arm_cpu_lowlevel_init();
+	stm32mp_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
 
 	fdt = __dtb_z_stm32mp157c_dk2_start + get_runtime_offset();
 
-	barebox_arm_entry(STM32_DDR_BASE, SZ_512M, fdt);
+	stm32mp1_barebox_entry(fdt);
 }
diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi
index e9e386a664..6be208f32e 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1.dtsi
@@ -8,10 +8,6 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-	aliases {
-		mmc0 = &sdmmc1;
-	};
-
 	chosen {
 		environment {
 			compatible = "barebox,environment";
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 97c075a020..e416c89856 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -18,11 +18,19 @@
 		gpio9 = &gpioj;
 		gpio10 = &gpiok;
 		gpio25 = &gpioz;
+		mmc0 = &sdmmc1;
 	};
 
 	psci {
 		compatible = "arm,psci-0.2";
 	};
+
+	soc {
+		memory-controller@5a003000 {
+			compatible = "st,stm32mp1-ddr";
+			reg = <0x5a003000 0x1000>;
+		};
+	};
 };
 
 &bsec {
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 6f49528892..8e14b22535 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -1,2 +1,3 @@
 obj-y := init.o
+obj-pbl-y := ddrctrl.o
 obj-$(CONFIG_BOOTM) += stm32image.o
diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c
new file mode 100644
index 0000000000..962d4c0d52
--- /dev/null
+++ b/arch/arm/mach-stm32mp/ddrctrl.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/stm32.h>
+#include <mach/ddr_regs.h>
+#include <mach/entry.h>
+#include <mach/stm32.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+
+#define ADDRMAP1_BANK_B0	GENMASK( 5,  0)
+#define ADDRMAP1_BANK_B1	GENMASK(13,  8)
+#define ADDRMAP1_BANK_B2	GENMASK(21, 16)
+
+#define ADDRMAP2_COL_B2		GENMASK( 3,  0)
+#define ADDRMAP2_COL_B3		GENMASK(11,  8)
+#define ADDRMAP2_COL_B4		GENMASK(19, 16)
+#define ADDRMAP2_COL_B5		GENMASK(27, 24)
+
+#define ADDRMAP3_COL_B6		GENMASK( 3,  0)
+#define ADDRMAP3_COL_B7		GENMASK(12,  8)
+#define ADDRMAP3_COL_B8		GENMASK(20, 16)
+#define ADDRMAP3_COL_B9		GENMASK(28, 24)
+
+#define ADDRMAP4_COL_B10	GENMASK( 4,  0)
+#define ADDRMAP4_COL_B11	GENMASK(12,  8)
+
+#define ADDRMAP5_ROW_B0		GENMASK( 3,  0)
+#define ADDRMAP5_ROW_B1		GENMASK(11,  8)
+#define ADDRMAP5_ROW_B2_10	GENMASK(19, 16)
+#define ADDRMAP5_ROW_B11	GENMASK(27, 24)
+
+#define ADDRMAP6_ROW_B12	GENMASK( 3,  0)
+#define ADDRMAP6_ROW_B13	GENMASK(11,  8)
+#define ADDRMAP6_ROW_B14	GENMASK(19, 16)
+#define ADDRMAP6_ROW_B15	GENMASK(27, 24)
+
+#define ADDRMAP9_ROW_B2		GENMASK( 3,  0)
+#define ADDRMAP9_ROW_B3		GENMASK(11,  8)
+#define ADDRMAP9_ROW_B4		GENMASK(19, 16)
+#define ADDRMAP9_ROW_B5		GENMASK(27, 24)
+
+#define ADDRMAP10_ROW_B6	GENMASK( 3,  0)
+#define ADDRMAP10_ROW_B7	GENMASK(11,  8)
+#define ADDRMAP10_ROW_B8	GENMASK(19, 16)
+#define ADDRMAP10_ROW_B9	GENMASK(27, 24)
+
+#define ADDRMAP11_ROW_B10	GENMASK( 3, 0)
+
+#define LINE_UNUSED(reg, mask) (((reg) & (mask)) == (mask))
+
+enum ddrctrl_buswidth {
+	BUSWIDTH_FULL = 0,
+	BUSWIDTH_HALF = 1,
+	BUSWIDTH_QUARTER = 2
+};
+
+static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
+					     enum ddrctrl_buswidth buswidth)
+{
+	unsigned banks = 3, cols = 12, rows = 16;
+	u32 reg;
+
+	cols += buswidth;
+
+	reg = readl(&d->addrmap1);
+	if (LINE_UNUSED(reg, ADDRMAP1_BANK_B2)) banks--;
+	if (LINE_UNUSED(reg, ADDRMAP1_BANK_B1)) banks--;
+	if (LINE_UNUSED(reg, ADDRMAP1_BANK_B0)) banks--;
+
+	reg = readl(&d->addrmap2);
+	if (LINE_UNUSED(reg, ADDRMAP2_COL_B5)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP2_COL_B4)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP2_COL_B3)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP2_COL_B2)) cols--;
+
+	reg = readl(&d->addrmap3);
+	if (LINE_UNUSED(reg, ADDRMAP3_COL_B9)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP3_COL_B8)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP3_COL_B7)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP3_COL_B6)) cols--;
+
+	reg = readl(&d->addrmap4);
+	if (LINE_UNUSED(reg, ADDRMAP4_COL_B11)) cols--;
+	if (LINE_UNUSED(reg, ADDRMAP4_COL_B10)) cols--;
+
+	reg = readl(&d->addrmap5);
+	if (LINE_UNUSED(reg, ADDRMAP5_ROW_B11)) rows--;
+
+	reg = readl(&d->addrmap6);
+	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B15)) rows--;
+	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B14)) rows--;
+	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B13)) rows--;
+	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B12)) rows--;
+
+	return memory_sdram_size(cols, rows, BIT(banks), 4 / BIT(buswidth));
+}
+
+static inline unsigned ddrctrl_ramsize(void __iomem *base)
+{
+	struct stm32mp1_ddrctl __iomem *ddrctl = base;
+	unsigned buswidth = readl(&ddrctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
+	buswidth >>= DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
+
+	return ddrctrl_addrmap_ramsize(ddrctl, buswidth);
+}
+
+static inline unsigned stm32mp1_ddrctrl_ramsize(void)
+{
+	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE));
+}
+
+void __noreturn stm32mp1_barebox_entry(void *boarddata)
+{
+	barebox_arm_entry(STM32_DDR_BASE, stm32mp1_ddrctrl_ramsize(), boarddata);
+}
+
+
+static int stm32mp1_ddr_probe(struct device_d *dev)
+{
+	struct resource *iores;
+	void __iomem *base;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	base = IOMEM(iores->start);
+
+	arm_add_mem_device("ram0", STM32_DDR_BASE, ddrctrl_ramsize(base));
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id stm32mp1_ddr_dt_ids[] = {
+	{ .compatible = "st,stm32mp1-ddr" },
+	{ /* sentinel */ }
+};
+
+static struct driver_d stm32mp1_ddr_driver = {
+	.name   = "stm32mp1-ddr",
+	.probe  = stm32mp1_ddr_probe,
+	.of_compatible = DRV_OF_COMPAT(stm32mp1_ddr_dt_ids),
+};
+
+static int stm32mp1_ddr_init(void)
+{
+	return platform_driver_register(&stm32mp1_ddr_driver);
+}
+mem_initcall(stm32mp1_ddr_init);
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr_regs.h b/arch/arm/mach-stm32mp/include/mach/ddr_regs.h
new file mode 100644
index 0000000000..7d6a5b8be4
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/ddr_regs.h
@@ -0,0 +1,368 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _STM32MP1_DDR_REGS_H
+#define _STM32MP1_DDR_REGS_H
+
+/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
+struct stm32mp1_ddrctl {
+	u32 mstr ;		/* 0x0 Master*/
+	u32 stat;		/* 0x4 Operating Mode Status*/
+	u8 reserved008[0x10 - 0x8];
+	u32 mrctrl0;		/* 0x10 Control 0.*/
+	u32 mrctrl1;		/* 0x14 Control 1*/
+	u32 mrstat;		/* 0x18 Status*/
+	u32 reserved01c;	/* 0x1c */
+	u32 derateen;		/* 0x20 Temperature Derate Enable*/
+	u32 derateint;		/* 0x24 Temperature Derate Interval*/
+	u8 reserved028[0x30 - 0x28];
+	u32 pwrctl;		/* 0x30 Low Power Control*/
+	u32 pwrtmg;		/* 0x34 Low Power Timing*/
+	u32 hwlpctl;		/* 0x38 Hardware Low Power Control*/
+	u8 reserved03c[0x50 - 0x3C];
+	u32 rfshctl0;		/* 0x50 Refresh Control 0*/
+	u32 reserved054;	/* 0x54 Refresh Control 1*/
+	u32 reserved058;	/* 0x58 Refresh Control 2*/
+	u32 reserved05C;
+	u32 rfshctl3;		/* 0x60 Refresh Control 0*/
+	u32 rfshtmg;		/* 0x64 Refresh Timing*/
+	u8 reserved068[0xc0 - 0x68];
+	u32 crcparctl0;		/* 0xc0 CRC Parity Control0*/
+	u32 reserved0c4;	/* 0xc4 CRC Parity Control1*/
+	u32 reserved0c8;	/* 0xc8 CRC Parity Control2*/
+	u32 crcparstat;		/* 0xcc CRC Parity Status*/
+	u32 init0;		/* 0xd0 SDRAM Initialization 0*/
+	u32 init1;		/* 0xd4 SDRAM Initialization 1*/
+	u32 init2;		/* 0xd8 SDRAM Initialization 2*/
+	u32 init3;		/* 0xdc SDRAM Initialization 3*/
+	u32 init4;		/* 0xe0 SDRAM Initialization 4*/
+	u32 init5;		/* 0xe4 SDRAM Initialization 5*/
+	u32 reserved0e8;
+	u32 reserved0ec;
+	u32 dimmctl;		/* 0xf0 DIMM Control*/
+	u8 reserved0f4[0x100 - 0xf4];
+	u32 dramtmg0;		/* 0x100 SDRAM Timing 0*/
+	u32 dramtmg1;		/* 0x104 SDRAM Timing 1*/
+	u32 dramtmg2;		/* 0x108 SDRAM Timing 2*/
+	u32 dramtmg3;		/* 0x10c SDRAM Timing 3*/
+	u32 dramtmg4;		/* 0x110 SDRAM Timing 4*/
+	u32 dramtmg5;		/* 0x114 SDRAM Timing 5*/
+	u32 dramtmg6;		/* 0x118 SDRAM Timing 6*/
+	u32 dramtmg7;		/* 0x11c SDRAM Timing 7*/
+	u32 dramtmg8;		/* 0x120 SDRAM Timing 8*/
+	u8 reserved124[0x138 - 0x124];
+	u32 dramtmg14;		/* 0x138 SDRAM Timing 14*/
+	u32 dramtmg15;		/* 0x13C SDRAM Timing 15*/
+	u8 reserved140[0x180 - 0x140];
+	u32 zqctl0;		/* 0x180 ZQ Control 0*/
+	u32 zqctl1;		/* 0x184 ZQ Control 1*/
+	u32 zqctl2;		/* 0x188 ZQ Control 2*/
+	u32 zqstat;		/* 0x18c ZQ Status*/
+	u32 dfitmg0;		/* 0x190 DFI Timing 0*/
+	u32 dfitmg1;		/* 0x194 DFI Timing 1*/
+	u32 dfilpcfg0;		/* 0x198 DFI Low Power Configuration 0*/
+	u32 reserved19c;
+	u32 dfiupd0;		/* 0x1a0 DFI Update 0*/
+	u32 dfiupd1;		/* 0x1a4 DFI Update 1*/
+	u32 dfiupd2;		/* 0x1a8 DFI Update 2*/
+	u32 reserved1ac;
+	u32 dfimisc;		/* 0x1b0 DFI Miscellaneous Control*/
+	u8 reserved1b4[0x1bc - 0x1b4];
+	u32 dfistat;		/* 0x1bc DFI Miscellaneous Control*/
+	u8 reserved1c0[0x1c4 - 0x1c0];
+	u32 dfiphymstr;		/* 0x1c4 DFI PHY Master interface*/
+	u8 reserved1c8[0x204 - 0x1c8];
+	u32 addrmap1;		/* 0x204 Address Map 1*/
+	u32 addrmap2;		/* 0x208 Address Map 2*/
+	u32 addrmap3;		/* 0x20c Address Map 3*/
+	u32 addrmap4;		/* 0x210 Address Map 4*/
+	u32 addrmap5;		/* 0x214 Address Map 5*/
+	u32 addrmap6;		/* 0x218 Address Map 6*/
+	u8 reserved21c[0x224 - 0x21c];
+	u32 addrmap9;		/* 0x224 Address Map 9*/
+	u32 addrmap10;		/* 0x228 Address Map 10*/
+	u32 addrmap11;		/* 0x22C Address Map 11*/
+	u8 reserved230[0x240 - 0x230];
+	u32 odtcfg;		/* 0x240 ODT Configuration*/
+	u32 odtmap;		/* 0x244 ODT/Rank Map*/
+	u8 reserved248[0x250 - 0x248];
+	u32 sched;		/* 0x250 Scheduler Control*/
+	u32 sched1;		/* 0x254 Scheduler Control 1*/
+	u32 reserved258;
+	u32 perfhpr1;		/* 0x25c High Priority Read CAM 1*/
+	u32 reserved260;
+	u32 perflpr1;		/* 0x264 Low Priority Read CAM 1*/
+	u32 reserved268;
+	u32 perfwr1;		/* 0x26c Write CAM 1*/
+	u8 reserved27c[0x300 - 0x270];
+	u32 dbg0;		/* 0x300 Debug 0*/
+	u32 dbg1;		/* 0x304 Debug 1*/
+	u32 dbgcam;		/* 0x308 CAM Debug*/
+	u32 dbgcmd;		/* 0x30c Command Debug*/
+	u32 dbgstat;		/* 0x310 Status Debug*/
+	u8 reserved314[0x320 - 0x314];
+	u32 swctl;		/* 0x320 Software Programming Control Enable*/
+	u32 swstat;		/* 0x324 Software Programming Control Status*/
+	u8 reserved328[0x36c - 0x328];
+	u32 poisoncfg;		/* 0x36c AXI Poison Configuration Register*/
+	u32 poisonstat;		/* 0x370 AXI Poison Status Register*/
+	u8 reserved374[0x3fc - 0x374];
+
+	/* Multi Port registers */
+	u32 pstat;		/* 0x3fc Port Status*/
+	u32 pccfg;		/* 0x400 Port Common Configuration*/
+
+	/* PORT 0 */
+	u32 pcfgr_0;		/* 0x404 Configuration Read*/
+	u32 pcfgw_0;		/* 0x408 Configuration Write*/
+	u8 reserved40c[0x490 - 0x40c];
+	u32 pctrl_0;		/* 0x490 Port Control Register */
+	u32 pcfgqos0_0;		/* 0x494 Read QoS Configuration 0*/
+	u32 pcfgqos1_0;		/* 0x498 Read QoS Configuration 1*/
+	u32 pcfgwqos0_0;	/* 0x49c Write QoS Configuration 0*/
+	u32 pcfgwqos1_0;	/* 0x4a0 Write QoS Configuration 1*/
+	u8 reserved4a4[0x4b4 - 0x4a4];
+
+	/* PORT 1 */
+	u32 pcfgr_1;		/* 0x4b4 Configuration Read*/
+	u32 pcfgw_1;		/* 0x4b8 Configuration Write*/
+	u8 reserved4bc[0x540 - 0x4bc];
+	u32 pctrl_1;		/* 0x540 Port 2 Control Register */
+	u32 pcfgqos0_1;		/* 0x544 Read QoS Configuration 0*/
+	u32 pcfgqos1_1;		/* 0x548 Read QoS Configuration 1*/
+	u32 pcfgwqos0_1;	/* 0x54c Write QoS Configuration 0*/
+	u32 pcfgwqos1_1;	/* 0x550 Write QoS Configuration 1*/
+};
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp1_ddrphy {
+	u32 ridr;		/* 0x00 R Revision Identification*/
+	u32 pir;		/* 0x04 R/W PHY Initialization*/
+	u32 pgcr;		/* 0x08 R/W PHY General Configuration*/
+	u32 pgsr;		/* 0x0C PHY General Status*/
+	u32 dllgcr;		/* 0x10 R/W DLL General Control*/
+	u32 acdllcr;		/* 0x14 R/W AC DLL Control*/
+	u32 ptr0;		/* 0x18 R/W PHY Timing 0*/
+	u32 ptr1;		/* 0x1C R/W PHY Timing 1*/
+	u32 ptr2;		/* 0x20 R/W PHY Timing 2*/
+	u32 aciocr;		/* 0x24 AC I/O Configuration*/
+	u32 dxccr;		/* 0x28 DATX8 Common Configuration*/
+	u32 dsgcr;		/* 0x2C DDR System General Configuration*/
+	u32 dcr;		/* 0x30 DRAM Configuration*/
+	u32 dtpr0;		/* 0x34 DRAM Timing Parameters0*/
+	u32 dtpr1;		/* 0x38 DRAM Timing Parameters1*/
+	u32 dtpr2;		/* 0x3C DRAM Timing Parameters2*/
+	u32 mr0;		/* 0x40 Mode 0*/
+	u32 mr1;		/* 0x44 Mode 1*/
+	u32 mr2;		/* 0x48 Mode 2*/
+	u32 mr3;		/* 0x4C Mode 3*/
+	u32 odtcr;		/* 0x50 ODT Configuration*/
+	u32 dtar;		/* 0x54 data training address*/
+	u32 dtdr0;		/* 0x58 */
+	u32 dtdr1;		/* 0x5c */
+	u8 res1[0x0c0 - 0x060];	/* 0x60 */
+	u32 dcuar;		/* 0xc0 Address*/
+	u32 dcudr;		/* 0xc4 DCU Data*/
+	u32 dcurr;		/* 0xc8 DCU Run*/
+	u32 dculr;		/* 0xcc DCU Loop*/
+	u32 dcugcr;		/* 0xd0 DCU General Configuration*/
+	u32 dcutpr;		/* 0xd4 DCU Timing Parameters */
+	u32 dcusr0;		/* 0xd8 DCU Status 0*/
+	u32 dcusr1;		/* 0xdc DCU Status 1*/
+	u8 res2[0x100 - 0xe0];	/* 0xe0 */
+	u32 bistrr;		/* 0x100 BIST Run*/
+	u32 bistmskr0;		/* 0x104 BIST Mask 0*/
+	u32 bistmskr1;		/* 0x108 BIST Mask 0*/
+	u32 bistwcr;		/* 0x10c BIST Word Count*/
+	u32 bistlsr;		/* 0x110 BIST LFSR Seed*/
+	u32 bistar0;		/* 0x114 BIST Address 0*/
+	u32 bistar1;		/* 0x118 BIST Address 1*/
+	u32 bistar2;		/* 0x11c BIST Address 2*/
+	u32 bistupdr;		/* 0x120 BIST User Data Pattern*/
+	u32 bistgsr;		/* 0x124 BIST General Status*/
+	u32 bistwer;		/* 0x128 BIST Word Error*/
+	u32 bistber0;		/* 0x12c BIST Bit Error 0*/
+	u32 bistber1;		/* 0x130 BIST Bit Error 1*/
+	u32 bistber2;		/* 0x134 BIST Bit Error 2*/
+	u32 bistwcsr;		/* 0x138 BIST Word Count Status*/
+	u32 bistfwr0;		/* 0x13c BIST Fail Word 0*/
+	u32 bistfwr1;		/* 0x140 BIST Fail Word 1*/
+	u8 res3[0x178 - 0x144];	/* 0x144 */
+	u32 gpr0;		/* 0x178 General Purpose 0 (GPR0)*/
+	u32 gpr1;		/* 0x17C General Purpose 1 (GPR1)*/
+	u32 zq0cr0;		/* 0x180 zq 0 control 0 */
+	u32 zq0cr1;		/* 0x184 zq 0 control 1 */
+	u32 zq0sr0;		/* 0x188 zq 0 status 0 */
+	u32 zq0sr1;		/* 0x18C zq 0 status 1 */
+	u8 res4[0x1C0 - 0x190];	/* 0x190 */
+	u32 dx0gcr;		/* 0x1c0 Byte lane 0 General Configuration*/
+	u32 dx0gsr0;		/* 0x1c4 Byte lane 0 General Status 0*/
+	u32 dx0gsr1;		/* 0x1c8 Byte lane 0 General Status 1*/
+	u32 dx0dllcr;		/* 0x1cc Byte lane 0 DLL Control*/
+	u32 dx0dqtr;		/* 0x1d0 Byte lane 0 DQ Timing*/
+	u32 dx0dqstr;		/* 0x1d4 Byte lane 0 DQS Timing*/
+	u8 res5[0x200 - 0x1d8];	/* 0x1d8 */
+	u32 dx1gcr;		/* 0x200 Byte lane 1 General Configuration*/
+	u32 dx1gsr0;		/* 0x204 Byte lane 1 General Status 0*/
+	u32 dx1gsr1;		/* 0x208 Byte lane 1 General Status 1*/
+	u32 dx1dllcr;		/* 0x20c Byte lane 1 DLL Control*/
+	u32 dx1dqtr;		/* 0x210 Byte lane 1 DQ Timing*/
+	u32 dx1dqstr;		/* 0x214 Byte lane 1 QS Timing*/
+	u8 res6[0x240 - 0x218];	/* 0x218 */
+	u32 dx2gcr;		/* 0x240 Byte lane 2 General Configuration*/
+	u32 dx2gsr0;		/* 0x244 Byte lane 2 General Status 0*/
+	u32 dx2gsr1;		/* 0x248 Byte lane 2 General Status 1*/
+	u32 dx2dllcr;		/* 0x24c Byte lane 2 DLL Control*/
+	u32 dx2dqtr;		/* 0x250 Byte lane 2 DQ Timing*/
+	u32 dx2dqstr;		/* 0x254 Byte lane 2 QS Timing*/
+	u8 res7[0x280 - 0x258];	/* 0x258 */
+	u32 dx3gcr;		/* 0x280 Byte lane 3 General Configuration*/
+	u32 dx3gsr0;		/* 0x284 Byte lane 3 General Status 0*/
+	u32 dx3gsr1;		/* 0x288 Byte lane 3 General Status 1*/
+	u32 dx3dllcr;		/* 0x28c Byte lane 3 DLL Control*/
+	u32 dx3dqtr;		/* 0x290 Byte lane 3 DQ Timing*/
+	u32 dx3dqstr;		/* 0x294 Byte lane 3 QS Timing*/
+};
+
+#define DXN(phy, offset, byte)	((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
+#define DXNGCR(phy, byte)	DXN(phy, 0x1c0, byte)
+#define DXNDLLCR(phy, byte)	DXN(phy, 0x1cc, byte)
+#define DXNDQTR(phy, byte)	DXN(phy, 0x1d0, byte)
+#define DXNDQSTR(phy, byte)	DXN(phy, 0x1d4, byte)
+
+/* DDRCTRL REGISTERS */
+#define DDRCTRL_MSTR_DDR3			BIT(0)
+#define DDRCTRL_MSTR_LPDDR2			BIT(2)
+#define DDRCTRL_MSTR_LPDDR3			BIT(3)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT	12
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK	GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL	(0 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	(1 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER	(2 << 12)
+#define DDRCTRL_MSTR_DLL_OFF_MODE		BIT(15)
+
+#define DDRCTRL_STAT_OPERATING_MODE_MASK	GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL	1
+#define DDRCTRL_STAT_OPERATING_MODE_SR		3
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK		GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR		(3 << 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_SR		(2 << 4)
+
+#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE		0
+/* only one rank supported */
+#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT		4
+#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
+		(0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT		12
+#define DDRCTRL_MRCTRL0_MR_ADDR_MASK		GENMASK(15, 12)
+#define DDRCTRL_MRCTRL0_MR_WR			BIT(31)
+
+#define DDRCTRL_MRSTAT_MR_WR_BUSY		BIT(0)
+
+#define DDRCTRL_PWRCTL_POWERDOWN_EN		BIT(1)
+#define DDRCTRL_PWRCTL_SELFREF_SW		BIT(5)
+
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH	BIT(0)
+
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK	GENMASK(27, 16)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT	16
+
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK	(0xC0000000)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL	(BIT(30))
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN	BIT(0)
+
+#define DDRCTRL_DBG1_DIS_HIF			BIT(1)
+
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY	BIT(29)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY	BIT(28)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY		BIT(26)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH		GENMASK(12, 8)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH		GENMASK(4, 0)
+#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
+		(DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
+		 DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
+		(DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+		 DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
+		 DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
+
+#define DDRCTRL_DBGCMD_RANK0_REFRESH		BIT(0)
+
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY	BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE			BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK		BIT(0)
+
+#define DDRCTRL_PCTRL_N_PORT_EN			BIT(0)
+
+/* DDRPHYC registers */
+#define DDRPHYC_PIR_INIT			BIT(0)
+#define DDRPHYC_PIR_DLLSRST			BIT(1)
+#define DDRPHYC_PIR_DLLLOCK			BIT(2)
+#define DDRPHYC_PIR_ZCAL			BIT(3)
+#define DDRPHYC_PIR_ITMSRST			BIT(4)
+#define DDRPHYC_PIR_DRAMRST			BIT(5)
+#define DDRPHYC_PIR_DRAMINIT			BIT(6)
+#define DDRPHYC_PIR_QSTRN			BIT(7)
+#define DDRPHYC_PIR_ICPC			BIT(16)
+#define DDRPHYC_PIR_ZCALBYP			BIT(30)
+#define DDRPHYC_PIR_INITSTEPS_MASK		GENMASK(31, 7)
+
+#define DDRPHYC_PGCR_DFTCMP			BIT(2)
+#define DDRPHYC_PGCR_PDDISDX			BIT(24)
+#define DDRPHYC_PGCR_RFSHDT_MASK		GENMASK(28, 25)
+
+#define DDRPHYC_PGSR_IDONE			BIT(0)
+#define DDRPHYC_PGSR_DTERR			BIT(5)
+#define DDRPHYC_PGSR_DTIERR			BIT(6)
+#define DDRPHYC_PGSR_DFTERR			BIT(7)
+#define DDRPHYC_PGSR_RVERR			BIT(8)
+#define DDRPHYC_PGSR_RVEIRR			BIT(9)
+
+#define DDRPHYC_DLLGCR_BPS200			BIT(23)
+
+#define DDRPHYC_ACDLLCR_DLLDIS			BIT(31)
+
+#define DDRPHYC_ZQ0CRN_ZDATA_MASK		GENMASK(27, 0)
+#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT		0
+#define DDRPHYC_ZQ0CRN_ZDEN			BIT(28)
+
+#define DDRPHYC_DXNGCR_DXEN			BIT(0)
+
+#define DDRPHYC_DXNDLLCR_DLLSRST		BIT(30)
+#define DDRPHYC_DXNDLLCR_DLLDIS			BIT(31)
+#define DDRPHYC_DXNDLLCR_SDPHASE_MASK		GENMASK(17, 14)
+#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT		14
+
+#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)	(4 * (bit))
+#define DDRPHYC_DXNDQTR_DQDLY_MASK		GENMASK(3, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK		GENMASK(1, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK		GENMASK(3, 2)
+
+#define DDRPHYC_DXNDQSTR_DQSDLY_MASK		GENMASK(22, 20)
+#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT		20
+#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK		GENMASK(25, 23)
+#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT		23
+#define DDRPHYC_DXNDQSTR_R0DGSL_MASK		GENMASK(2, 0)
+#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT		0
+#define DDRPHYC_DXNDQSTR_R0DGPS_MASK		GENMASK(13, 12)
+#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT		12
+
+#define DDRPHYC_BISTRR_BDXSEL_MASK		GENMASK(22, 19)
+#define DDRPHYC_BISTRR_BDXSEL_SHIFT		19
+
+#define DDRPHYC_BISTGSR_BDDONE			BIT(0)
+#define DDRPHYC_BISTGSR_BDXERR			BIT(2)
+
+#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT		16
+
+/* PWR registers */
+#define PWR_CR3					0x00C
+#define PWR_CR3_DDRSRDIS			BIT(11)
+#define PWR_CR3_DDRRETEN			BIT(12)
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/entry.h b/arch/arm/mach-stm32mp/include/mach/entry.h
new file mode 100644
index 0000000000..92e15b5cf4
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/entry.h
@@ -0,0 +1,19 @@
+#ifndef _STM32MP_MACH_ENTRY_H_
+#define _STM32MP_MACH_ENTRY_H_
+
+#include <linux/kernel.h>
+#include <asm/barebox-arm.h>
+
+static __always_inline void stm32mp_cpu_lowlevel_init(void)
+{
+	unsigned long stack_top;
+	arm_cpu_lowlevel_init();
+
+	stack_top = (unsigned long)__image_end + get_runtime_offset() + 64;
+	stack_top = ALIGN(stack_top, 16);
+	arm_setup_stack(stack_top);
+}
+
+void __noreturn stm32mp1_barebox_entry(void *boarddata);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index f9bdb788b9..adb898fa26 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -12,6 +12,8 @@
 #define STM32_RCC_BASE			0x50000000
 #define STM32_PWR_BASE			0x50001000
 #define STM32_DBGMCU_BASE		0x50081000
+#define STM32_DDRCTL_BASE		0x5A003000
+#define STM32_DDRPHY_BASE		0x5A004000
 #define STM32_BSEC_BASE			0x5C005000
 #define STM32_TZC_BASE			0x5C006000
 #define STM32_ETZPC_BASE		0x5C007000
diff --git a/drivers/i2c/busses/i2c-stm32.c b/drivers/i2c/busses/i2c-stm32.c
index 6af55fb3ff..9f34760e3f 100644
--- a/drivers/i2c/busses/i2c-stm32.c
+++ b/drivers/i2c/busses/i2c-stm32.c
@@ -785,7 +785,6 @@ static int __init stm32_i2c_probe(struct device_d *dev)
 	struct resource *iores;
 	struct stm32_i2c *stm32_i2c;
 	struct i2c_platform_data *pdata;
-	struct reset_control *rst;
 	const struct stm32_i2c_setup *setup;
 	struct i2c_timings *timings;
 	int ret;
@@ -799,13 +798,9 @@ static int __init stm32_i2c_probe(struct device_d *dev)
 		return PTR_ERR(stm32_i2c->clk);
 	clk_enable(stm32_i2c->clk);
 
-	rst = reset_control_get(dev, NULL);
-	if (IS_ERR(rst))
-		return PTR_ERR(rst);
-
-	reset_control_assert(rst);
-	udelay(2);
-	reset_control_deassert(rst);
+	ret = device_reset_us(dev, 2);
+	if (ret)
+		return ret;
 
 	ret = dev_get_drvdata(dev, (const void **)&setup);
 	if (ret)
diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index eae6fe3a4e..ab13ded0ec 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -12,8 +12,7 @@
 #include <of.h>
 #include <regmap.h>
 #include <xfuncs.h>
-
-#define VERSION_SR		0x6
+#include <linux/mfd/stpmic1.h>
 
 struct stpmic1 {
 	struct device_d		*dev;
diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c
index 8235d468d1..d772d0b7af 100644
--- a/drivers/nvmem/bsec.c
+++ b/drivers/nvmem/bsec.c
@@ -57,7 +57,7 @@ static int bsec_smc(struct bsec_priv *priv, u8 op, enum bsec_field field,
 	return -ENXIO;
 }
 
-static int st32_bsec_read_shadow(void *ctx, unsigned reg, unsigned *val)
+static int stm32_bsec_read_shadow(void *ctx, unsigned reg, unsigned *val)
 {
 	return bsec_smc(ctx, BSEC_SMC_READ_SHADOW, reg, 0, val);
 }
@@ -69,7 +69,7 @@ static int stm32_bsec_reg_write_shadow(void *ctx, unsigned reg, unsigned val)
 
 static struct regmap_bus stm32_bsec_regmap_bus = {
 	.reg_write = stm32_bsec_reg_write_shadow,
-	.reg_read = st32_bsec_read_shadow,
+	.reg_read = stm32_bsec_read_shadow,
 };
 
 static int stm32_bsec_write(struct device_d *dev, int offset,
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 8139b6442c..a193fadb69 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -21,6 +21,16 @@ config IMX_REMOTEPROC
 
 	  It's safe to say N here.
 
+config STM32_REMOTEPROC
+	tristate "STM32 remoteproc support"
+	depends on ARCH_STM32MP
+	select MFD_SYSCON
+	help
+	  Say y here to support STM32 MCU processors via the
+	  remote processor framework.
+
+	  It's safe to say N here.
+
 endif # REMOTEPROC
 
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 1072969229..43658df5c6 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -5,3 +5,4 @@
 
 obj-$(CONFIG_REMOTEPROC)		+= remoteproc_core.o remoteproc_elf_loader.o
 obj-$(CONFIG_IMX_REMOTEPROC)		+= imx_rproc.o
+obj-$(CONFIG_STM32_REMOTEPROC)		+= stm32_rproc.o
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 7cac47e06c..8a28c1bafc 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -107,14 +107,36 @@ static int rproc_firmware_finish(struct firmware_handler *fh)
 	return ret;
 }
 
+static int rproc_register_dev(struct rproc *rproc, const char *alias)
+{
+	if (alias) {
+		rproc->dev.id = DEVICE_ID_SINGLE;
+		dev_set_name(&rproc->dev, alias);
+	} else {
+		rproc->dev.id = DEVICE_ID_DYNAMIC;
+		dev_set_name(&rproc->dev, "remoteproc");
+	}
+
+	return register_device(&rproc->dev);
+}
+
 int rproc_add(struct rproc *rproc)
 {
 	struct device_d *dev = &rproc->dev;
 	struct firmware_handler *fh;
+	const char *alias = NULL;
 	int ret;
 
+	if (dev->device_node)
+		alias = of_alias_get(dev->device_node);
+
+	ret = rproc_register_dev(rproc, alias);
+	if (ret)
+		return ret;
+
 	fh = &rproc->fh;
-	fh->id = xstrdup(rproc->name);
+	fh->id = xstrdup(dev_name(dev));
+	fh->model = xstrdup(rproc->name);
 	fh->open = rproc_firmware_start;
 	fh->write = rproc_firmware_write_buf;
 	fh->close = rproc_firmware_finish;
@@ -153,11 +175,6 @@ struct rproc *rproc_alloc(struct device_d *dev, const char *name,
 	rproc->dev.parent = dev;
 	rproc->dev.priv = rproc;
 
-	/* Assign a unique device index and name */
-	rproc->index = 1;
-
-	dev_set_name(&rproc->dev, "remoteproc%d", rproc->index);
-
 	/* Default to ELF loader if no load function is specified */
 	if (!rproc->ops->load)
 		rproc->ops->load = rproc_elf_load_segments;
diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c
new file mode 100644
index 0000000000..bfd4d59768
--- /dev/null
+++ b/drivers/remoteproc/stm32_rproc.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <io.h>
+#include <mach/smc.h>
+#include <mfd/syscon.h>
+#include <of_address.h>
+#include <regmap.h>
+#include <linux/remoteproc.h>
+#include <linux/reset.h>
+
+#include "remoteproc_internal.h"
+
+#define HOLD_BOOT		0
+#define RELEASE_BOOT		1
+
+struct stm32_syscon {
+	struct regmap *map;
+	u32 reg;
+	u32 mask;
+};
+
+struct stm32_rproc {
+	struct reset_control *rst;
+	struct stm32_syscon hold_boot;
+	bool secured_soc;
+};
+
+static void *stm32_rproc_da_to_va(struct rproc *rproc, u64 da, int len)
+{
+	__be32 in_addr = cpu_to_be32(da);
+	struct device_d *dev = &rproc->dev;
+	u64 paddr;
+
+	paddr = of_translate_dma_address(dev->parent->device_node, &in_addr);
+	if (paddr == OF_BAD_ADDR)
+		return NULL;
+
+	return phys_to_virt(paddr);
+}
+
+static int stm32_rproc_set_hold_boot(struct rproc *rproc, bool hold)
+{
+	struct stm32_rproc *ddata = rproc->priv;
+	struct stm32_syscon *hold_boot = &ddata->hold_boot;
+	struct arm_smccc_res smc_res;
+	int val, err;
+
+	val = hold ? HOLD_BOOT : RELEASE_BOOT;
+
+	if (IS_ENABLED(CONFIG_ARM_SMCC) && ddata->secured_soc) {
+		arm_smccc_smc(STM32_SMC_RCC, STM32_SMC_REG_WRITE,
+			      hold_boot->reg, val, 0, 0, 0, 0, &smc_res);
+		err = smc_res.a0;
+	} else {
+		err = regmap_update_bits(hold_boot->map, hold_boot->reg,
+					 hold_boot->mask, val);
+	}
+
+	if (err)
+		dev_err(&rproc->dev, "failed to set hold boot\n");
+
+	return err;
+}
+
+static int stm32_rproc_start(struct rproc *rproc)
+{
+	int err;
+
+	err = stm32_rproc_set_hold_boot(rproc, false);
+	if (err)
+		return err;
+
+	return stm32_rproc_set_hold_boot(rproc, true);
+}
+
+static int stm32_rproc_stop(struct rproc *rproc)
+{
+	struct stm32_rproc *ddata = rproc->priv;
+	int err;
+
+	err = stm32_rproc_set_hold_boot(rproc, true);
+	if (err)
+		return err;
+
+	err = reset_control_assert(ddata->rst);
+	if (err) {
+		dev_err(&rproc->dev, "failed to assert the reset\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static struct rproc_ops st_rproc_ops = {
+	.start		= stm32_rproc_start,
+	.stop		= stm32_rproc_stop,
+	.da_to_va	= stm32_rproc_da_to_va,
+};
+
+static int stm32_rproc_get_syscon(struct device_node *np, const char *prop,
+				  struct stm32_syscon *syscon)
+{
+	int err = 0;
+
+	syscon->map = syscon_regmap_lookup_by_phandle(np, prop);
+	if (IS_ERR(syscon->map)) {
+		err = PTR_ERR(syscon->map);
+		syscon->map = NULL;
+		goto out;
+	}
+
+	err = of_property_read_u32_index(np, prop, 1, &syscon->reg);
+	if (err)
+		goto out;
+
+	err = of_property_read_u32_index(np, prop, 2, &syscon->mask);
+
+out:
+	return err;
+}
+
+static int stm32_rproc_parse_dt(struct device_d *dev, struct stm32_rproc *ddata)
+{
+	struct device_node *np = dev->device_node;
+	struct stm32_syscon tz;
+	unsigned int tzen;
+	int err;
+
+	ddata->rst = reset_control_get(dev, NULL);
+	if (IS_ERR(ddata->rst)) {
+		dev_err(dev, "failed to get mcu reset\n");
+		return PTR_ERR(ddata->rst);
+	}
+
+	/*
+	 * if platform is secured the hold boot bit must be written by
+	 * smc call and read normally.
+	 * if not secure the hold boot bit could be read/write normally
+	 */
+	err = stm32_rproc_get_syscon(np, "st,syscfg-tz", &tz);
+	if (err) {
+		dev_err(dev, "failed to get tz syscfg\n");
+		return err;
+	}
+
+	err = regmap_read(tz.map, tz.reg, &tzen);
+	if (err) {
+		dev_err(dev, "failed to read tzen\n");
+		return err;
+	}
+	ddata->secured_soc = tzen & tz.mask;
+
+	err = stm32_rproc_get_syscon(np, "st,syscfg-holdboot",
+				     &ddata->hold_boot);
+	if (err) {
+		dev_err(dev, "failed to get hold boot\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int stm32_rproc_probe(struct device_d *dev)
+{
+	struct rproc *rproc;
+	int ret;
+
+	rproc = rproc_alloc(dev, dev_name(dev), &st_rproc_ops,
+			    sizeof(struct stm32_rproc));
+	if (!rproc)
+		return -ENOMEM;
+
+	ret = stm32_rproc_parse_dt(dev, rproc->priv);
+	if (ret)
+		return ret;
+
+	return rproc_add(rproc);
+}
+
+static const struct of_device_id stm32_rproc_of_match[] = {
+	{ .compatible = "st,stm32mp1-m4" },
+	{ /* sentinel */ },
+};
+
+static struct driver_d stm32_rproc_driver = {
+	.name = "stm32-rproc",
+	.probe = stm32_rproc_probe,
+	.of_compatible = DRV_OF_COMPAT(stm32_rproc_of_match),
+};
+device_platform_driver(stm32_rproc_driver);
diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
index 4d252e558c..808d7c8372 100644
--- a/drivers/watchdog/stm32_iwdg.c
+++ b/drivers/watchdog/stm32_iwdg.c
@@ -132,7 +132,7 @@ static int stm32_iwdg_set_timeout(struct watchdog *wdd, unsigned int timeout)
 	int ret;
 
 	if (!timeout)
-		return -EINVAL; /* can't disable */
+		return -ENOSYS; /* can't disable */
 
 	if (timeout > wdd->timeout_max)
 		return -EINVAL;
diff --git a/drivers/watchdog/stpmic1_wdt.c b/drivers/watchdog/stpmic1_wdt.c
index 9b7a586387..40273ffc4c 100644
--- a/drivers/watchdog/stpmic1_wdt.c
+++ b/drivers/watchdog/stpmic1_wdt.c
@@ -14,22 +14,15 @@
 #include <restart.h>
 #include <reset_source.h>
 
-#define RESTART_SR		0x05
-#define MAIN_CR			0x10
-#define WCHDG_CR		0x1B
-#define WCHDG_TIMER_CR		0x1C
+#include <linux/mfd/stpmic1.h>
 
-/* Restart Status Register (RESTART_SR) */
+/* Restart Status Register (RREQ_STATE_SR) */
 #define R_RST			BIT(0)
 #define R_SWOFF			BIT(1)
 #define R_WDG			BIT(2)
 #define R_PKEYLKP		BIT(3)
 #define R_VINOK_FA		BIT(4)
 
-/* Main PMIC Control Register (MAIN_CR) */
-#define SWOFF                   BIT(0)
-#define RREQ_EN                 BIT(1)
-
 /* Watchdog Control Register (WCHDG_CR) */
 #define WDT_START		BIT(0)
 #define WDT_PING		BIT(1)
@@ -106,8 +99,9 @@ static void __noreturn stpmic1_restart_handler(struct restart_handler *rst)
 {
 	struct stpmic1_wdt *wdt = container_of(rst, struct stpmic1_wdt, restart);
 
-	regmap_write_bits(wdt->regmap, MAIN_CR,
-			  SWOFF | RREQ_EN, SWOFF | RREQ_EN);
+	regmap_write_bits(wdt->regmap, SWOFF_PWRCTRL_CR,
+			  SOFTWARE_SWITCH_OFF_ENABLED | RESTART_REQUEST_ENABLED,
+			  SOFTWARE_SWITCH_OFF_ENABLED | RESTART_REQUEST_ENABLED);
 
 	mdelay(1000);
 	hang();
@@ -119,8 +113,9 @@ static void __noreturn stpmic1_poweroff(struct poweroff_handler *handler)
 
 	shutdown_barebox();
 
-	regmap_write_bits(wdt->regmap, MAIN_CR,
-			  SWOFF | RREQ_EN, SWOFF);
+	regmap_write_bits(wdt->regmap, SWOFF_PWRCTRL_CR,
+			  SOFTWARE_SWITCH_OFF_ENABLED | RESTART_REQUEST_ENABLED,
+			  SOFTWARE_SWITCH_OFF_ENABLED);
 
 	mdelay(1000);
 	hang();
@@ -142,7 +137,7 @@ static int stpmic1_set_reset_reason(struct regmap *map)
 	int ret;
 	int i, instance = 0;
 
-	ret = regmap_read(map, RESTART_SR, &reg);
+	ret = regmap_read(map, RREQ_STATE_SR, &reg);
 	if (ret)
 		return ret;
 
@@ -156,7 +151,7 @@ static int stpmic1_set_reset_reason(struct regmap *map)
 
 	reset_source_set_prinst(type, 400, instance);
 
-	pr_info("STPMIC1 reset reason %s (RESTART_SR: 0x%08x)\n",
+	pr_info("STPMIC1 reset reason %s (RREQ_STATE_SR: 0x%08x)\n",
 		reset_source_name(), reg);
 
 	return 0;
@@ -180,7 +175,8 @@ static int stpmic1_wdt_probe(struct device_d *dev)
 	wdd->timeout_max = PMIC_WDT_MAX_TIMEOUT;
 
 	/* have the watchdog reset, not power-off the system */
-	regmap_write_bits(wdt->regmap, MAIN_CR, RREQ_EN, RREQ_EN);
+	regmap_write_bits(wdt->regmap, SWOFF_PWRCTRL_CR,
+			  RESTART_REQUEST_ENABLED, RESTART_REQUEST_ENABLED);
 
 	ret = watchdog_register(wdd);
 	if (ret) {
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index feee9ee4ee..c6264d1c0a 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -38,7 +38,6 @@ struct rproc {
 	void *priv;
 	struct rproc_ops *ops;
 	struct device_d dev;
-	int index;
 
 	void *fw_buf;
 	size_t fw_buf_ofs;