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authorLucas Stach <dev@lynxeye.de>2019-11-09 15:28:34 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-11 09:15:55 +0100
commit7984f6549f300ffd6cff0bae6794b8008cdbbbd0 (patch)
treef74deb8f906f20643d2addd5ae45f808d1f057d5
parent70b00bda144d2bf0dfbf55cef62d70f9e5e4fb69 (diff)
downloadbarebox-7984f6549f300ffd6cff0bae6794b8008cdbbbd0.tar.gz
barebox-7984f6549f300ffd6cff0bae6794b8008cdbbbd0.tar.xz
clk: zynq: remove clkdevs
They aren't needed anymore, as all the Zynq devices now use a DT based clock lookup. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/zynq/clkc.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index f30aa8238a..30ca5a60fa 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -476,15 +476,6 @@ static int zynq_clock_probe(struct device_d *dev)
clks[smc_aper] = clk_gate("smc_aper", "cpu_1x",
clk_base + 0x2C, 24, 0, 0);
- clk_register_clkdev(clks[cpu_3or2x], NULL, "arm_smp_twd");
- clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
- clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
- clk_register_clkdev(clks[gem0], NULL, "macb0");
- clk_register_clkdev(clks[gem1], NULL, "macb1");
-
- clkdev_add_physbase(clks[cpu_3or2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
-
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,