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authorSascha Hauer <s.hauer@pengutronix.de>2020-04-16 18:40:52 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-04-16 18:40:52 +0200
commit4b919832ad3cd33fa6fbd2a1eefd85b99cf42b31 (patch)
treee95494895f3a046d1896356e06eefabe0cf5a5f5
parent711bc44d6119d62009c25658ecdfca3e55d32df0 (diff)
parentfd3728a4a94e1eac7c690cf82c0c6cb9fdaf3b76 (diff)
downloadbarebox-4b919832ad3cd33fa6fbd2a1eefd85b99cf42b31.tar.gz
barebox-4b919832ad3cd33fa6fbd2a1eefd85b99cf42b31.tar.xz
Merge branch 'for-next/zynq'
-rw-r--r--arch/arm/boards/avnet-zedboard/lowlevel.c25
-rw-r--r--drivers/mci/Kconfig1
-rw-r--r--drivers/mci/arasan-sdhci.c2
-rw-r--r--scripts/zynq_mkimage.c9
4 files changed, 31 insertions, 6 deletions
diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c
index 912eb11fda..eb85df507a 100644
--- a/arch/arm/boards/avnet-zedboard/lowlevel.c
+++ b/arch/arm/boards/avnet-zedboard/lowlevel.c
@@ -258,7 +258,7 @@ static void avnet_zedboard_ps7_init(void)
/* GEM0 */
writel(0x00000001, 0xf8000138);
- writel(0x00500801, 0xf8000140);
+ writel(0x00100801, 0xf8000140);
writel(0x00000302, 0xf8000740);
writel(0x00000302, 0xf8000744);
writel(0x00000302, 0xf8000748);
@@ -271,11 +271,20 @@ static void avnet_zedboard_ps7_init(void)
writel(0x00001303, 0xf8000764);
writel(0x00001303, 0xf8000768);
writel(0x00001303, 0xf800076C);
- writel(0x00001280, 0xf80007D0);
- writel(0x00001280, 0xf80007D4);
+ writel(0x00000280, 0xf80007D0);
+ writel(0x00000280, 0xf80007D4);
writel(0x00000001, 0xf8000B00);
+ /* FPGA Clock Control */
+ writel(0x00101400, 0xf8000170);
+ writel(0x00101400, 0xf8000180);
+ writel(0x00101400, 0xf8000190);
+ writel(0x00101400, 0xf80001a0);
+
+ /* PCAP Clock Control */
+ writel(0x00000501, 0xf8000168);
+
/* lock up. secure, secure */
writel(0x0000767B, ZYNQ_SLCR_LOCK);
}
@@ -297,6 +306,16 @@ ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2)
void *fdt = __dtb_zynq_zed_start + get_runtime_offset();
+ /* MIO_07 in GPIO Mode 3.3V VIO, can be uncomented because it is the default value */
+ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK);
+ writel(0x00000600, 0xF800071C );
+ writel(0x0000767B, ZYNQ_SLCR_LOCK);
+
+ /* turns on the LED MIO_07 */
+ writel((1<<7), 0xe000a204 ); // Direction
+ writel((1<<7), 0xe000a208 ); // Output enable
+ writel((1<<7), 0xe000a040 ); // DATA Register
+
arm_cpu_lowlevel_init();
zynq_cpu_lowlevel_init();
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 80b3a26002..9f56bed3ab 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -141,6 +141,7 @@ config MCI_TEGRA
config MCI_ARASAN
bool "Arasan SDHCI Controller"
+ select MCI_SDHCI
help
Enable this to support SD and MMC card read/write on systems with
the Arasan SD3.0 / SDIO3.0 / eMMC4.51 host controller.
diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c
index b43a4f8ddf..520bf30ff9 100644
--- a/drivers/mci/arasan-sdhci.c
+++ b/drivers/mci/arasan-sdhci.c
@@ -278,7 +278,7 @@ static int arasan_sdhci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
mask = SDHCI_INT_CMD_COMPLETE;
if (data)
- mask |= SDHCI_INT_XFER_COMPLETE;
+ mask |= SDHCI_INT_DATA_AVAIL;
sdhci_set_cmd_xfer_mode(&host->sdhci, cmd, data, false, &command, &xfer);
diff --git a/scripts/zynq_mkimage.c b/scripts/zynq_mkimage.c
index 0a1c069472..a211b79c28 100644
--- a/scripts/zynq_mkimage.c
+++ b/scripts/zynq_mkimage.c
@@ -241,7 +241,7 @@ int main(int argc, char *argv[])
char *buf;
const char *infile = NULL, *outfile = NULL, *cfgfile = NULL;
struct stat st;
- int opt;
+ int opt, ret;
prgname = argv[0];
@@ -309,7 +309,12 @@ int main(int argc, char *argv[])
exit(EXIT_FAILURE);
}
- fread(buf + IMAGE_OFFSET, sizeof(char), st.st_size, ifile);
+ ret = fread(buf + IMAGE_OFFSET, sizeof(char), st.st_size, ifile);
+
+ if(ret != st.st_size) {
+ fprintf(stderr, "Error while reading %s\n", infile);
+ exit(EXIT_FAILURE);
+ }
add_header(buf, st.st_size);