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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-01-31 08:53:38 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-31 10:41:08 +0100 |
| commit | 65683428c113c9fe114e2f89aa5e9b8909534a43 (patch) | |
| tree | d7b3471506424e44ff58144d97587efcdeb66f96 | |
| parent | a756af03562dcd2fb0ed9c6cdbbefc9983e108c3 (diff) | |
| download | barebox-65683428c113c9fe114e2f89aa5e9b8909534a43.tar.gz barebox-65683428c113c9fe114e2f89aa5e9b8909534a43.tar.xz | |
reset: stm32: drop STM32 MCU support in favor of simple reset driver
RCC reset will eventually get more involved when we add SCMI support.
Linux already has reset and clock control in the same driver.
As we now have a simple driver that can toggle resets on the STM32 MCUs
as well, we can drop the now duplicate support from the dedicated
STM32 reset driver.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220131075338.1869305-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | drivers/reset/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/reset/reset-stm32.c | 15 |
2 files changed, 2 insertions, 15 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 82c8516253..b12159094d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -43,7 +43,7 @@ config RESET_STM32 bool "STM32 Reset Driver" depends on ARCH_STM32MP || COMPILE_TEST help - This enables the reset controller driver for STM32MP and STM32 MCUs. + This enables the reset controller driver for STM32MP1. config RESET_STARFIVE bool "StarFive Controller Driver" if COMPILE_TEST diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c index 703ba1f072..186b2a8bc6 100644 --- a/drivers/reset/reset-stm32.c +++ b/drivers/reset/reset-stm32.c @@ -66,14 +66,6 @@ static void stm32mp_reset(void __iomem *reg, unsigned offset, bool assert) writel(BIT(offset), reg); } -static void stm32mcu_reset(void __iomem *reg, unsigned offset, bool assert) -{ - if (assert) - setbits_le32(reg, BIT(offset)); - else - clrbits_le32(reg, BIT(offset)); -} - static u32 stm32_reset_status(struct stm32_reset *priv, unsigned long bank) { return readl(priv->base + bank); @@ -195,18 +187,13 @@ static const struct stm32_reset_ops stm32mp1_reset_ops = { .reset_reasons = stm32mp_reset_reasons, }; -static const struct stm32_reset_ops stm32mcu_reset_ops = { - .reset = stm32mcu_reset, -}; - static const struct of_device_id stm32_rcc_reset_dt_ids[] = { { .compatible = "st,stm32mp1-rcc", .data = &stm32mp1_reset_ops }, - { .compatible = "st,stm32-rcc", .data = &stm32mcu_reset_ops }, { /* sentinel */ }, }; static struct driver_d stm32_rcc_reset_driver = { - .name = "stm32_rcc_reset", + .name = "stm32mp_rcc_reset", .probe = stm32_reset_probe, .of_compatible = DRV_OF_COMPAT(stm32_rcc_reset_dt_ids), }; |