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authorSascha Hauer <s.hauer@pengutronix.de>2019-01-15 13:42:54 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-01-15 13:42:54 +0100
commit05cb1e23acbbb0ef8cad0c368981460251725d72 (patch)
treee779c6f005d93b636a4351713e01c7e4b7c1825f
parent595cdd17b7906ac6945d2b543af31a01b0a51173 (diff)
parent29841dfa4b3b31189c5ec28d17ca52f7a5d2d522 (diff)
downloadbarebox-05cb1e23acbbb0ef8cad0c368981460251725d72.tar.gz
barebox-05cb1e23acbbb0ef8cad0c368981460251725d72.tar.xz
Merge branch 'for-next/imx'
-rw-r--r--Documentation/boards/imx/nxp-imx8mq-evk.rst4
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boards/ccxmx51/Makefile4
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51.c626
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51.h35
-rw-r--r--arch/arm/boards/ccxmx51/ccxmx51js.c103
-rw-r--r--arch/arm/boards/ccxmx51/defaultenv-ccxmx51/boot/nand (renamed from arch/arm/boards/ccxmx51/env/boot/nand)0
-rw-r--r--arch/arm/boards/ccxmx51/defaultenv-ccxmx51/nv/boot.default (renamed from arch/arm/boards/ccxmx51/env/nv/boot.default)0
-rw-r--r--arch/arm/boards/ccxmx51/env/init/mtdparts-nand6
-rw-r--r--arch/arm/boards/ccxmx51/env/nv/autoboot_timeout1
-rw-r--r--arch/arm/boards/ccxmx51/lowlevel.c15
-rw-r--r--arch/arm/boards/efika-mx-smartbook/board.c2
-rw-r--r--arch/arm/boards/phytec-phycard-imx27/lowlevel.c52
-rw-r--r--arch/arm/boards/zii-imx6q-rdu2/Makefile2
-rw-r--r--arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c49
-rw-r--r--arch/arm/configs/ccmx51_defconfig60
-rw-r--r--arch/arm/configs/efika-mx-smartbook_defconfig106
-rw-r--r--arch/arm/configs/imx_v7_defconfig2
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx51-ccxmx51.dts41
-rw-r--r--arch/arm/dts/imx6qdl-nitrogen6x.dtsi3
-rw-r--r--arch/arm/dts/imx8mq-evk.dts427
-rw-r--r--arch/arm/dts/imx8mq-pinfunc.h623
-rw-r--r--arch/arm/dts/imx8mq.dtsi772
-rw-r--r--arch/arm/mach-imx/Kconfig32
-rw-r--r--arch/arm/mach-imx/imx7.c9
-rw-r--r--common/imx-bbu-nand-fcb.c12
-rw-r--r--drivers/clk/clk-divider.c30
-rw-r--r--drivers/clk/clk-gate.c12
-rw-r--r--drivers/clk/clk-mux.c11
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-composite-8m.c171
-rw-r--r--drivers/clk/imx/clk-imx5.c3
-rw-r--r--drivers/clk/imx/clk-imx8mq.c535
-rw-r--r--drivers/clk/imx/clk.h19
-rw-r--r--drivers/mfd/rave-sp.c72
-rw-r--r--drivers/mtd/core.c25
-rw-r--r--drivers/nvmem/ocotp.c13
-rw-r--r--drivers/pinctrl/imx-iomux-v3.c4
-rw-r--r--drivers/spi/imx_spi.c11
-rw-r--r--drivers/video/rave-sp-backlight.c2
-rw-r--r--images/Makefile.imx15
-rw-r--r--include/dt-bindings/clock/imx8mq-clock.h629
-rw-r--r--include/linux/clk.h30
-rw-r--r--include/linux/kernel.h5
-rw-r--r--include/linux/mfd/rave-sp.h1
-rw-r--r--include/mfd/mc13892.h23
47 files changed, 1131 insertions, 3469 deletions
diff --git a/Documentation/boards/imx/nxp-imx8mq-evk.rst b/Documentation/boards/imx/nxp-imx8mq-evk.rst
index f0cdc34866..dfe004e0e4 100644
--- a/Documentation/boards/imx/nxp-imx8mq-evk.rst
+++ b/Documentation/boards/imx/nxp-imx8mq-evk.rst
@@ -45,8 +45,8 @@ DDR Configuration Code
The following two files:
- - ddr_init.c
- - ddrphy_train.c
+ - arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
+ - arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
were obtained by running i.MX 8M DDR Tool that can be found here:
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5db67b9db8..2d55bc69a3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -246,7 +246,6 @@ barebox.imximg: $(KBUILD_BINARY) FORCE
boarddir = $(srctree)/arch/arm/boards
imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_TX51) += $(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg
imxcfg-$(CONFIG_MACH_GUF_VINCELL) += $(boarddir)/guf-vincell/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += $(boarddir)/eukrea_cpuimx51/flash-header.imxcfg
diff --git a/arch/arm/boards/ccxmx51/Makefile b/arch/arm/boards/ccxmx51/Makefile
index 6ba98b12de..50cf929c5d 100644
--- a/arch/arm/boards/ccxmx51/Makefile
+++ b/arch/arm/boards/ccxmx51/Makefile
@@ -1,3 +1,3 @@
obj-y += ccxmx51.o
-lwl-y += lowlevel.o
-obj-$(CONFIG_MACH_CCMX51_BASEBOARD) += ccxmx51js.o
+lwl-y += lowlevel.o
+bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-ccxmx51
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index 71a51e1927..13fba51fec 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -1,477 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009-2010 Digi International, Inc.
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* (c) 2011 Eukrea Electromatique, Eric BĂ©nard <eric@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * Modified for barebox by Alexander Shiyan <shc_work@mail.ru>
*/
#include <common.h>
-#include <net.h>
+#include <envfs.h>
#include <init.h>
-#include <environment.h>
-#include <mach/imx51-regs.h>
-#include <platform_data/eth-fec.h>
+#include <net.h>
+#include <notifier.h>
#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <fs.h>
-#include <fcntl.h>
#include <linux/sizes.h>
-#include <nand.h>
-#include <notifier.h>
-#include <spi/spi.h>
#include <mfd/mc13xxx.h>
-#include <asm/io.h>
-#include <mach/imx-nand.h>
-#include <mach/spi.h>
-#include <mach/generic.h>
-#include <mach/iomux-mx51.h>
-#include <mach/devices-imx51.h>
+#include <mfd/mc13892.h>
+
+#include <mach/bbu.h>
+#include <mach/esdctl.h>
#include <mach/iim.h>
-#include <mach/clock-imx51_53.h>
#include <mach/imx5.h>
+#include <mach/imx51-regs.h>
#include <mach/revision.h>
-#include <mach/esdctl.h>
-
-#include "ccxmx51.h"
-
-static struct ccxmx51_ident ccxmx51_ids[] = {
-/* 0x00 */ { "Unknown", 0, 0, 0, 0, 0 },
-/* 0x01 */ { "Not supported", 0, 0, 0, 0, 0 },
-/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1 },
-/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0 },
-/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1 },
-/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 0 },
-/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
-/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
-/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 0, 1, 0, 1 },
-/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", SZ_256M, 0, 1, 0, 0 },
-/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 1, 1, 0, 1 },
-/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", SZ_256M, 1, 1, 0, 0 },
-/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 0, 1, 0, 1 },
-/* 0x0d */ { "i.MX512@800MHz", SZ_128M, 0, 0, 0, 0 },
-/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
-/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", SZ_128M, 1, 1, 0, 0 },
-/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 1, 1, 0, 1 },
-/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", SZ_128M, 0, 1, 0, 0 },
-/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1 },
-/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
-};
-
-struct ccxmx51_ident *ccxmx51_id;
-
-struct imx_nand_platform_data nand_info = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static struct fec_platform_data fec_info = {
- .xcv_type = PHY_INTERFACE_MODE_MII,
- .phy_addr = 7,
-};
-static iomux_v3_cfg_t ccxmx51_pads[] = {
- /* UART1 */
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- /* UART2 */
- MX51_PAD_UART2_RXD__UART2_RXD,
- MX51_PAD_UART2_TXD__UART2_TXD,
- /* UART3 */
- MX51_PAD_UART3_RXD__UART3_RXD,
- MX51_PAD_UART3_TXD__UART3_TXD,
- /* I2C2 */
- MX51_PAD_GPIO1_2__I2C2_SCL,
- MX51_PAD_GPIO1_3__I2C2_SDA,
- /* eCSPI1 */
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
- MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
- MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
- /* FEC */
- MX51_PAD_DISP2_DAT14__FEC_RDATA0,
- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
- MX51_PAD_DI_GP4__FEC_RDATA2,
- MX51_PAD_DISP2_DAT0__FEC_RDATA3,
- MX51_PAD_DISP2_DAT15__FEC_TDATA0,
- MX51_PAD_DISP2_DAT6__FEC_TDATA1,
- MX51_PAD_DISP2_DAT7__FEC_TDATA2,
- MX51_PAD_DISP2_DAT8__FEC_TDATA3,
- MX51_PAD_DISP2_DAT9__FEC_TX_EN,
- MX51_PAD_DISP2_DAT10__FEC_COL,
- MX51_PAD_DISP2_DAT11__FEC_RX_CLK,
- MX51_PAD_DISP2_DAT12__FEC_RX_DV,
- MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
- MX51_PAD_DI2_PIN2__FEC_MDC,
- MX51_PAD_DI2_PIN4__FEC_CRS,
- MX51_PAD_DI2_PIN3__FEC_MDIO,
- MX51_PAD_DI_GP3__FEC_TX_ER,
- MX51_PAD_DISP2_DAT1__FEC_RX_ER,
- /* WEIM */
- MX51_PAD_EIM_DA0__EIM_DA0,
- MX51_PAD_EIM_DA1__EIM_DA1,
- MX51_PAD_EIM_DA2__EIM_DA2,
- MX51_PAD_EIM_DA3__EIM_DA3,
- MX51_PAD_EIM_DA4__EIM_DA4,
- MX51_PAD_EIM_DA5__EIM_DA5,
- MX51_PAD_EIM_DA6__EIM_DA6,
- MX51_PAD_EIM_DA7__EIM_DA7,
- MX51_PAD_EIM_D16__EIM_D16,
- MX51_PAD_EIM_D17__EIM_D17,
- MX51_PAD_EIM_D18__EIM_D18,
- MX51_PAD_EIM_D19__EIM_D19,
- MX51_PAD_EIM_D20__EIM_D20,
- MX51_PAD_EIM_D21__EIM_D21,
- MX51_PAD_EIM_D22__EIM_D22,
- MX51_PAD_EIM_D23__EIM_D23,
- MX51_PAD_EIM_D24__EIM_D24,
- MX51_PAD_EIM_D25__EIM_D25,
- MX51_PAD_EIM_D26__EIM_D26,
- MX51_PAD_EIM_D27__EIM_D27,
- MX51_PAD_EIM_D28__EIM_D28,
- MX51_PAD_EIM_D29__EIM_D29,
- MX51_PAD_EIM_D30__EIM_D30,
- MX51_PAD_EIM_D31__EIM_D31,
- MX51_PAD_EIM_OE__EIM_OE,
- MX51_PAD_EIM_CS5__EIM_CS5,
- /* NAND */
- MX51_PAD_NANDF_D0__NANDF_D0,
- MX51_PAD_NANDF_D1__NANDF_D1,
- MX51_PAD_NANDF_D2__NANDF_D2,
- MX51_PAD_NANDF_D3__NANDF_D3,
- MX51_PAD_NANDF_D4__NANDF_D4,
- MX51_PAD_NANDF_D5__NANDF_D5,
- MX51_PAD_NANDF_D6__NANDF_D6,
- MX51_PAD_NANDF_D7__NANDF_D7,
- MX51_PAD_NANDF_ALE__NANDF_ALE,
- MX51_PAD_NANDF_CLE__NANDF_CLE,
- MX51_PAD_NANDF_RE_B__NANDF_RE_B,
- MX51_PAD_NANDF_WE_B__NANDF_WE_B,
- MX51_PAD_NANDF_WP_B__NANDF_WP_B,
- MX51_PAD_NANDF_CS0__NANDF_CS0,
- MX51_PAD_NANDF_RB0__NANDF_RB0,
- /* LAN9221 IRQ (GPIO1.9) */
- MX51_PAD_GPIO1_9__GPIO1_9,
- /* MC13892 IRQ (GPIO1.5) */
- MX51_PAD_GPIO1_5__GPIO1_5,
- /* MMA7455LR IRQ1 (GPIO1.7) */
- MX51_PAD_GPIO1_7__GPIO1_7,
- /* MMA7455LR IRQ2 (GPIO1.6) */
- MX51_PAD_GPIO1_6__GPIO1_6,
- /* User GPIOs */
- MX51_PAD_GPIO1_0__GPIO1_0,
- MX51_PAD_GPIO1_1__GPIO1_1,
- MX51_PAD_GPIO1_8__GPIO1_8,
- MX51_PAD_DI1_PIN11__GPIO3_0,
- MX51_PAD_DI1_PIN12__GPIO3_1,
- MX51_PAD_DI1_PIN13__GPIO3_2,
- MX51_PAD_DI1_D0_CS__GPIO3_3,
- MX51_PAD_DI1_D1_CS__GPIO3_4,
- MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
- MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
- MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
- MX51_PAD_DISPB2_SER_RS__GPIO3_8,
- MX51_PAD_NANDF_RB1__GPIO3_9,
- MX51_PAD_NANDF_RB2__GPIO3_10,
- MX51_PAD_NANDF_RB3__GPIO3_11,
- MX51_PAD_CSI1_D8__GPIO3_12,
- MX51_PAD_CSI1_D9__GPIO3_13,
- MX51_PAD_NANDF_CS1__GPIO3_17,
- MX51_PAD_NANDF_CS2__GPIO3_18,
- MX51_PAD_NANDF_CS3__GPIO3_19,
- MX51_PAD_NANDF_CS4__GPIO3_20,
- MX51_PAD_NANDF_CS5__GPIO3_21,
- MX51_PAD_NANDF_CS6__GPIO3_22,
+static const struct ccxmx_ident {
+ char *id_string;
+ unsigned int mem_sz;
+ unsigned int cpu_mhz;
+ unsigned char eth0:1;
+ unsigned char eth1:1;
+ unsigned char wless:1;
+ unsigned char accel:1;
+} *ccxmx_id, ccxmx51_ids[] = {
+ [0x00] = { NULL /* Unknown */, 0, 0, 0, 0, 0, 0 },
+ [0x01] = { NULL /* Not supported */, 0, 0, 0, 0, 0, 0 },
+ [0x02] = { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 1, 1 },
+ [0x03] = { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 0, 1 },
+ [0x04] = { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 600, 1, 1, 1, 1 },
+ [0x05] = { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 600, 1, 1, 0, 1 },
+ [0x06] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 800, 1, 0, 1, 1 },
+ [0x07] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 },
+ [0x08] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 800, 1, 0, 1, 1 },
+ [0x09] = { "i.MX515@800MHz, PHY, Accel", SZ_256M, 800, 1, 0, 0, 1 },
+ [0x0a] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 600, 1, 0, 1, 1 },
+ [0x0b] = { "i.MX515@600MHz, PHY, Accel", SZ_256M, 600, 1, 0, 0, 1 },
+ [0x0c] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 800, 1, 0, 1, 1 },
+ [0x0d] = { "i.MX512@800MHz", SZ_128M, 800, 0, 0, 0, 0 },
+ [0x0e] = { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 800, 1, 0, 1, 1 },
+ [0x0f] = { "i.MX515@600MHz, PHY, Accel", SZ_128M, 600, 1, 0, 0, 1 },
+ [0x10] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 600, 1, 0, 1, 1 },
+ [0x11] = { "i.MX515@800MHz, PHY, Accel", SZ_128M, 800, 1, 0, 0, 1 },
+ [0x12] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 600, 1, 0, 1, 1 },
+ [0x13] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 },
};
-#define CCXMX51_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
-#define CCXMX51_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
+static u32 boardserial;
-static int ecspi_0_cs[] = { CCXMX51_ECSPI1_CS0, CCXMX51_ECSPI1_CS1, };
-
-static struct spi_imx_master ecspi_0_data = {
- .chipselect = ecspi_0_cs,
- .num_chipselect = ARRAY_SIZE(ecspi_0_cs),
-};
-
-static const struct spi_board_info ccxmx51_spi_board_info[] = {
- {
- .name = "mc13892",
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static struct imxusb_platformdata ccxmx51_otg_pdata = {
- .flags = MXC_EHCI_MODE_UTMI_16_BIT | MXC_EHCI_POWER_PINS_ENABLED,
- .mode = IMX_USB_MODE_HOST,
-};
-
-static int ccxmx51_power_init(void)
+static void ccxmx51_power_init(struct mc13xxx *mc13xxx)
{
- struct mc13xxx *mc13xxx_dev;
u32 val;
- mc13xxx_dev = mc13xxx_get();
- if (!mc13xxx_dev)
- return -ENODEV;
-
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val);
- /* Reset devices by clearing GP01-GPO4 */
- val &= ~((1 << 21) | (3 << 12) | (3 << 10) | (3 << 8) | (3 << 6));
- /* Switching off the PWGT1SPIEN */
- val |= (1 << 15);
- /* Switching on the PWGT2SPIEN */
- val &= ~(1 << 16);
- /* Enable short circuit protection */
- val |= (1 << 0);
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val);
-
- /* Allow charger to charge (4.2V and 560mA) */
- val = 0x238033;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_CHARGE, val);
-
- if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
- /* Set core voltage (SW1) to 1.1V */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_0, &val);
- val &= ~0x00001f;
- val |= 0x000014;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_0, val);
-
- /* Setup VCC (SW2) to 1.25 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val);
- val &= ~0x00001f;
- val |= 0x00001a;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val);
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val);
- val &= ~0x00001f;
- val |= 0x00001a;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val);
- } else {
- /* Setup VCC (SW2) to 1.225 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val);
- val &= ~0x00001f;
- val |= 0x000019;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val);
-
- /* Setup 1V2_DIG1 (SW3) to 1.2 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val);
- val &= ~0x00001f;
- val |= 0x000018;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val);
- }
-
- if (mc13xxx_revision(mc13xxx_dev) <= MC13892_REVISION_2_0) {
- /* Set switchers in PWM mode for Atlas 2.0 and lower */
- /* Setup the switcher mode for SW1 & SW2*/
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val);
- val &= ~0x003c0f;
- val |= 0x001405;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val);
- val &= ~0x000f0f;
- val |= 0x000505;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val);
- } else {
- /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
- /* Setup the switcher mode for SW1 & SW2*/
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val);
- val &= ~0x003c0f;
- val |= 0x002008;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val);
- val &= ~0x000f0f;
- val |= 0x000808;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val);
- }
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_1, &val);
- val &= ~0x0001fc;
- val |= 0x0001f4;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_1, val);
+ /* Clear GP01-GPO4, enable short circuit protection, PWGT1SPIEN off */
+ val = MC13892_POWER_MISC_REGSCPEN | MC13892_POWER_MISC_PWGT1SPIEN;
+ val |= MC13892_POWER_MISC_GPO4ADIN;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
+
+ /* Set ICHRG in externally powered mode, 4.2V, Disable thermistor */
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0xa3827b);
+
+ /* Set core voltage (SW1) to 1.1V NORMAL, 1.05V STANDBY */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT);
+ val |= MC13892_SWx_SWx_1_100V << MC13892_SWMODE1_SHIFT;
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT);
+ val |= MC13892_SWx_SWx_1_050V << MC13892_SWMODE2_SHIFT;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.225 NORMAL, 1.175V STANDBY */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT);
+ val |= MC13892_SWx_SWx_1_225V << MC13892_SWMODE1_SHIFT;
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT);
+ val |= MC13892_SWx_SWx_1_175V << MC13892_SWMODE2_SHIFT;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.2 NORMAL, 1.15V STANDBY */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE1_SHIFT);
+ val |= MC13892_SWx_SWx_1_200V << MC13892_SWMODE1_SHIFT;
+ val &= ~(MC13892_SWx_SWx_VOLT_MASK << MC13892_SWMODE2_SHIFT);
+ val |= MC13892_SWx_SWx_1_150V << MC13892_SWMODE2_SHIFT;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
+
+ /* Set SW1-SW4 switcher in Auto in NORMAL & STANDBY mode */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
+ val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE1_SHIFT);
+ val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE1_SHIFT;
+ val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE2_SHIFT);
+ val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE2_SHIFT;
+ /* Disable current limit */
+ val |= 1 << 22;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
+
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
+ val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE3_SHIFT);
+ val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE3_SHIFT;
+ val &= ~(MC13892_SWMODE_MASK << MC13892_SWMODE4_SHIFT);
+ val |= MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE4_SHIFT;
+ /* Enable SWBST */
+ val |= 1 << 20;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
+
+ /* Set VVIDEO=2.775V, VAUDIO=3V, VSD=3.15V */
+ val = MC13892_SETTING_1_VVIDEO_2_775 | MC13892_SETTING_1_VAUDIO_3_0;
+ val |= MC13892_SETTING_1_VSD_3_15;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
- val = 0x000208;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val);
+ val = MC13892_MODE_1_VGEN3CONFIG | MC13892_MODE_1_VCAMCONFIG;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
- /* Set VGEN3 to 1.8V */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_0, &val);
- val &= ~(1 << 14);
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_0, val);
+ /* Set VGEN2=3.15V, VGEN3=1.8V, VDIG=1.25V, VCAM=2.75V */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
+ val &= ~(MC13892_SETTING_0_VGEN2_MASK | MC13892_SETTING_0_VGEN3_MASK);
+ val |= MC13892_SETTING_0_VGEN2_3_15 | MC13892_SETTING_0_VGEN3_1_8;
+ val &= ~(MC13892_SETTING_0_VDIG_MASK | MC13892_SETTING_0_VCAM_MASK);
+ val |= MC13892_SETTING_0_VDIG_1_25 | MC13892_SETTING_0_VCAM_2_75;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = 0x049249;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val);
+ /* Enable OTG function */
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_USB1, 0x409);
- /* Enable USB1 charger */
- val = 0x000409;
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_USB1, val);
-
- /* Set VCOIN to 3.0V and Enable It */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_CTL0, &val);
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = MC13892_MODE_1_VGEN3EN | MC13892_MODE_1_VGEN3CONFIG;
+ val |= MC13892_MODE_1_VCAMEN | MC13892_MODE_1_VCAMCONFIG;
+ val |= MC13892_MODE_1_VVIDEOEN | MC13892_MODE_1_VAUDIOEN;
+ val |= MC13892_MODE_1_VSDEN;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
+
+ /* Set VCOIN=3.0V, Keeps VSRTC and CLK32KMCU */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_CTL0, &val);
val &= ~(7 << 20);
- val |= (4 << 20) | (1 << 23);
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val);
- /* Keeps VSRTC and CLK32KMCU */
- val |= (1 << 4);
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val);
-
- /* De-assert reset of external devices on GP01, GPO2, GPO3 and GPO4 */
- mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val);
+ val |= (1 << 4) | (4 << 20) | (1 << 23);
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_CTL0, val);
+
+ /* De-assert reset of external devices on GP01-GPO4 */
+ mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
/* GPO1 - External */
/* GP02 - LAN9221 Power */
/* GP03 - FEC Reset */
/* GP04 - Wireless Power */
- if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth1) {
- val |= (1 << 8);
- mdelay(50);
+ if (ccxmx_id->eth1) {
+ val |= MC13892_POWER_MISC_GPO2EN;
+ mdelay(100);
}
- if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth0)
- val |= (1 << 10);
- if (ccxmx51_id->wless)
- val |= (1 << 12);
- mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val);
+ if (ccxmx_id->eth0)
+ val |= MC13892_POWER_MISC_GPO3EN;
+ if (ccxmx_id->wless)
+ val |= MC13892_POWER_MISC_GPO4EN;
+ mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
udelay(100);
- return 0;
+ console_flush();
+ imx51_init_lowlevel(ccxmx_id->cpu_mhz);
+ clock_notifier_call_chain();
+
+ printf("MC13892 PMIC initialized.\n");
}
-/*
- * On this board the SDRAM is always configured for 512Mib. The real
- * size is determined by the board id read from the IIM module.
- */
-static int ccxmx51_sdram_fixup(void)
+static void ccxmx51_disable_device(struct device_node *root, const char *label)
{
- imx_esdctl_disable();
+ struct device_node *np = of_find_node_by_name(root, label);
+ if (np)
+ of_device_disable(np);
+}
+
+static int ccxmx51_board_fixup(struct device_node *root, void *unused)
+{
+ char *serial;
+
+ if (!ccxmx_id->accel)
+ ccxmx51_disable_device(root, "mma7455l@1d");
+
+ if (!ccxmx_id->eth0)
+ ccxmx51_disable_device(root, "ethernet@83fec000");
+
+ if (!ccxmx_id->eth1)
+ ccxmx51_disable_device(root, "lan9221@5,0");
+
+ if (!ccxmx_id->wless)
+ ccxmx51_disable_device(root, "esdhc@70008000");
+
+ serial = basprintf("%08x%08x", 0, boardserial);
+ of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1);
+ free(serial);
return 0;
}
-postcore_initcall(ccxmx51_sdram_fixup);
-static int ccxmx51_memory_init(void)
+static __init int ccxmx51_is_compatible(void)
{
+ return of_machine_is_compatible("digi,connectcore-ccxmx51-som");
+}
+
+static __init int ccxmx51_sdram_fixup(void)
+{
+ if (!ccxmx51_is_compatible())
+ return 0;
+
arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, SZ_128M);
+ /*
+ * On this board the SDRAM is always configured for 512Mib. The real
+ * size is determined by the board id read from the IIM module.
+ */
+ imx_esdctl_disable();
+
+ of_register_fixup(ccxmx51_board_fixup, NULL);
+
return 0;
}
-mem_initcall(ccxmx51_memory_init);
+postcore_initcall(ccxmx51_sdram_fixup);
-static int ccxmx51_devices_init(void)
+static __init int ccxmx51_init(void)
{
+ char manloc = 'N';
u8 hwid[6];
- int pwr;
- char manloc;
-
- if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids)))
- memset(hwid, 0x00, sizeof(hwid));
-
- ccxmx51_id = &ccxmx51_ids[hwid[0]];
- printf("Module Variant: %s (0x%02x)\n", ccxmx51_id->id_string, hwid[0]);
-
- if (hwid[0]) {
- printf("Module HW Rev : %02x\n", hwid[1] + 1);
- switch (hwid[2] & 0xc0) {
- case 0x00:
- manloc = 'B';
- break;
- case 0x40:
- manloc = 'W';
- break;
- case 0x80:
- manloc = 'S';
- break;
- default:
- manloc = 'N';
- break;
- }
- printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
- if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
- arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
- } else
- return -ENOSYS;
-
- imx51_add_uart1();
- imx51_add_uart2();
-
- spi_register_board_info(ccxmx51_spi_board_info, ARRAY_SIZE(ccxmx51_spi_board_info));
- imx51_add_spi0(&ecspi_0_data);
-
- pwr = ccxmx51_power_init();
- console_flush();
- imx51_init_lowlevel((ccxmx51_id->industrial || pwr) ? 600 : 800);
- clock_notifier_call_chain();
- if (pwr)
- printf("Could not setup PMIC. Clocks not adjusted.\n");
- imx51_add_i2c1(NULL);
+ if (!ccxmx51_is_compatible())
+ return 0;
- imx51_add_nand(&nand_info);
- devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
- dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x80000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw");
- dev_add_bb_dev("env_raw", "env0");
-
- if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth0 && !pwr) {
- eth_register_ethaddr(0, hwid);
- imx51_add_fec(&fec_info);
+ if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) ||
+ (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) {
+ printf("Unknown board variant (0x%02x). System halted.\n", hwid[0]);
+ hang();
}
- if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth1 && !pwr) {
- /* Configure the WEIM CS5 timming, bus width, etc */
- /* 16 bit on DATA[31..16], not multiplexed, async */
- writel(0x00420081, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR1(5));
- /* ADH has not effect on non muxed bus */
- writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR2(5));
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR1(5));
- /* APR=0 */
- writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR2(5));
- /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0 */
- writel(0x72080f00, MX51_WEIM_BASE_ADDR + WEIM_CSxWCR1(5));
-
- /* LAN9221 network controller */
- add_generic_device("smc911x", 1, NULL, MX51_CS5_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL);
+ ccxmx_id = &ccxmx51_ids[hwid[0]];
+
+ switch (hwid[2] & 0xc0) {
+ case 0x00:
+ manloc = 'B';
+ break;
+ case 0x40:
+ manloc = 'W';
+ break;
+ case 0x80:
+ manloc = 'S';
+ break;
+ default:
+ break;
}
- imx51_add_usbotg(&ccxmx51_otg_pdata);
+ eth_register_ethaddr(0, hwid);
- armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51 : MACH_TYPE_CCMX51);
+ boardserial = ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5];
- return 0;
-}
-device_initcall(ccxmx51_devices_init);
+ printf("Module Variant: %s (0x%02x)\n", ccxmx_id->id_string, hwid[0]);
+ printf("Module HW Rev : %02x\n", hwid[1] + 1);
+ printf("Module Serial : %c%d\n", manloc, boardserial);
-static int ccxmx51_console_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(ccxmx51_pads, ARRAY_SIZE(ccxmx51_pads));
+ if ((ccxmx_id->mem_sz - SZ_128M) > 0)
+ arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M,
+ ccxmx_id->mem_sz - SZ_128M);
+
+ mc13xxx_register_init_callback(ccxmx51_power_init);
- barebox_set_model("Digi ConnectCore i.MX51");
- barebox_set_hostname("ccmx51");
+ imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
+ BBU_HANDLER_FLAG_DEFAULT);
- imx51_add_uart0();
+ if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
+ defaultenv_append_directory(defaultenv_ccxmx51);
return 0;
}
-console_initcall(ccxmx51_console_init);
+fs_initcall(ccxmx51_init);
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h
deleted file mode 100644
index 3feacac034..0000000000
--- a/arch/arm/boards/ccxmx51/ccxmx51.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2010 Digi International Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef _CCXMX51_H_
-#define _CCXMX51_H_
-
-struct ccxmx51_hwid {
- u8 variant;
- u8 version;
- u32 sn;
- char mloc;
-};
-
-struct ccxmx51_ident {
- const char *id_string;
- const int mem_sz;
- const char industrial;
- const char eth0;
- const char eth1;
- const char wless;
-};
-
-extern struct ccxmx51_ident *ccxmx51_id;
-
-#endif /* _CCXMX51_H_ */
diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c
deleted file mode 100644
index 7f068e239a..0000000000
--- a/arch/arm/boards/ccxmx51/ccxmx51js.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <io.h>
-#include <init.h>
-#include <gpio.h>
-#include <mci.h>
-#include <asm/armlinux.h>
-#include <mach/generic.h>
-#include <mach/imx51-regs.h>
-#include <mach/iomux-mx51.h>
-#include <mach/devices-imx51.h>
-#include <generated/mach-types.h>
-
-#include "ccxmx51.h"
-
-#define CCXMX51JS_USBH1_RESET IMX_GPIO_NR(3, 8)
-#define CCXMX51JS_SD3_WP IMX_GPIO_NR(3, 17)
-
-static iomux_v3_cfg_t ccxmx51js_pads[] = {
- /* SD1 */
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- /* SD3 */
- MX51_PAD_NANDF_CS7__SD3_CLK,
- MX51_PAD_NANDF_RDY_INT__SD3_CMD,
- MX51_PAD_NANDF_D8__SD3_DATA0,
- MX51_PAD_NANDF_D9__SD3_DATA1,
- MX51_PAD_NANDF_D10__SD3_DATA2,
- MX51_PAD_NANDF_D11__SD3_DATA3,
- MX51_PAD_NANDF_D12__SD3_DAT4,
- MX51_PAD_NANDF_D13__SD3_DAT5,
- MX51_PAD_NANDF_D14__SD3_DAT6,
- MX51_PAD_NANDF_D15__SD3_DAT7,
- /* USB HOST1 */
- MX51_PAD_USBH1_CLK__USBH1_CLK,
- MX51_PAD_USBH1_DIR__USBH1_DIR,
- MX51_PAD_USBH1_NXT__USBH1_NXT,
- MX51_PAD_USBH1_STP__USBH1_STP,
- MX51_PAD_USBH1_DATA0__USBH1_DATA0,
- MX51_PAD_USBH1_DATA1__USBH1_DATA1,
- MX51_PAD_USBH1_DATA2__USBH1_DATA2,
- MX51_PAD_USBH1_DATA3__USBH1_DATA3,
- MX51_PAD_USBH1_DATA4__USBH1_DATA4,
- MX51_PAD_USBH1_DATA5__USBH1_DATA5,
- MX51_PAD_USBH1_DATA6__USBH1_DATA6,
- MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-};
-
-static struct esdhc_platform_data sdhc1_pdata = {
- .cd_type = ESDHC_CD_NONE,
- .wp_type = ESDHC_WP_NONE,
- .caps = MMC_CAP_4_BIT_DATA,
-};
-
-static struct esdhc_platform_data sdhc3_pdata = {
- .cd_type = ESDHC_CD_NONE,
- .wp_type = ESDHC_WP_GPIO,
- .wp_gpio = CCXMX51JS_SD3_WP,
- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-};
-
-static struct imxusb_platformdata ccxmx51js_usbhost1_pdata = {
- .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_ITC_NO_THRESHOLD,
- .mode = IMX_USB_MODE_HOST,
-};
-
-static int ccxmx51js_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(ccxmx51js_pads, ARRAY_SIZE(ccxmx51js_pads));
-
- if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC)) {
- imx51_add_mmc0(&sdhc1_pdata);
- imx51_add_mmc2(&sdhc3_pdata);
- }
-
- gpio_direction_output(CCXMX51JS_USBH1_RESET, 0);
- mdelay(10);
- gpio_set_value(CCXMX51JS_USBH1_RESET, 1);
- mdelay(10);
- imx51_add_usbh1(&ccxmx51js_usbhost1_pdata);
-
- armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51JS : MACH_TYPE_CCMX51JS);
-
- return 0;
-}
-
-late_initcall(ccxmx51js_init);
diff --git a/arch/arm/boards/ccxmx51/env/boot/nand b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/boot/nand
index d53f07ec5d..d53f07ec5d 100644
--- a/arch/arm/boards/ccxmx51/env/boot/nand
+++ b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/boot/nand
diff --git a/arch/arm/boards/ccxmx51/env/nv/boot.default b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/nv/boot.default
index 026a25cc7e..026a25cc7e 100644
--- a/arch/arm/boards/ccxmx51/env/nv/boot.default
+++ b/arch/arm/boards/ccxmx51/defaultenv-ccxmx51/nv/boot.default
diff --git a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand
deleted file mode 100644
index 27ed38a888..0000000000
--- a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="512k(barebox)ro,256k(bareboxenv),3328k(kernel),-(root)"
-kernelname="mxc_nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout b/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout
deleted file mode 100644
index 0cfbf08886..0000000000
--- a/arch/arm/boards/ccxmx51/env/nv/autoboot_timeout
+++ /dev/null
@@ -1 +0,0 @@
-2
diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c
index 2b3dc42e87..462c22e284 100644
--- a/arch/arm/boards/ccxmx51/lowlevel.c
+++ b/arch/arm/boards/ccxmx51/lowlevel.c
@@ -1,3 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
#include <common.h>
#include <mach/esdctl.h>
#include <mach/generic.h>
@@ -5,8 +8,16 @@
#include <asm/barebox-arm-head.h>
#include <mach/imx51-regs.h>
-void __naked barebox_arm_reset_vector(void)
+ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2)
{
+ extern char __dtb_imx51_ccxmx51_start[];
+ void *fdt;
+
imx5_cpu_lowlevel_init();
- barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, NULL);
+
+ arm_setup_stack(0x20000000 - 16);
+
+ fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset();
+
+ barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt);
}
diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c
index d7c5681dbc..ec41eb8c11 100644
--- a/arch/arm/boards/efika-mx-smartbook/board.c
+++ b/arch/arm/boards/efika-mx-smartbook/board.c
@@ -79,7 +79,7 @@ static void efikamx_power_init(struct mc13xxx *mc)
/* power up the system first */
mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC,
- MC13892_POWER_MISC_PWUP);
+ MC13892_POWER_MISC_GPO4ADIN);
/* Set core voltage to 1.1V */
mc13xxx_reg_read(mc, MC13892_REG_SW_0, &val);
diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index e1132e0b54..1e96c0893f 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -15,11 +15,30 @@
#include <mach/esdctl.h>
#include <mach/imx-nand.h>
-#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+enum {
+ PHYCARD_MICRON_64MB,
+ PHYCARD_MICRON_128MB,
+};
-static void sdram_init(void)
+#define ESDCTL0_VAL_64MB (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL9)
+#define ESDCFG0_VAL_64MB 0x00696429
+#define ESDCTL0_VAL_128MB (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+#define ESDCFG0_VAL_128MB 0x006ac73a
+
+static void sdram_init(int sdram)
{
int i;
+ unsigned esdcfg, esdctl;
+
+ if (sdram == PHYCARD_MICRON_64MB) {
+ esdcfg = ESDCFG0_VAL_64MB;
+ esdctl = ESDCTL0_VAL_64MB;
+ } else if (sdram == PHYCARD_MICRON_128MB) {
+ esdcfg = ESDCFG0_VAL_128MB;
+ esdctl = ESDCTL0_VAL_128MB;
+ } else {
+ hang();
+ }
/*
* DDR on CSD0
@@ -36,29 +55,29 @@ static void sdram_init(void)
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
- writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(esdcfg, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* precharge CSD0 all banks */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ writel(esdctl | ESDCTL0_SMODE_PRECHARGE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ writel(esdctl | ESDCTL0_SMODE_AUTO_REFRESH,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ writel(esdctl | ESDCTL0_SMODE_LOAD_MODE,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ writel(esdctl | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
-void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
+void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram)
{
unsigned long r;
@@ -96,14 +115,25 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
- sdram_init();
+ sdram_init(sdram);
imx27_barebox_boot_nand_external(fdt);
}
extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[];
-ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2)
+ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2)
+{
+ void *fdt;
+
+ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
+
+ fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
+
+ phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_64MB);
+}
+
+ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2)
{
void *fdt;
@@ -111,5 +141,5 @@ ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2)
fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
- phytec_phycard_imx27_common_init(fdt);
+ phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_128MB);
}
diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile
index c6285362f2..10dfba3a3c 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/Makefile
+++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile
@@ -1,3 +1,3 @@
-obj-y += board.o
+obj-y += board.o switch-cmd.o
lwl-y += lowlevel.o
bbenv-y += defaultenv-rdu2
diff --git a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c b/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c
new file mode 100644
index 0000000000..bdba46fb36
--- /dev/null
+++ b/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <common.h>
+#include <command.h>
+#include <i2c/i2c.h>
+
+static int do_rave_switch_reset(int argc, char *argv[])
+{
+ struct i2c_client client;
+ u8 reg;
+
+ if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
+ !of_machine_is_compatible("zii,imx6qp-zii-rdu2"))
+ return -ENODEV;
+
+ client.adapter = i2c_get_adapter(1);
+ if (!client.adapter)
+ return -ENODEV;
+
+ /* address of the switch watchdog microcontroller */
+ client.addr = 0x38;
+ reg = 0x78;
+ /* set switch reset time to 100ms */
+ i2c_write_reg(&client, 0x0a, &reg, 1);
+ /* reset the switch */
+ reg = 0x01;
+ i2c_write_reg(&client, 0x0d, &reg, 1);
+ /* issue dummy command to work around firmware bug */
+ i2c_read_reg(&client, 0x01, &reg, 1);
+
+ return 0;
+}
+
+BAREBOX_CMD_START(rave_reset_switch)
+ .cmd = do_rave_switch_reset,
+ BAREBOX_CMD_DESC("reset ethernet switch on RDU2")
+ BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
+BAREBOX_CMD_END
diff --git a/arch/arm/configs/ccmx51_defconfig b/arch/arm/configs/ccmx51_defconfig
deleted file mode 100644
index c16f73f7b1..0000000000
--- a/arch/arm/configs/ccmx51_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_CCMX51=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/ccxmx51/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_ARM_MMUINFO=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NANDTEST=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_OFTREE=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_DRIVER_NET_SMC911X=y
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_NAND_IMX=y
-CONFIG_USB_HOST=y
-CONFIG_USB_IMX_CHIPIDEA=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_STORAGE=y
-CONFIG_MCI=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_FS_CRAMFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/efika-mx-smartbook_defconfig b/arch/arm/configs/efika-mx-smartbook_defconfig
deleted file mode 100644
index a988a0c54d..0000000000
--- a/arch/arm/configs/efika-mx-smartbook_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_IMX_MULTI_BOARDS=y
-CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_THUMB2_BAREBOX=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_BOOTM_VERBOSE=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_BOOTM_OFTREE=y
-CONFIG_BOOTM_OFTREE_UIMAGE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/efika-mx-smartbook/env/"
-CONFIG_RESET_SOURCE=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_ARM_MMUINFO=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LED=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_LED_TRIGGER=y
-CONFIG_CMD_WD=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_TIME=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_OFDEVICE=y
-CONFIG_NET_USB=y
-CONFIG_NET_USB_ASIX=y
-CONFIG_NET_USB_SMSC95XX=y
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_M25P80=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_DISK_INTF_PLATFORM_IDE=y
-CONFIG_DISK_PATA_IMX=y
-CONFIG_USB_HOST=y
-CONFIG_USB_IMX_CHIPIDEA=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_STORAGE=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_IMX=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 64b202b9dc..2068a6cee4 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_KINDLE_MX50=y
+CONFIG_MACH_CCMX51=y
CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
CONFIG_MACH_EMBEDSKY_E9=y
CONFIG_MACH_FREESCALE_MX51_PDK=y
@@ -41,7 +42,6 @@ CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
CONFIG_MACH_FREESCALE_MX7_SABRESD=y
CONFIG_MACH_NXP_IMX6ULL_EVK=y
CONFIG_MACH_GRINN_LITEBOARD=y
-CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cdbaf8189f..9c657ded35 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -21,6 +21,7 @@ pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
pbl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o
+pbl-dtb-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o
pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
diff --git a/arch/arm/dts/imx51-ccxmx51.dts b/arch/arm/dts/imx51-ccxmx51.dts
new file mode 100644
index 0000000000..efe5dbf631
--- /dev/null
+++ b/arch/arm/dts/imx51-ccxmx51.dts
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+#include <arm/imx51-digi-connectcore-jsk.dts>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+
+ environment {
+ compatible = "barebox,environment";
+ device-path = &nfc, "partname:env";
+ };
+ };
+};
+
+&iim {
+ barebox,provide-mac-address = <&fec 1 9>;
+};
+
+&nfc {
+ partition@0 {
+ label = "boot";
+ reg = <0x00000 0x80000>;
+ };
+
+ partition@80000 {
+ label = "env";
+ reg = <0x80000 0x40000>;
+ };
+
+ partition@c0000 {
+ label = "kernel";
+ reg = <0xc0000 0x340000>;
+ };
+
+ partition@400000 {
+ label = "root";
+ reg = <0x400000 0>;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
index 53fdb722d0..5c43b16ab1 100644
--- a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi
@@ -32,6 +32,9 @@
reg = <0x0 0xe0000>;
};
+ /delete-node/ partition@c0000;
+ /delete-node/ partition@c2000;
+
partition@e0000 {
label = "barebox-environment";
reg = <0xe0000 0x20000>;
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 56a35173a0..9593c555f9 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -6,16 +6,11 @@
/dts-v1/;
+#include <arm64/freescale/imx8mq-evk.dts>
#include "imx8mq.dtsi"
-#include "imx8mq-ddrc.dtsi"
/ {
- model = "NXP i.MX8MQ EVK";
- compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
-
chosen {
- stdout-path = &uart1;
-
environment-emmc {
compatible = "barebox,environment";
device-path = &usdhc1, "partname:barebox-environment";
@@ -27,168 +22,9 @@
status = "disabled";
};
};
-
- reg_usdhc2_vmmc: regulator-vsd-3v3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2>;
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&dcss {
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1_mdc>, <&pinctrl_fec1_mdio>,
- <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
- <&pinctrl_fec1_phy_reset>;
- phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&hdmi {
- status ="okay";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@8 {
- compatible = "fsl,pfuze100";
- reg = <0x8>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw3a_reg: sw3ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <975000>;
- regulator-always-on;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1675000>;
- regulator-max-microvolt = <1975000>;
- regulator-always-on;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1625000>;
- regulator-max-microvolt = <1875000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3625000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
-};
-
-&ocotp {
- barebox,provide-mac-address = <&fec1 0x640>;
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- status = "okay";
- dr_mode = "host";
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
- <&pinctrl_usdhc1_data>;
- pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
- <&pinctrl_usdhc1_clk_strobe_100mhz>,
- <&pinctrl_usdhc1_data_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
- <&pinctrl_usdhc1_clk_strobe_200mhz>,
- <&pinctrl_usdhc1_data_200mhz>;
- vqmmc-supply = <&sw4_reg>;
- bus-width = <8>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
-
#address-cells = <1>;
#size-cells = <1>;
@@ -204,17 +40,6 @@
};
&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk>,
- <&pinctrl_usdhc2_data>;
- pinctrl-1 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_100mhz>,
- <&pinctrl_usdhc2_data_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_200mhz>,
- <&pinctrl_usdhc2_data_200mhz>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_usdhc2_vmmc>;
- status = "okay";
-
#address-cells = <1>;
#size-cells = <1>;
@@ -229,250 +54,6 @@
};
};
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1_mdc: fec1mdcgrp {
- pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
- drive-strength = <3>;
- slew-rate = <0>;
- };
-
- pinctrl_fec1_mdio: fec1mdiogrp {
- pinmux = <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO>;
- drive-strength = <3>;
- slew-rate = <0>;
- drive-open-drain;
- };
-
- pinctrl_fec1_phy_reset: fec1phyresetgrp {
- pinmux = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9>;
- drive-strength = <1>;
- slew-rate = <0>;
- };
-
- pinctrl_fec1_data_tx: fec1datatxgrp {
- pinmux = <
- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
- >;
- drive-strength = <7>;
- slew-rate = <3>;
- };
-
- pinctrl_fec1_data_rx: fec1datarxgrp {
- pinmux = <
- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
- >;
- drive-strength = <1>;
- slew-rate = <2>;
- input-schmitt-enable;
- };
-
- pinctrl_i2c1: i2c1grp {
- pinmux = <
- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
- >;
- drive-strength = <7>;
- slew-rate = <0>;
- drive-open-drain;
- input-enable;
- };
-
- pinctrl_reg_usdhc2: regusdhc2grpgpio {
- pinmux = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19>;
- drive-strength = <1>;
- slew-rate = <0>;
- bias-pull-up;
- };
-
- pinctrl_uart1: uart1grp {
- pinmux = <
- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
- >;
- drive-strength = <1>;
- slew-rate = <0>;
- bias-pull-up;
- };
-
- pinctrl_usdhc1_cd_reset: usdhc1cdgrp {
- pinmux = <
- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
- >;
- drive-strength = <1>;
- slew-rate = <0>;
- bias-pull-up;
- };
-
- pinctrl_usdhc1_clk_strobe: usdhc1clkgrp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
- >;
- drive-strength = <3>;
- slew-rate = <0>;
- };
-
- pinctrl_usdhc1_data: usdhc1datagrp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
- >;
- drive-strength = <3>;
- slew-rate = <0>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_usdhc1_clk_strobe_100mhz: usdhc1clk100grp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
- >;
- drive-strength = <3>;
- slew-rate = <0>;
- };
-
- pinctrl_usdhc1_data_100mhz: usdhc1data100grp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
- >;
- drive-strength = <5>;
- slew-rate = <1>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_usdhc1_clk_strobe_200mhz: usdhc1clk200grp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
- >;
- drive-strength = <7>;
- slew-rate = <3>;
- };
-
- pinctrl_usdhc1_data_200mhz: usdhc1data200grp {
- pinmux = <
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
- >;
- drive-strength = <7>;
- slew-rate = <3>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_usdhc2_vselect: usdhc2vselectgrp {
- pinmux = <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT>;
- drive-strength = <1>;
- slew-rate = <0>;
- bias-pull-up;
- };
-
- pinctrl_usdhc2_clk: usdhc2clkgrp {
- pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
- drive-strength = <3>;
- slew-rate = <0>;
- };
-
- pinctrl_usdhc2_data: usdhc2datagrp {
- pinmux = <
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
- >;
- drive-strength = <3>;
- slew-rate = <0>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_usdhc2_clk_100mhz: usdhc2clk100grp {
- pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
- drive-strength = <5>;
- slew-rate = <1>;
- };
-
- pinctrl_usdhc2_data_100mhz: usdhc2data100grp {
- pinmux = <
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
- >;
- drive-strength = <5>;
- slew-rate = <1>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_usdhc2_clk_200mhz: usdhc2clk200grp {
- pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
- drive-strength = <7>;
- slew-rate = <3>;
- };
-
- pinctrl_usdhc2_data_200mhz: usdhc2data200grp {
- pinmux = <
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
- >;
- drive-strength = <7>;
- slew-rate = <3>;
- bias-pull-up;
- input-schmitt-enable;
- };
-
- pinctrl_wdog: wdoggrp {
- pinmux = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;
- drive-strength = <6>;
- slew-rate = <0>;
- bias-pull-up;
- };
-};
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x640>;
+}; \ No newline at end of file
diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h
deleted file mode 100644
index b94b02080a..0000000000
--- a/arch/arm/dts/imx8mq-pinfunc.h
+++ /dev/null
@@ -1,623 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- */
-
-#ifndef __DTS_IMX8MQ_PINFUNC_H
-#define __DTS_IMX8MQ_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
-#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
-#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
-#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
-#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
-
-#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index f89bee200e..1ddb51f898 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -4,31 +4,10 @@
* Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
-#include <dt-bindings/clock/imx8mq-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
-#include "imx8mq-pinfunc.h"
-
-/* first 128 KiB of memory are owned by ATF */
-/memreserve/ 0x40000000 0x00020000;
/ {
- /* This should really be the GPC, but we need a driver for this first */
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
-
aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- i2c3 = &i2c4;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -36,186 +15,40 @@
gpio4 = &gpio5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
+ spi0 = &ecspi1;
};
- ckil: clk-ckil {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "ckil";
- };
-
- osc_25m: clk-osc-25m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "osc_25m";
- };
-
- osc_27m: clk-osc-27m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- clock-output-names = "osc_27m";
- };
-
- clk_ext1: clk-ext1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext1";
- };
-
- clk_ext2: clk-ext2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext2";
- };
-
- clk_ext3: clk-ext3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext3";
- };
-
- clk_ext4: clk-ext4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency= <133000000>;
- clock-output-names = "clk_ext4";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- A53_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- #cooling-cells = <2>;
- };
-
- A53_1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- };
-
- A53_2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x2>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- };
-
- A53_3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x3>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- };
-
- A53_L2: l2-cache0 {
- compatible = "cache";
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
- interrupt-parent = <&gic>;
- arm,no-tick-in-suspend;
- };
-
- display-subsystem {
- compatible = "fsl,imx-display-subsystem";
- ports = <&dcss_disp0>;
- };
-
- peripherals@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x3e000000>;
-
- bus@30000000 { /* AIPS1 */
- compatible = "fsl,imx8mq-aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30000000 0x30000000 0x400000>;
-
- gpio1: gpio@30200000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30200000 0x10000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@30210000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30210000 0x10000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@30220000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30220000 0x10000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
- gpio4: gpio@30230000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30230000 0x10000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
};
- gpio5: gpio@30240000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30240000 0x10000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
};
+ };
+ };
+ soc@0 {
+ bus@30000000 {
tmu: tmu@30260000 {
compatible = "fsl,imx8mq-tmu";
reg = <0x30260000 0x10000>;
@@ -223,158 +56,61 @@
little-endian;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration = <0x00000000 0x00000023
- 0x00000001 0x00000029
- 0x00000002 0x0000002f
- 0x00000003 0x00000035
- 0x00000004 0x0000003d
- 0x00000005 0x00000043
- 0x00000006 0x0000004b
- 0x00000007 0x00000051
- 0x00000008 0x00000057
- 0x00000009 0x0000005f
- 0x0000000a 0x00000067
- 0x0000000b 0x0000006f
-
- 0x00010000 0x0000001b
- 0x00010001 0x00000023
- 0x00010002 0x0000002b
- 0x00010003 0x00000033
- 0x00010004 0x0000003b
- 0x00010005 0x00000043
- 0x00010006 0x0000004b
- 0x00010007 0x00000055
- 0x00010008 0x0000005d
- 0x00010009 0x00000067
- 0x0001000a 0x00000070
-
- 0x00020000 0x00000017
- 0x00020001 0x00000023
- 0x00020002 0x0000002d
- 0x00020003 0x00000037
- 0x00020004 0x00000041
- 0x00020005 0x0000004b
- 0x00020006 0x00000057
- 0x00020007 0x00000063
- 0x00020008 0x0000006f
-
- 0x00030000 0x00000015
- 0x00030001 0x00000021
- 0x00030002 0x0000002d
- 0x00030003 0x00000039
- 0x00030004 0x00000045
- 0x00030005 0x00000053
- 0x00030006 0x0000005f
- 0x00030007 0x00000071>;
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
#thermal-sensor-cells = <0>;
};
- thermal-zones {
- /* cpu thermal */
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu>;
-
- trips {
- cpu_alert0: trip0 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit0: trip1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device =
- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- iomuxc: iomuxc@30330000 {
- compatible = "fsl,imx8mq-iomuxc";
- reg = <0x30330000 0x10000>;
- };
-
- gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
- reg = <0x30340000 0x10000>;
- };
-
ocotp: ocotp@30350000 {
compatible = "fsl,imx8mq-ocotp";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
};
-
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mq-anatop", "syscon";
- reg = <0x30360000 0x10000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mq-ccm";
- reg = <0x30380000 0x10000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- #clock-cells = <1>;
- clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
- <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "ckil", "osc_25m", "osc_27m",
- "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- };
-
- wdog1: watchdog@30280000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x30280000 0x10000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
- status = "disabled";
- };
-
- wdog2: watchdog@30290000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x30290000 0x10000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
- status = "disabled";
- };
-
- wdog3: watchdog@302a0000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x302a0000 0x10000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
- status = "disabled";
- };
};
- bus@30400000 { /* AIPS2 */
- compatible = "fsl,imx8mq-aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30400000 0x30400000 0x400000>;
- };
-
- bus@30800000 { /* AIPS3 */
- compatible = "fsl,imx8mq-aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30800000 0x30800000 0x400000>;
-
+ bus@30800000 {
ecspi1: ecspi@30820000 {
- compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
@@ -382,370 +118,30 @@
clock-names = "ipg", "per";
status = "disabled";
};
-
- uart1: serial@30860000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
- <&clk IMX8MQ_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart3: serial@30880000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
- <&clk IMX8MQ_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart2: serial@30890000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
- <&clk IMX8MQ_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- i2c1: i2c@30a20000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a20000 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@30a30000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a30000 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@30a40000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a40000 0x10000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@30a50000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a50000 0x10000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart4: serial@30a60000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30a60000 0x10000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
- <&clk IMX8MQ_CLK_UART4_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- usdhc1: usdhc@30b40000 {
- compatible = "fsl,imx8mq-usdhc",
- "fsl,imx7d-usdhc";
- reg = <0x30b40000 0x10000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
- <&clk IMX8MQ_CLK_USDHC1_ROOT>;
- clock-names = "ipg", "ahb", "per";
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc2: usdhc@30b50000 {
- compatible = "fsl,imx8mq-usdhc",
- "fsl,imx7d-usdhc";
- reg = <0x30b50000 0x10000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
- <&clk IMX8MQ_CLK_USDHC2_ROOT>;
- clock-names = "ipg", "ahb", "per";
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- fec1: ethernet@30be0000 {
- compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
- reg = <0x30be0000 0x10000>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
- <&clk IMX8MQ_CLK_ENET1_ROOT>,
- <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
- <&clk IMX8MQ_CLK_ENET_REF_DIV>,
- <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
- clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
- fsl,num-tx-queues = <3>;
- fsl,num-rx-queues = <3>;
- status = "disabled";
- };
- };
-
- bus@32c00000 { /* AIPS4 */
- compatible = "fsl,imx8mq-aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x32c00000 0x32c00000 0x400000>;
-
- hdmi: hdmi@32c00000 {
- compatible = "fsl,imx8mq-hdmi";
- reg = <0x32c00000 0x33800>, /* HDP registers */
- <0x32e40000 0x40000>; /* HDP SEC register */
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "plug_in", "plug_out";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- port@0 {
- reg = <0>;
- hdmi_disp: endpoint {
- remote-endpoint = <&dcss_disp0_hdmi>;
- };
- };
- };
-
- dcss: dcss@32e00000 {
- compatible = "nxp,imx8mq-dcss";
- reg = <0x32e00000 0x30000>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>,
- <4 IRQ_TYPE_LEVEL_HIGH>,
- <5 IRQ_TYPE_LEVEL_HIGH>,
- <6 IRQ_TYPE_LEVEL_HIGH>,
- <8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "dpr_dc_ch0",
- "dpr_dc_ch1",
- "dpr_dc_ch2",
- "ctx_ld",
- "dtg_prg1";
- interrupt-parent = <&irqsteer_dcss>;
- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
- <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
- <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
- <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
- <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
- clock-names = "apb", "axi", "rtrm",
- "pixel", "dtrc";
- assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
- <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
- assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
- <&clk IMX8MQ_SYS1_PLL_800M>,
- <&clk IMX8MQ_SYS1_PLL_800M>;
- assigned-clock-rates = <594000000>,
- <800000000>,
- <400000000>,
- <400000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- dcss_disp0: port@0 {
- reg = <0>;
- dcss_disp0_hdmi: hdmi-endpoint {
- remote-endpoint = <&hdmi_disp>;
- };
- };
- };
-
- irqsteer_dcss: interrupt-controller@32e2d000 {
- compatible = "nxp,imx-irqsteer";
- reg = <0x32e2d000 0x1000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
- clock-names = "ipg";
- nxp,channel = <2>;
- nxp,endian = <1>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- gpu: gpu@38000000 {
- compatible = "vivante,gc";
- reg = <0x38000000 0x40000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
- <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
- <&clk IMX8MQ_CLK_GPU_AXI_DIV>,
- <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
- clock-names = "core", "shader", "bus", "reg";
-
- assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
- <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
- <&clk IMX8MQ_CLK_GPU_AXI_SRC>,
- <&clk IMX8MQ_CLK_GPU_AHB_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>;
- assigned-clock-rates = <800000000>, <800000000>,
- <800000000>, <800000000>;
- //power-domains = <&gpu_pd>;
- };
-
- usb3_0: usb0@38100000 {
- compatible = "fsl,imx8mq-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x38100000 0x38100000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
- clock-names = "usb1_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
- <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- status = "disabled";
-
- usb_dwc3_0: dwc3@38100000 {
- compatible = "snps,dwc3";
- reg = <0x38100000 0x10000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy0 0>, <&usb3_phy0 1>;
- phy-names = "usb2-phy", "usb3-phy";
- //power-domains = <&usb_otg1_pd>;
- snps,power-down-scale = <2>;
- usb3-resume-missing-cas;
- status = "disabled";
- };
- };
-
- usb3_phy0: phy@381f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x381f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
- clock-names = "usb_phy_root_clk";
- #phy-cells = <1>;
-
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
-
- status = "disabled";
- };
-
- usb3_1: usb1@38200000 {
- compatible = "fsl,imx8mq-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x38200000 0x38200000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
- clock-names = "usb2_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
- <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- status = "disabled";
-
- usb_dwc3_1: dwc3@38200000 {
- compatible = "snps,dwc3";
- reg = <0x38200000 0x10000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy1 0>, <&usb3_phy1 1>;
- phy-names = "usb2-phy", "usb3-phy";
- //power-domains = <&usb_otg2_pd>;
- snps,power-down-scale = <2>;
- usb3-resume-missing-cas;
- status = "disabled";
- };
- };
-
- usb3_phy1: phy@382f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x382f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
- clock-names = "usb_phy_root_clk";
- #phy-cells = <1>;
-
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
-
- status = "disabled";
- };
-
- gic: interrupt-controller@38800000 {
- compatible = "arm,gic-v3";
- reg = <0x38800000 0x10000>, /* GIC Dist */
- <0x38880000 0xc0000>, /* GICR */
- <0x31000000 0x2000>, /* GICC */
- <0x31010000 0x2000>, /* GICV */
- <0x31020000 0x2000>; /* GICH */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
};
};
};
-
+&A53_0 {
+ #cooling-cells = <2>;
+};
&clk {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>,
- <&clk IMX8MQ_CLK_USDHC1_DIV>,
- <&clk IMX8MQ_CLK_USDHC2_SRC>,
- <&clk IMX8MQ_CLK_USDHC2_DIV>,
- <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
- <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
- <&clk IMX8MQ_CLK_ENET_REF_SRC>,
- <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
-
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>,
+ <&clk IMX8MQ_CLK_USDHC2>,
+ <&clk IMX8MQ_CLK_ENET_AXI>,
+ <&clk IMX8MQ_CLK_ENET_TIMER>,
+ <&clk IMX8MQ_CLK_ENET_REF>;
+
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_400M>,
- <0>,
<&clk IMX8MQ_SYS1_PLL_400M>,
- <0>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
- <&clk IMX8MQ_SYS2_PLL_125M>,
- <0>;
+ <&clk IMX8MQ_SYS2_PLL_125M>;
- assigned-clock-rates = <400000000>,
- <200000000>,
- <400000000>,
+ assigned-clock-rates = <200000000>,
<200000000>,
<266000000>,
- <0>,
- <125000000>,
- <25000000>;
+ <25000000>,
+ <125000000>;
};
-
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index d9b60053db..44ca27096b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -26,7 +26,6 @@ config ARCH_TEXT_BASE
default 0x93d00000 if MACH_TX25
default 0x7ff00000 if MACH_TQMA53
default 0x97f00000 if MACH_TX51
- default 0x97f00000 if MACH_CCMX51
default 0x4fc00000 if MACH_SABRELITE
default 0x8fe00000 if MACH_TX53
default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK
@@ -246,6 +245,18 @@ config MACH_KINDLE_MX50
Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or
EY21 (Kindle Paperwhite).
+config MACH_CCMX51
+ bool "ConnectCore i.MX51"
+ select ARCH_IMX51
+ select IMX_IIM
+ select SPI
+ select DRIVER_SPI_IMX
+ select MFD_MC13XXX
+ select RELOCATABLE
+ help
+ Say Y here if you are using Digi ConnectCore (W)i-i.MX51
+ equipped with a Freescale i.MX51 Processor
+
config MACH_EFIKA_MX_SMARTBOOK
bool "Efika MX smartbook"
select ARCH_IMX51
@@ -622,25 +633,6 @@ config MACH_TX51
help
Say Y here if you are using the Ka-Ro tx51 board
-config MACH_CCMX51
- bool "ConnectCore i.MX51"
- select ARCH_IMX51
- select IMX_IIM
- select SPI
- select DRIVER_SPI_IMX
- select MFD_MC13XXX
- help
- Say Y here if you are using Digi ConnectCore (W)i-i.MX51
- equipped with a Freescale i.MX51 Processor
-
-config MACH_CCMX51_BASEBOARD
- bool "Digi development board for CCMX51 module"
- depends on MACH_CCMX51
- default y
- help
- This adds board specific devices that can be found on Digi
- evaluation board for CCMX51 module.
-
# ----------------------------------------------------------
comment "i.MX53 Boards"
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index ca11e83456..ff2a828c7d 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -26,6 +26,7 @@ void imx7_init_lowlevel(void)
{
void __iomem *aips1 = IOMEM(MX7_AIPS1_CONFIG_BASE_ADDR);
void __iomem *aips2 = IOMEM(MX7_AIPS2_CONFIG_BASE_ADDR);
+ void __iomem *aips3 = IOMEM(MX7_AIPS3_CONFIG_BASE_ADDR);
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -46,6 +47,14 @@ void imx7_init_lowlevel(void)
writel(0, aips2 + 0x48);
writel(0, aips2 + 0x4c);
writel(0, aips2 + 0x50);
+
+ writel(0x77777777, aips3);
+ writel(0x77777777, aips3 + 0x4);
+ writel(0, aips3 + 0x40);
+ writel(0, aips3 + 0x44);
+ writel(0, aips3 + 0x48);
+ writel(0, aips3 + 0x4c);
+ writel(0, aips3 + 0x50);
}
#define SC_CNTCR 0x0
diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c
index 8c276a43c0..a29a1bf91a 100644
--- a/common/imx-bbu-nand-fcb.c
+++ b/common/imx-bbu-nand-fcb.c
@@ -1198,9 +1198,8 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat
int ret, i;
struct fcb_block *fcb = NULL;
void *fw = NULL, *fw_orig = NULL;
- unsigned fw_size, partition_size;
enum filetype filetype;
- unsigned num_blocks_fw;
+ unsigned num_blocks_fw, fw_size;
int used = 0;
int fw_orig_len;
int used_refresh = 0, unused_refresh = 0;
@@ -1222,7 +1221,12 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat
}
mtd = bcb_cdev->mtd;
- partition_size = mtd->size;
+
+ num_blocks_fw = imx_bbu_firmware_max_blocks(mtd);
+ if (num_blocks_fw < 1) {
+ pr_err("Not enough space for firmware\n");
+ return -ENOSPC;
+ }
for (i = 0; i < 4; i++) {
read_fcb(mtd, i, &fcb);
@@ -1329,8 +1333,6 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat
pr_info("Refreshing existing firmware\n");
}
- num_blocks_fw = imx_bbu_firmware_max_blocks(mtd);
-
if (num_blocks_fw * mtd->erasesize < fw_size) {
pr_err("Not enough space for update\n");
return -ENOSPC;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 791e10ea99..7b1bdde1ce 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -20,6 +20,7 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/log2.h>
+#include <asm-generic/div64.h>
#define div_mask(d) ((1 << ((d)->width)) - 1)
@@ -56,17 +57,17 @@ static unsigned int _get_table_div(const struct clk_div_table *table,
return 0;
}
-static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flags, u8 width)
{
- if (divider->flags & CLK_DIVIDER_ONE_BASED)
+ if (flags & CLK_DIVIDER_ONE_BASED)
return val;
- if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
return 1 << val;
- if (divider->table)
- return _get_table_div(divider->table, val);
+ if (table)
+ return _get_table_div(table, val);
return val + 1;
}
-
static unsigned int _get_table_val(const struct clk_div_table *table,
unsigned int div)
{
@@ -89,6 +90,18 @@ static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
return div - 1;
}
+unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width)
+{
+ unsigned int div;
+
+ div = _get_div(table, val, flags, width);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
static unsigned long clk_divider_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
@@ -98,9 +111,10 @@ static unsigned long clk_divider_recalc_rate(struct clk *clk,
val = readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
- div = _get_div(divider, val);
+ div = _get_div(divider->table, val, divider->flags, divider->width);
- return parent_rate / div;
+ return divider_recalc_rate(clk, parent_rate, val, divider->table,
+ divider->flags, divider->width);
}
/*
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 695e19ab54..89240ff794 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -20,16 +20,6 @@
#include <linux/clk.h>
#include <linux/err.h>
-struct clk_gate {
- struct clk clk;
- void __iomem *reg;
- int shift;
- const char *parent;
- unsigned flags;
-};
-
-#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
-
static void clk_gate_endisable(struct clk *clk, int enable)
{
struct clk_gate *gate = container_of(clk, struct clk_gate, clk);
@@ -79,7 +69,7 @@ static int clk_gate_is_enabled(struct clk *clk)
return g->flags & CLK_GATE_INVERTED ? 1 : 0;
}
-static struct clk_ops clk_gate_ops = {
+struct clk_ops clk_gate_ops = {
.set_rate = clk_parent_set_rate,
.round_rate = clk_parent_round_rate,
.enable = clk_gate_enable,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 22e131faae..d5fe640dce 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -20,15 +20,6 @@
#include <linux/clk.h>
#include <linux/err.h>
-struct clk_mux {
- struct clk clk;
- void __iomem *reg;
- int shift;
- int width;
-};
-
-#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
-
static int clk_mux_get_parent(struct clk *clk)
{
struct clk_mux *m = container_of(clk, struct clk_mux, clk);
@@ -53,7 +44,7 @@ static int clk_mux_set_parent(struct clk *clk, u8 idx)
return 0;
}
-static struct clk_ops clk_mux_ops = {
+struct clk_ops clk_mux_ops = {
.set_rate = clk_parent_set_rate,
.round_rate = clk_parent_round_rate,
.get_parent = clk_mux_get_parent,
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 8f441a97e7..97ae97a2a9 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_COMMON_CLK) += \
+ clk-composite-8m.o \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 0000000000..0cd52b5b46
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include "clk.h"
+
+#define PCG_PREDIV_SHIFT 16
+#define PCG_PREDIV_WIDTH 3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT 0
+#define PCG_DIV_WIDTH 6
+#define PCG_DIV_MAX 64
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_WIDTH 3
+
+#define PCG_CGC_SHIFT 28
+
+#define clk_div_mask(width) ((1 << (width)) - 1)
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+ unsigned long prediv_rate;
+ unsigned int prediv_value;
+ unsigned int div_value;
+
+ prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value &= clk_div_mask(divider->width);
+
+ prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+ div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+ return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+ divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+ unsigned long parent_rate,
+ int *prediv, int *postdiv)
+{
+ int div1, div2;
+ int error = INT_MAX;
+ int ret = -EINVAL;
+
+ *prediv = 1;
+ *postdiv = 1;
+
+ for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+ for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+ int new_error = ((parent_rate / div1) / div2) - rate;
+
+ if (abs(new_error) < abs(error)) {
+ *prediv = div1;
+ *postdiv = div2;
+ error = new_error;
+ ret = 0;
+ }
+ }
+ }
+ return ret;
+}
+
+static long imx8m_clk_composite_divider_round_rate(struct clk *clk,
+ unsigned long rate,
+ unsigned long *prate)
+{
+ int prediv_value;
+ int div_value;
+
+ imx8m_clk_composite_compute_dividers(rate, *prate,
+ &prediv_value, &div_value);
+ rate = DIV_ROUND_UP(*prate, prediv_value);
+
+ return DIV_ROUND_UP(rate, div_value);
+
+}
+
+static int imx8m_clk_composite_divider_set_rate(struct clk *clk,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+ int prediv_value;
+ int div_value;
+ int ret;
+ u32 val;
+
+ ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+ &prediv_value, &div_value);
+ if (ret)
+ return -EINVAL;
+
+ val = readl(divider->reg);
+ val &= ~((clk_div_mask(divider->width) << divider->shift) |
+ (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+ val |= (u32)(prediv_value - 1) << divider->shift;
+ val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+ writel(val, divider->reg);
+
+ return ret;
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+ .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
+ .round_rate = imx8m_clk_composite_divider_round_rate,
+ .set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char **parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk *comp = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->width = PCG_PCS_WIDTH;
+ mux->clk.ops = &clk_mux_ops;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg;
+ div->shift = PCG_PREDIV_SHIFT;
+ div->width = PCG_PREDIV_WIDTH;
+ div->clk.ops = &imx8m_clk_composite_divider_ops;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg;
+ gate->shift = PCG_CGC_SHIFT;
+ gate->clk.ops = &clk_gate_ops;
+
+ comp = clk_register_composite(name, parent_names, num_parents,
+ &mux->clk, &div->clk, &gate->clk, flags);
+ if (IS_ERR(comp))
+ goto fail;
+
+ return comp;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(comp);
+}
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c
index f59a41b001..69ac2f5e3e 100644
--- a/drivers/clk/imx/clk-imx5.c
+++ b/drivers/clk/imx/clk-imx5.c
@@ -271,6 +271,7 @@ static void mx5_clocks_mx51_mx53_init(void __iomem *base)
clks[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
clks[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
+ clks[IMX5_CLK_DI_PRED] = imx_clk_divider_np("di_pred", "pll3_sw", base + CCM_CDCDR, 6, 3);
clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
}
@@ -362,6 +363,8 @@ static void mx51_clocks_ipu_init(void __iomem *regs)
mx5_clocks_ipu_init(regs);
+ clk_set_rate(clks[IMX5_CLK_DI_PRED], clk_get_rate(clks[IMX5_CLK_PLL3_SW]));
+
clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 0431f61f09..016d405e90 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -1,25 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2017 NXP.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * Copyright 2018 NXP.
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
-#include <common.h>
-#include <init.h>
-#include <driver.h>
-#include <linux/clk.h>
+#include <dt-bindings/clock/imx8mq-clock.h>
#include <io.h>
-#include <of.h>
-#include <of_address.h>
-#include <linux/clkdev.h>
+#include <linux/clk.h>
#include <linux/err.h>
-#include <mach/revision.h>
-#include <dt-bindings/clock/imx8mq-clock.h>
+#include <linux/types.h>
+#include <of_address.h>
#include "clk.h"
@@ -37,18 +27,25 @@ static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", };
static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", };
static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", };
static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", };
-static const char *video2_pll1_out_sels[] = {"video2_pll1", "video2_pll1_ref_sel", };
static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", };
static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", };
static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", };
static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", };
-static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref_sel", };
/* CCM ROOT */
static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
+static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
+ "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
+
+static const char *imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
@@ -58,9 +55,25 @@ static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_p
static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
"sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
+static const char *imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
+
+static const char *imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
+
+static const char *imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out",
+ "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
+
+static const char *imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
+ "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
+
static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
"sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+static const char *imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
@@ -70,11 +83,25 @@ static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pl
static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
"sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+static const char *imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
+ "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"};
+
static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
- "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
+ "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
- "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
+
+static const char *imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
+
+static const char *imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
+
+static const char *imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
@@ -89,6 +116,22 @@ static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio
static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+static const char *imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
+
+static const char *imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
+
+static const char *imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m",
"sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
@@ -167,6 +210,36 @@ static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_1
static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
"sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
+static const char *imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
@@ -186,18 +259,19 @@ static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_
static struct clk_onecell_data clk_data;
static int const clks_init_on[] = {
- IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG,
- IMX8MQ_CLK_NOC_DIV, IMX8MQ_CLK_NOC_APB_DIV,
- IMX8MQ_CLK_NAND_USDHC_BUS_SRC,
- IMX8MQ_CLK_MAIN_AXI_SRC, IMX8MQ_CLK_A53_CG,
- IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT,
- IMX8MQ_CLK_DRAM_APB_SRC,
+ IMX8MQ_CLK_A53_CG,
+ IMX8MQ_CLK_DRAM_CORE,
+ IMX8MQ_CLK_TMU_ROOT,
+ IMX8MQ_CLK_MAIN_AXI,
+ IMX8MQ_CLK_NOC,
+ IMX8MQ_CLK_NOC_APB,
+ IMX8MQ_CLK_DRAM_APB
};
-
-static void __init imx8mq_clocks_init(struct device_node *ccm_node)
+static int imx8mq_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
+ int err;
int i;
clks[IMX8MQ_CLK_DUMMY] = clk_fixed("dummy", 0);
@@ -211,7 +285,8 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
base = of_iomap(np, 0);
- WARN_ON(!base);
+ if (WARN_ON(!base))
+ return -ENOMEM;
clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -223,7 +298,6 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
@@ -235,7 +309,6 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3);
clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3);
clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3);
- clks[IMX8MQ_VIDEO2_PLL1_REF_DIV] = imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, 25, 3);
clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28);
clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18);
@@ -247,25 +320,21 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1);
clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1);
clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1);
- clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", "video2_pll1_ref_div", base + 0x5c, SCCG_PLL1);
clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2);
clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2);
clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2);
clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2);
- clks[IMX8MQ_VIDEO2_PLL2] = imx_clk_sccg_pll("video2_pll2", "video2_pll1_out_div", base + 0x54, SCCG_PLL2);
/* PLL divs */
clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6);
clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6);
clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6);
clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6);
- clks[IMX8MQ_VIDEO2_PLL1_OUT_DIV] = imx_clk_divider("video2_pll1_out_div", "video2_pll1_out", base + 0x5c, 19, 6);
clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6);
clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6);
clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6);
clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6);
- clks[IMX8MQ_VIDEO2_PLL2_DIV] = imx_clk_divider("video2_pll2_div", "video2_pll2", base + 0x5c, 1, 6);
/* PLL bypass out */
clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels));
@@ -279,21 +348,10 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels));
clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels));
clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels));
- clks[IMX8MQ_VIDEO2_PLL1_OUT] = imx_clk_mux("video2_pll1_out", base + 0x54, 5, 1, video2_pll1_out_sels, ARRAY_SIZE(video2_pll1_out_sels));
clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels));
clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels));
clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels));
clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels));
- clks[IMX8MQ_VIDEO2_PLL2_OUT] = imx_clk_mux("video2_pll2_out", base + 0x54, 4, 1, video2_pll2_out_sels, ARRAY_SIZE(video2_pll2_out_sels));
-
- /* unbypass all the plls */
- clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]);
- clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]);
- clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]);
- clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]);
- clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);
- clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]);
- clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]);
/* PLL OUT GATE */
clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21);
@@ -306,7 +364,6 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9);
clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9);
clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9);
- clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_gate("video2_pll_out", "video2_pll2_out", base + 0x54, 9);
/* SYS PLL fixed output */
clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
@@ -331,251 +388,172 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
np = ccm_node;
base = of_iomap(np, 0);
- WARN_ON(!base);
+ if (WARN_ON(!base))
+ return -ENOMEM;
+
/* CORE */
clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
+ clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
+ clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
+ clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels));
clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
+ clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
+ clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
+ clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
+
clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
+ clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
+ clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
/* BUS */
- clks[IMX8MQ_CLK_MAIN_AXI_SRC] = imx_clk_mux2("main_axi_src", base + 0x8800, 24, 3, imx8mq_main_axi_sels, ARRAY_SIZE(imx8mq_main_axi_sels));
- clks[IMX8MQ_CLK_ENET_AXI_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8880, 24, 3, imx8mq_enet_axi_sels, ARRAY_SIZE(imx8mq_enet_axi_sels));
- clks[IMX8MQ_CLK_NAND_USDHC_BUS_SRC] = imx_clk_mux2("nand_usdhc_bus_src", base + 0x8900, 24, 3, imx8mq_nand_usdhc_sels, ARRAY_SIZE(imx8mq_nand_usdhc_sels));
- clks[IMX8MQ_CLK_USB_BUS_SRC] = imx_clk_mux2("usb_bus_src", base + 0x8b80, 24, 3, imx8mq_usb_bus_sels, ARRAY_SIZE(imx8mq_usb_bus_sels));
- clks[IMX8MQ_CLK_NOC_SRC] = imx_clk_mux2("noc_src", base + 0x8d00, 24, 3, imx8mq_noc_sels, ARRAY_SIZE(imx8mq_noc_sels));
- clks[IMX8MQ_CLK_NOC_APB_SRC] = imx_clk_mux2("noc_apb_src", base + 0x8d80, 24, 3, imx8mq_noc_apb_sels, ARRAY_SIZE(imx8mq_noc_apb_sels));
-
- clks[IMX8MQ_CLK_MAIN_AXI_CG] = imx_clk_gate3("main_axi_cg", "main_axi_src", base + 0x8800, 28);
- clks[IMX8MQ_CLK_ENET_AXI_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8880, 28);
- clks[IMX8MQ_CLK_NAND_USDHC_BUS_CG] = imx_clk_gate3("nand_usdhc_bus_cg", "nand_usdhc_bus_src", base + 0x8900, 28);
- clks[IMX8MQ_CLK_USB_BUS_CG] = imx_clk_gate3("usb_bus_cg", "usb_bus_src", base + 0x8b80, 28);
- clks[IMX8MQ_CLK_NOC_CG] = imx_clk_gate3("noc_cg", "noc_src", base + 0x8d00, 28);
- clks[IMX8MQ_CLK_NOC_APB_CG] = imx_clk_gate3("noc_apb_cg", "noc_apb_src", base + 0x8d80, 28);
-
- clks[IMX8MQ_CLK_MAIN_AXI_PRE_DIV] = imx_clk_divider2("main_axi_pre_div", "main_axi_cg", base + 0x8800, 16, 3);
- clks[IMX8MQ_CLK_ENET_AXI_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8880, 16, 3);
- clks[IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV] = imx_clk_divider2("nand_usdhc_bus_pre_div", "nand_usdhc_bus_cg", base + 0x8900, 16, 3);
- clks[IMX8MQ_CLK_DISP_AXI_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8a00, 16, 3);
- clks[IMX8MQ_CLK_DISP_APB_PRE_DIV] = imx_clk_divider2("disp_apb_pre_div", "disp_apb_cg", base + 0x8a80, 16, 3);
- clks[IMX8MQ_CLK_DISP_RTRM_PRE_DIV] = imx_clk_divider2("disp_rtrm_pre_div", "disp_rtrm_cg", base + 0x8b00, 16, 3);
- clks[IMX8MQ_CLK_USB_BUS_PRE_DIV] = imx_clk_divider2("usb_bus_pre_div", "usb_bus_cg", base + 0x8b80, 16, 3);
- clks[IMX8MQ_CLK_GPU_AXI_PRE_DIV] = imx_clk_divider2("gpu_axi_pre_div", "gpu_axi_cg", base + 0x8c00, 16, 3);
- clks[IMX8MQ_CLK_GPU_AHB_PRE_DIV] = imx_clk_divider2("gpu_ahb_pre_div", "gpu_ahb_cg", base + 0x8c80, 16, 3);
- clks[IMX8MQ_CLK_NOC_PRE_DIV] = imx_clk_divider2("noc_pre_div", "noc_cg", base + 0x8d00, 16, 3);
- clks[IMX8MQ_CLK_NOC_APB_PRE_DIV] = imx_clk_divider2("noc_apb_pre_div", "noc_apb_cg", base + 0x8d80, 16, 3);
-
- clks[IMX8MQ_CLK_MAIN_AXI_DIV] = imx_clk_divider2("main_axi_div", "main_axi_pre_div", base + 0x8800, 0, 6);
- clks[IMX8MQ_CLK_ENET_AXI_DIV] = imx_clk_divider2("enet_axi_div", "enet_axi_pre_div", base + 0x8880, 0, 6);
- clks[IMX8MQ_CLK_NAND_USDHC_BUS_DIV] = imx_clk_divider2("nand_usdhc_bus_div", "nand_usdhc_bus_pre_div", base + 0x8900, 0, 6);
- clks[IMX8MQ_CLK_USB_BUS_DIV] = imx_clk_divider2("usb_bus_div", "usb_bus_pre_div", base + 0x8b80, 0, 6);
- clks[IMX8MQ_CLK_NOC_DIV] = imx_clk_divider2("noc_div", "noc_pre_div", base + 0x8d00, 0, 6);
- clks[IMX8MQ_CLK_NOC_APB_DIV] = imx_clk_divider2("noc_apb_div", "noc_apb_pre_div", base + 0x8d80, 0, 6);
+ clks[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_composite("main_axi", imx8mq_main_axi_sels, base + 0x8800);
+ clks[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
+ clks[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
+ clks[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
+ clks[IMX8MQ_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
+ clks[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
+ clks[IMX8MQ_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
+ clks[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
+ clks[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
+ clks[IMX8MQ_CLK_NOC] = imx8m_clk_composite("noc", imx8mq_noc_sels, base + 0x8d00);
+ clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
/* AHB */
- clks[IMX8MQ_CLK_AHB_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, imx8mq_ahb_sels, ARRAY_SIZE(imx8mq_ahb_sels));
- clks[IMX8MQ_CLK_AHB_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
- clks[IMX8MQ_CLK_AHB_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
- clks[IMX8MQ_CLK_AHB_DIV] = imx_clk_divider_flags("ahb_div", "ahb_pre_div", base + 0x9000, 0, 6, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000);
+ clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
/* IPG */
- clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_div", base + 0x9080, 0, 1);
+ clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
+ clks[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
/* IP */
- clks[IMX8MQ_CLK_DRAM_ALT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa000, 24, 3, imx8mq_dram_alt_sels, ARRAY_SIZE(imx8mq_dram_alt_sels));
clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels));
- clks[IMX8MQ_CLK_DRAM_APB_SRC] = imx_clk_mux2("dram_apb_src", base + 0xa080, 24, 3, imx8mq_dram_apb_sels, ARRAY_SIZE(imx8mq_dram_apb_sels));
- clks[IMX8MQ_CLK_PCIE1_CTRL_SRC] = imx_clk_mux2("pcie1_ctrl_src", base + 0xa300, 24, 3, imx8mq_pcie1_ctrl_sels, ARRAY_SIZE(imx8mq_pcie1_ctrl_sels));
- clks[IMX8MQ_CLK_PCIE1_PHY_SRC] = imx_clk_mux2("pcie1_phy_src", base + 0xa380, 24, 3, imx8mq_pcie1_phy_sels, ARRAY_SIZE(imx8mq_pcie1_phy_sels));
- clks[IMX8MQ_CLK_PCIE1_AUX_SRC] = imx_clk_mux2("pcie1_aux_src", base + 0xa400, 24, 3, imx8mq_pcie1_aux_sels, ARRAY_SIZE(imx8mq_pcie1_aux_sels));
- clks[IMX8MQ_CLK_DC_PIXEL_SRC] = imx_clk_mux2("dc_pixel_src", base + 0xa480, 24, 3, imx8mq_dc_pixel_sels, ARRAY_SIZE(imx8mq_dc_pixel_sels));
- clks[IMX8MQ_CLK_LCDIF_PIXEL_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa500, 24, 3, imx8mq_lcdif_pixel_sels, ARRAY_SIZE(imx8mq_lcdif_pixel_sels));
- clks[IMX8MQ_CLK_ENET_REF_SRC] = imx_clk_mux2("enet_ref_src", base + 0xa980, 24, 3, imx8mq_enet_ref_sels, ARRAY_SIZE(imx8mq_enet_ref_sels));
- clks[IMX8MQ_CLK_ENET_TIMER_SRC] = imx_clk_mux2("enet_timer_src", base + 0xaa00, 24, 3, imx8mq_enet_timer_sels, ARRAY_SIZE(imx8mq_enet_timer_sels));
- clks[IMX8MQ_CLK_ENET_PHY_REF_SRC] = imx_clk_mux2("enet_phy_src", base + 0xaa80, 24, 3, imx8mq_enet_phy_sels, ARRAY_SIZE(imx8mq_enet_phy_sels));
- clks[IMX8MQ_CLK_NAND_SRC] = imx_clk_mux2("nand_src", base + 0xab00, 24, 3, imx8mq_nand_sels, ARRAY_SIZE(imx8mq_nand_sels));
- clks[IMX8MQ_CLK_QSPI_SRC] = imx_clk_mux2("qspi_src", base + 0xab80, 24, 3, imx8mq_qspi_sels, ARRAY_SIZE(imx8mq_qspi_sels));
- clks[IMX8MQ_CLK_USDHC1_SRC] = imx_clk_mux2("usdhc1_src", base + 0xac00, 24, 3, imx8mq_usdhc1_sels, ARRAY_SIZE(imx8mq_usdhc1_sels));
- clks[IMX8MQ_CLK_USDHC2_SRC] = imx_clk_mux2("usdhc2_src", base + 0xac80, 24, 3, imx8mq_usdhc2_sels, ARRAY_SIZE(imx8mq_usdhc2_sels));
- clks[IMX8MQ_CLK_I2C1_SRC] = imx_clk_mux2("i2c1_src", base + 0xad00, 24, 3, imx8mq_i2c1_sels, ARRAY_SIZE(imx8mq_i2c1_sels));
- clks[IMX8MQ_CLK_I2C2_SRC] = imx_clk_mux2("i2c2_src", base + 0xad80, 24, 3, imx8mq_i2c2_sels, ARRAY_SIZE(imx8mq_i2c2_sels));
- clks[IMX8MQ_CLK_I2C3_SRC] = imx_clk_mux2("i2c3_src", base + 0xae00, 24, 3, imx8mq_i2c3_sels, ARRAY_SIZE(imx8mq_i2c3_sels));
- clks[IMX8MQ_CLK_I2C4_SRC] = imx_clk_mux2("i2c4_src", base + 0xae80, 24, 3, imx8mq_i2c4_sels, ARRAY_SIZE(imx8mq_i2c4_sels));
- clks[IMX8MQ_CLK_UART1_SRC] = imx_clk_mux2("uart1_src", base + 0xaf00, 24, 3, imx8mq_uart1_sels, ARRAY_SIZE(imx8mq_uart1_sels));
- clks[IMX8MQ_CLK_UART2_SRC] = imx_clk_mux2("uart2_src", base + 0xaf80, 24, 3, imx8mq_uart2_sels, ARRAY_SIZE(imx8mq_uart2_sels));
- clks[IMX8MQ_CLK_UART3_SRC] = imx_clk_mux2("uart3_src", base + 0xb000, 24, 3, imx8mq_uart3_sels, ARRAY_SIZE(imx8mq_uart3_sels));
- clks[IMX8MQ_CLK_UART4_SRC] = imx_clk_mux2("uart4_src", base + 0xb080, 24, 3, imx8mq_uart4_sels, ARRAY_SIZE(imx8mq_uart4_sels));
- clks[IMX8MQ_CLK_USB_CORE_REF_SRC] = imx_clk_mux2("usb_core_ref_src", base + 0xb100, 24, 3, imx8mq_usb_core_sels, ARRAY_SIZE(imx8mq_usb_core_sels));
- clks[IMX8MQ_CLK_USB_PHY_REF_SRC] = imx_clk_mux2("usb_phy_ref_src", base + 0xb180, 24, 3, imx8mq_usb_phy_sels, ARRAY_SIZE(imx8mq_usb_phy_sels));
- clks[IMX8MQ_CLK_ECSPI1_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb280, 24, 3, imx8mq_ecspi1_sels, ARRAY_SIZE(imx8mq_ecspi1_sels));
- clks[IMX8MQ_CLK_ECSPI2_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb300, 24, 3, imx8mq_ecspi2_sels, ARRAY_SIZE(imx8mq_ecspi2_sels));
- clks[IMX8MQ_CLK_PWM1_SRC] = imx_clk_mux2("pwm1_src", base + 0xb380, 24, 3, imx8mq_pwm1_sels, ARRAY_SIZE(imx8mq_pwm1_sels));
- clks[IMX8MQ_CLK_PWM2_SRC] = imx_clk_mux2("pwm2_src", base + 0xb400, 24, 3, imx8mq_pwm2_sels, ARRAY_SIZE(imx8mq_pwm2_sels));
- clks[IMX8MQ_CLK_PWM3_SRC] = imx_clk_mux2("pwm3_src", base + 0xb480, 24, 3, imx8mq_pwm3_sels, ARRAY_SIZE(imx8mq_pwm3_sels));
- clks[IMX8MQ_CLK_PWM4_SRC] = imx_clk_mux2("pwm4_src", base + 0xb500, 24, 3, imx8mq_pwm4_sels, ARRAY_SIZE(imx8mq_pwm4_sels));
- clks[IMX8MQ_CLK_GPT1_SRC] = imx_clk_mux2("gpt1_src", base + 0xb580, 24, 3, imx8mq_gpt1_sels, ARRAY_SIZE(imx8mq_gpt1_sels));
- clks[IMX8MQ_CLK_WDOG_SRC] = imx_clk_mux2("wdog_src", base + 0xb900, 24, 3, imx8mq_wdog_sels, ARRAY_SIZE(imx8mq_wdog_sels));
- clks[IMX8MQ_CLK_WRCLK_SRC] = imx_clk_mux2("wrclk_src", base + 0xb980, 24, 3, imx8mq_wrclk_sels, ARRAY_SIZE(imx8mq_wrclk_sels));
- clks[IMX8MQ_CLK_CLKO2_SRC] = imx_clk_mux2("clko2_src", base + 0xba80, 24, 3, imx8mq_clko2_sels, ARRAY_SIZE(imx8mq_clko2_sels));
- clks[IMX8MQ_CLK_PCIE2_CTRL_SRC] = imx_clk_mux2("pcie2_ctrl_src", base + 0xc000, 24, 3, imx8mq_pcie2_ctrl_sels, ARRAY_SIZE(imx8mq_pcie2_ctrl_sels));
- clks[IMX8MQ_CLK_PCIE2_PHY_SRC] = imx_clk_mux2("pcie2_phy_src", base + 0xc080, 24, 3, imx8mq_pcie2_phy_sels, ARRAY_SIZE(imx8mq_pcie2_phy_sels));
- clks[IMX8MQ_CLK_PCIE2_AUX_SRC] = imx_clk_mux2("pcie2_aux_src", base + 0xc100, 24, 3, imx8mq_pcie2_aux_sels, ARRAY_SIZE(imx8mq_pcie2_aux_sels));
- clks[IMX8MQ_CLK_ECSPI3_SRC] = imx_clk_mux2("ecspi3_src", base + 0xc180, 24, 3, imx8mq_ecspi3_sels, ARRAY_SIZE(imx8mq_ecspi3_sels));
-
- clks[IMX8MQ_CLK_DRAM_ALT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa000, 28);
- clks[IMX8MQ_CLK_DRAM_APB_CG] = imx_clk_gate3("dram_apb_cg", "dram_apb_src", base + 0xa080, 28);
- clks[IMX8MQ_CLK_PCIE1_CTRL_CG] = imx_clk_gate3("pcie1_ctrl_cg", "pcie1_ctrl_src", base + 0xa300, 28);
- clks[IMX8MQ_CLK_PCIE1_PHY_CG] = imx_clk_gate3("pcie1_phy_cg", "pcie1_phy_src", base + 0xa380, 28);
- clks[IMX8MQ_CLK_PCIE1_AUX_CG] = imx_clk_gate3("pcie1_aux_cg", "pcie1_aux_src", base + 0xa400, 28);
- clks[IMX8MQ_CLK_ENET_REF_CG] = imx_clk_gate3("enet_ref_cg", "enet_ref_src", base + 0xa980, 28);
- clks[IMX8MQ_CLK_ENET_TIMER_CG] = imx_clk_gate3("enet_timer_cg", "enet_timer_src", base + 0xaa00, 28);
- clks[IMX8MQ_CLK_ENET_PHY_REF_CG] = imx_clk_gate3("enet_phy_cg", "enet_phy_src", base + 0xaa80, 28);
- clks[IMX8MQ_CLK_NAND_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xab00, 28);
- clks[IMX8MQ_CLK_QSPI_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xab80, 28);
- clks[IMX8MQ_CLK_USDHC1_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xac00, 28);
- clks[IMX8MQ_CLK_USDHC2_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xac80, 28);
- clks[IMX8MQ_CLK_I2C1_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad00, 28);
- clks[IMX8MQ_CLK_I2C2_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xad80, 28);
- clks[IMX8MQ_CLK_I2C3_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae00, 28);
- clks[IMX8MQ_CLK_I2C4_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xae80, 28);
- clks[IMX8MQ_CLK_UART1_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf00, 28);
- clks[IMX8MQ_CLK_UART2_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xaf80, 28);
- clks[IMX8MQ_CLK_UART3_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb000, 28);
- clks[IMX8MQ_CLK_UART4_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb080, 28);
- clks[IMX8MQ_CLK_USB_CORE_REF_CG] = imx_clk_gate3("usb_core_ref_cg", "usb_core_ref_src", base + 0xb100, 28);
- clks[IMX8MQ_CLK_USB_PHY_REF_CG] = imx_clk_gate3("usb_phy_ref_cg", "usb_phy_ref_src", base + 0xb180, 28);
- clks[IMX8MQ_CLK_ECSPI1_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src", base + 0xb280, 28);
- clks[IMX8MQ_CLK_ECSPI2_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb300, 28);
- clks[IMX8MQ_CLK_PWM1_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb380, 28);
- clks[IMX8MQ_CLK_PWM2_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb400, 28);
- clks[IMX8MQ_CLK_PWM3_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb480, 28);
- clks[IMX8MQ_CLK_PWM4_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb500, 28);
- clks[IMX8MQ_CLK_GPT1_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb580, 28);
- clks[IMX8MQ_CLK_WDOG_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xb900, 28);
- clks[IMX8MQ_CLK_WRCLK_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xb980, 28);
- clks[IMX8MQ_CLK_CLKO2_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xba80, 28);
- clks[IMX8MQ_CLK_PCIE2_CTRL_CG] = imx_clk_gate3("pcie2_ctrl_cg", "pcie2_ctrl_src", base + 0xc000, 28);
- clks[IMX8MQ_CLK_PCIE2_PHY_CG] = imx_clk_gate3("pcie2_phy_cg", "pcie2_phy_src", base + 0xc080, 28);
- clks[IMX8MQ_CLK_PCIE2_AUX_CG] = imx_clk_gate3("pcie2_aux_cg", "pcie2_aux_src", base + 0xc100, 28);
- clks[IMX8MQ_CLK_ECSPI3_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xc180, 28);
-
- clks[IMX8MQ_CLK_DRAM_ALT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa000, 16, 3);
- clks[IMX8MQ_CLK_DRAM_APB_PRE_DIV] = imx_clk_divider_flags("dram_apb_pre_div", "dram_apb_cg", base + 0xa080, 16, 3, CLK_OPS_PARENT_ENABLE);
- clks[IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV] = imx_clk_divider2("pcie1_ctrl_pre_div", "pcie1_ctrl_cg", base + 0xa300, 16, 3);
- clks[IMX8MQ_CLK_PCIE1_PHY_PRE_DIV] = imx_clk_divider2("pcie1_phy_pre_div", "pcie1_phy_cg", base + 0xa380, 16, 3);
- clks[IMX8MQ_CLK_PCIE1_AUX_PRE_DIV] = imx_clk_divider2("pcie1_aux_pre_div", "pcie1_aux_cg", base + 0xa400, 16, 3);
- clks[IMX8MQ_CLK_DC_PIXEL_PRE_DIV] = imx_clk_divider2("dc_pixel_pre_div", "dc_pixel_cg", base + 0xa480, 16, 3);
- clks[IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa500, 16, 3);
- clks[IMX8MQ_CLK_SPDIF1_PRE_DIV] = imx_clk_divider2("spdif1_pre_div", "spdif1_cg", base + 0xa880, 16, 3);
- clks[IMX8MQ_CLK_SPDIF2_PRE_DIV] = imx_clk_divider2("spdif2_pre_div", "spdif2_cg", base + 0xa900, 16, 3);
- clks[IMX8MQ_CLK_ENET_REF_PRE_DIV] = imx_clk_divider2("enet_ref_pre_div", "enet_ref_cg", base + 0xa980, 16, 3);
- clks[IMX8MQ_CLK_ENET_TIMER_PRE_DIV] = imx_clk_divider2("enet_timer_pre_div", "enet_timer_cg", base + 0xaa00, 16, 3);
- clks[IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV] = imx_clk_divider2("enet_phy_pre_div", "enet_phy_cg", base + 0xaa80, 16, 3);
- clks[IMX8MQ_CLK_NAND_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xab00, 16, 3);
- clks[IMX8MQ_CLK_QSPI_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xab80, 16, 3);
- clks[IMX8MQ_CLK_USDHC1_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xac00, 16, 3);
- clks[IMX8MQ_CLK_USDHC2_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xac80, 16, 3);
- clks[IMX8MQ_CLK_I2C1_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad00, 16, 3);
- clks[IMX8MQ_CLK_I2C2_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xad80, 16, 3);
- clks[IMX8MQ_CLK_I2C3_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae00, 16, 3);
- clks[IMX8MQ_CLK_I2C4_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xae80, 16, 3);
- clks[IMX8MQ_CLK_UART1_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf00, 16, 3);
- clks[IMX8MQ_CLK_UART2_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xaf80, 16, 3);
- clks[IMX8MQ_CLK_UART3_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb000, 16, 3);
- clks[IMX8MQ_CLK_UART4_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb080, 16, 3);
- clks[IMX8MQ_CLK_USB_CORE_REF_PRE_DIV] = imx_clk_divider2("usb_core_ref_pre_div", "usb_core_ref_cg", base + 0xb100, 16, 3);
- clks[IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = imx_clk_divider2("usb_phy_ref_pre_div", "usb_phy_ref_cg", base + 0xb180, 16, 3);
- clks[IMX8MQ_CLK_ECSPI1_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb280, 16, 3);
- clks[IMX8MQ_CLK_ECSPI2_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb300, 16, 3);
- clks[IMX8MQ_CLK_PWM1_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb380, 16, 3);
- clks[IMX8MQ_CLK_PWM2_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb400, 16, 3);
- clks[IMX8MQ_CLK_PWM3_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb480, 16, 3);
- clks[IMX8MQ_CLK_PWM4_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb500, 16, 3);
- clks[IMX8MQ_CLK_GPT1_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb580, 16, 3);
- clks[IMX8MQ_CLK_WDOG_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xb900, 16, 3);
- clks[IMX8MQ_CLK_WRCLK_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xb980, 16, 3);
- clks[IMX8MQ_CLK_CLKO2_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xba80, 16, 3);
- clks[IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = imx_clk_divider2("pcie2_ctrl_pre_div", "pcie2_ctrl_cg", base + 0xc000, 16, 3);
- clks[IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = imx_clk_divider2("pcie2_phy_pre_div", "pcie2_phy_cg", base + 0xc080, 16, 3);
- clks[IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = imx_clk_divider2("pcie2_aux_pre_div", "pcie2_aux_cg", base + 0xc100, 16, 3);
- clks[IMX8MQ_CLK_ECSPI3_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xc180, 16, 3);
-
- clks[IMX8MQ_CLK_DRAM_ALT_DIV] = imx_clk_divider2("dram_alt_div", "dram_alt_pre_div", base + 0xa000, 0, 6);
- clks[IMX8MQ_CLK_DRAM_APB_DIV] = imx_clk_divider2("dram_apb_div", "dram_apb_pre_div", base + 0xa080, 0, 6);
- clks[IMX8MQ_CLK_PCIE1_CTRL_DIV] = imx_clk_divider2("pcie1_ctrl_div", "pcie1_ctrl_pre_div", base + 0xa300, 0, 6);
- clks[IMX8MQ_CLK_PCIE1_PHY_DIV] = imx_clk_divider2("pcie1_phy_div", "pcie1_phy_pre_div", base + 0xa380, 0, 6);
- clks[IMX8MQ_CLK_PCIE1_AUX_DIV] = imx_clk_divider2("pcie1_aux_div", "pcie1_aux_pre_div", base + 0xa400, 0, 6);
- clks[IMX8MQ_CLK_DC_PIXEL_DIV] = imx_clk_divider2("dc_pixel_div", "dc_pixel_pre_div", base + 0xa480, 0, 6);
- clks[IMX8MQ_CLK_LCDIF_PIXEL_DIV] = imx_clk_divider2("lcdif_pixel_div", "lcdif_pixel_pre_div", base + 0xa500, 0, 6);
- clks[IMX8MQ_CLK_ENET_REF_DIV] = imx_clk_divider2("enet_ref_div", "enet_ref_pre_div", base + 0xa980, 0, 6);
- clks[IMX8MQ_CLK_ENET_TIMER_DIV] = imx_clk_divider2("enet_timer_div", "enet_timer_pre_div", base + 0xaa00, 0, 6);
- clks[IMX8MQ_CLK_ENET_PHY_REF_DIV] = imx_clk_divider2("enet_phy_div", "enet_phy_pre_div", base + 0xaa80, 0, 6);
- clks[IMX8MQ_CLK_NAND_DIV] = imx_clk_divider2("nand_div", "nand_pre_div", base + 0xab00, 0, 6);
- clks[IMX8MQ_CLK_QSPI_DIV] = imx_clk_divider2("qspi_div", "qspi_pre_div", base + 0xab80, 0, 6);
- clks[IMX8MQ_CLK_USDHC1_DIV] = imx_clk_divider2("usdhc1_div", "usdhc1_pre_div", base + 0xac00, 0, 6);
- clks[IMX8MQ_CLK_USDHC2_DIV] = imx_clk_divider2("usdhc2_div", "usdhc2_pre_div", base + 0xac80, 0, 6);
- clks[IMX8MQ_CLK_I2C1_DIV] = imx_clk_divider2("i2c1_div", "i2c1_pre_div", base + 0xad00, 0, 6);
- clks[IMX8MQ_CLK_I2C2_DIV] = imx_clk_divider2("i2c2_div", "i2c2_pre_div", base + 0xad80, 0, 6);
- clks[IMX8MQ_CLK_I2C3_DIV] = imx_clk_divider2("i2c3_div", "i2c3_pre_div", base + 0xae00, 0, 6);
- clks[IMX8MQ_CLK_I2C4_DIV] = imx_clk_divider2("i2c4_div", "i2c4_pre_div", base + 0xae80, 0, 6);
- clks[IMX8MQ_CLK_UART1_DIV] = imx_clk_divider2("uart1_div", "uart1_pre_div", base + 0xaf00, 0, 6);
- clks[IMX8MQ_CLK_UART2_DIV] = imx_clk_divider2("uart2_div", "uart2_pre_div", base + 0xaf80, 0, 6);
- clks[IMX8MQ_CLK_UART3_DIV] = imx_clk_divider2("uart3_div", "uart3_pre_div", base + 0xb000, 0, 6);
- clks[IMX8MQ_CLK_UART4_DIV] = imx_clk_divider2("uart4_div", "uart4_pre_div", base + 0xb080, 0, 6);
- clks[IMX8MQ_CLK_USB_CORE_REF_DIV] = imx_clk_divider2("usb_core_ref_div", "usb_core_ref_pre_div", base + 0xb100, 0, 6);
- clks[IMX8MQ_CLK_USB_PHY_REF_DIV] = imx_clk_divider2("usb_phy_ref_div", "usb_phy_ref_pre_div", base + 0xb180, 0, 6);
- clks[IMX8MQ_CLK_ECSPI1_DIV] = imx_clk_divider2("ecspi1_div", "ecspi1_pre_div", base + 0xb280, 0, 6);
- clks[IMX8MQ_CLK_ECSPI2_DIV] = imx_clk_divider2("ecspi2_div", "ecspi2_pre_div", base + 0xb300, 0, 6);
- clks[IMX8MQ_CLK_PWM1_DIV] = imx_clk_divider2("pwm1_div", "pwm1_pre_div", base + 0xb380, 0, 6);
- clks[IMX8MQ_CLK_PWM2_DIV] = imx_clk_divider2("pwm2_div", "pwm2_pre_div", base + 0xb400, 0, 6);
- clks[IMX8MQ_CLK_PWM3_DIV] = imx_clk_divider2("pwm3_div", "pwm3_pre_div", base + 0xb480, 0, 6);
- clks[IMX8MQ_CLK_PWM4_DIV] = imx_clk_divider2("pwm4_div", "pwm4_pre_div", base + 0xb500, 0, 6);
- clks[IMX8MQ_CLK_GPT1_DIV] = imx_clk_divider2("gpt1_div", "gpt1_pre_div", base + 0xb580, 0, 6);
- clks[IMX8MQ_CLK_WDOG_DIV] = imx_clk_divider2("wdog_div", "wdog_pre_div", base + 0xb900, 0, 6);
- clks[IMX8MQ_CLK_WRCLK_DIV] = imx_clk_divider2("wrclk_div", "wrclk_pre_div", base + 0xb980, 0, 6);
- clks[IMX8MQ_CLK_CLKO2_DIV] = imx_clk_divider2("clko2_div", "clko2_pre_div", base + 0xba80, 0, 6);
- clks[IMX8MQ_CLK_PCIE2_CTRL_DIV] = imx_clk_divider2("pcie2_ctrl_div", "pcie2_ctrl_pre_div", base + 0xc000, 0, 6);
- clks[IMX8MQ_CLK_PCIE2_PHY_DIV] = imx_clk_divider2("pcie2_phy_div", "pcie2_phy_pre_div", base + 0xc080, 0, 6);
- clks[IMX8MQ_CLK_PCIE2_AUX_DIV] = imx_clk_divider2("pcie2_aux_div", "pcie2_aux_pre_div", base + 0xc100, 0, 6);
- clks[IMX8MQ_CLK_ECSPI3_DIV] = imx_clk_divider2("ecspi3_div", "ecspi3_pre_div", base + 0xc180, 0, 6);
-
- /*FIXME, the doc is not ready now */
- clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_div", base + 0x4070, 0);
- clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_div", base + 0x4080, 0);
- clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_div", base + 0x4090, 0);
- clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi_div", base + 0x40a0, 0);
- clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1_div", base + 0x4100, 0);
- clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1_div", base + 0x4170, 0);
- clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2_div", base + 0x4180, 0);
- clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3_div", base + 0x4190, 0);
- clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4_div", base + 0x41a0, 0);
+
+ clks[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);
+ clks[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_composite("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);
+ clks[IMX8MQ_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
+ clks[IMX8MQ_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180);
+ clks[IMX8MQ_CLK_DISP_DTRC] = imx8m_clk_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200);
+ clks[IMX8MQ_CLK_DISP_DC8000] = imx8m_clk_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280);
+ clks[IMX8MQ_CLK_PCIE1_CTRL] = imx8m_clk_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300);
+ clks[IMX8MQ_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380);
+ clks[IMX8MQ_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400);
+ clks[IMX8MQ_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480);
+ clks[IMX8MQ_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500);
+ clks[IMX8MQ_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mq_sai1_sels, base + 0xa580);
+ clks[IMX8MQ_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mq_sai2_sels, base + 0xa600);
+ clks[IMX8MQ_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mq_sai3_sels, base + 0xa680);
+ clks[IMX8MQ_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mq_sai4_sels, base + 0xa700);
+ clks[IMX8MQ_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mq_sai5_sels, base + 0xa780);
+ clks[IMX8MQ_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mq_sai6_sels, base + 0xa800);
+ clks[IMX8MQ_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880);
+ clks[IMX8MQ_CLK_SPDIF2] = imx8m_clk_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900);
+ clks[IMX8MQ_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980);
+ clks[IMX8MQ_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00);
+ clks[IMX8MQ_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80);
+ clks[IMX8MQ_CLK_NAND] = imx8m_clk_composite("nand", imx8mq_nand_sels, base + 0xab00);
+ clks[IMX8MQ_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80);
+ clks[IMX8MQ_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00);
+ clks[IMX8MQ_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80);
+ clks[IMX8MQ_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00);
+ clks[IMX8MQ_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80);
+ clks[IMX8MQ_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00);
+ clks[IMX8MQ_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80);
+ clks[IMX8MQ_CLK_UART1] = imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00);
+ clks[IMX8MQ_CLK_UART2] = imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80);
+ clks[IMX8MQ_CLK_UART3] = imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000);
+ clks[IMX8MQ_CLK_UART4] = imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080);
+ clks[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100);
+ clks[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180);
+ clks[IMX8MQ_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280);
+ clks[IMX8MQ_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300);
+ clks[IMX8MQ_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380);
+ clks[IMX8MQ_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400);
+ clks[IMX8MQ_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480);
+ clks[IMX8MQ_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500);
+ clks[IMX8MQ_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580);
+ clks[IMX8MQ_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900);
+ clks[IMX8MQ_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980);
+ clks[IMX8MQ_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mq_clko2_sels, base + 0xba80);
+ clks[IMX8MQ_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00);
+ clks[IMX8MQ_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80);
+ clks[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
+ clks[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
+ clks[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
+ clks[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
+ clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
+ clks[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
+ clks[IMX8MQ_CLK_CSI2_CORE] = imx8m_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80);
+ clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00);
+ clks[IMX8MQ_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80);
+ clks[IMX8MQ_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000);
+ clks[IMX8MQ_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080);
+ clks[IMX8MQ_CLK_PCIE2_AUX] = imx8m_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100);
+ clks[IMX8MQ_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180);
+
+ clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
+ clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
+ clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
+ clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
+ clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
+ clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
+ clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
+ clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
+ clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
- clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl_div", base + 0x4250, 0);
- clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl_div", base + 0x4640, 0);
- clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1_div", base + 0x4280, 0);
- clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2_div", base + 0x4290, 0);
- clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3_div", base + 0x42a0, 0);
- clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4_div", base + 0x42b0, 0);
- clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi_div", base + 0x42f0, 0);
- clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate4("nand_root_clk", "nand_div", base + 0x4300, 0);
- clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate_shared("nand_usdhc_rawnand_clk", "nand_usdhc_bus_div", "nand_root_clk");
- clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1_div", base + 0x4490, 0);
- clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2_div", base + 0x44a0, 0);
- clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3_div", base + 0x44b0, 0);
- clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4_div", base + 0x44c0, 0);
- clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref_div", base + 0x44d0, 0);
- clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref_div", base + 0x44e0, 0);
- clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref_div", base + 0x44f0, 0);
- clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref_div", base + 0x4500, 0);
- clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_div", base + 0x4510, 0);
- clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_div", base + 0x4520, 0);
- clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog_div", base + 0x4530, 0);
- clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog_div", base + 0x4540, 0);
- clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog_div", base + 0x4550, 0);
+ clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0);
+ clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0);
+ clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
+ clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
+ clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
+ clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
+ clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
+ clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0);
+ clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0);
+ clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0);
+ clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0);
+ clks[IMX8MQ_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0);
+ clks[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0);
+ clks[IMX8MQ_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0);
+ clks[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0);
+ clks[IMX8MQ_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0);
+ clks[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0);
+ clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0);
+ clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0);
+ clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0);
+ clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
+ clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
+ clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
+ clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
+ clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
+ clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0);
+ clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
+ clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
+ clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
+ clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
+ clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
+ clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
+ clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
+ clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0);
+ clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0);
+ clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0);
+ clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0);
+ clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0);
clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
+ clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
+ clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
+ clks[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
+ clks[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
- clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt_div", 1, 4);
+ clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
for (i = 0; i < IMX8MQ_CLK_END; i++)
if (IS_ERR(clks[i]))
@@ -587,7 +565,10 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
+ err = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ WARN_ON(err);
+
+ return err;
+}
CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index c6ec0fc403..945671cbad 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -102,6 +102,13 @@ static inline struct clk *imx_clk_gate2_shared2(const char *name, const char *pa
CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
}
+static inline struct clk *imx_clk_gate2_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift,
+ unsigned long flags)
+{
+ return clk_gate2(name, parent, reg, shift, 0x3, flags);
+}
+
static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 cgr_val)
{
@@ -194,4 +201,16 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char **parent_names, int num_parents, void __iomem *reg,
+ unsigned long flags);
+
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
+ imx8m_clk_composite_flags(name, parent_names, \
+ ARRAY_SIZE(parent_names), reg, \
+ flags | CLK_OPS_PARENT_ENABLE)
+
+#define imx8m_clk_composite(name, parent_names, reg) \
+ __imx8m_clk_composite(name, parent_names, reg, 0)
+
#endif /* __IMX_CLK_H */
diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c
index 469ce4cc0d..b7efb62617 100644
--- a/drivers/mfd/rave-sp.c
+++ b/drivers/mfd/rave-sp.c
@@ -57,6 +57,8 @@
#define RAVE_SP_TX_BUFFER_SIZE \
(RAVE_SP_STX_ETX_SIZE + 2 * RAVE_SP_RX_BUFFER_SIZE)
+#define RAVE_SP_IPADDR_INVALID U32_MAX
+
/**
* enum rave_sp_deframer_state - Possible state for de-framer
*
@@ -183,6 +185,7 @@ struct rave_sp_variant {
* @part_number_bootloader: Bootloader version
*/
struct rave_sp {
+ struct device_d dev;
struct serdev_device *serdev;
struct rave_sp_deframer deframer;
unsigned int ackid;
@@ -192,6 +195,9 @@ struct rave_sp {
const char *part_number_firmware;
const char *part_number_bootloader;
+
+ IPaddr_t ipaddr;
+ IPaddr_t netmask;
};
static bool rave_sp_id_is_event(u8 code)
@@ -718,6 +724,65 @@ static const struct of_device_id __maybe_unused rave_sp_dt_ids[] = {
{ /* sentinel */ }
};
+static int rave_sp_req_ip_addr(struct param_d *p, void *context)
+{
+ struct rave_sp *sp = context;
+ u8 cmd[] = {
+ [0] = RAVE_SP_CMD_REQ_IP_ADDR,
+ [1] = 0,
+ [2] = 0, /* FIXME: Support for RJU? */
+ [3] = 0, /* Add support for IPs other than "self" */
+ };
+ struct {
+ __le32 ipaddr;
+ __le32 netmask;
+ } __packed rsp;
+ int ret;
+
+ /*
+ * We only query RAVE SP device for IP/Netmask once, after
+ * that we just "serve" cached data.
+ */
+ if (sp->ipaddr != RAVE_SP_IPADDR_INVALID)
+ return 0;
+
+ ret = rave_sp_exec(sp, &cmd, sizeof(cmd), &rsp, sizeof(rsp));
+ if (ret < 0)
+ return ret;
+
+ sp->ipaddr = le32_to_cpu(rsp.ipaddr);
+ sp->netmask = le32_to_cpu(rsp.netmask);
+
+ return 0;
+}
+
+static int rave_sp_add_params(struct rave_sp *sp)
+{
+ struct device_d *dev = &sp->dev;
+ struct param_d *p;
+ int ret;
+
+ dev->parent = sp->serdev->dev;
+ dev_set_name(dev, "sp");
+ dev->id = DEVICE_ID_SINGLE;
+
+ ret = register_device(dev);
+ if (ret)
+ return ret;
+
+ p = dev_add_param_ip(dev, "ipaddr", NULL, rave_sp_req_ip_addr,
+ &sp->ipaddr, sp);
+ if (IS_ERR(p))
+ return PTR_ERR(p);
+
+ p = dev_add_param_ip(dev, "netmask", NULL, rave_sp_req_ip_addr,
+ &sp->netmask, sp);
+ if (IS_ERR(p))
+ return PTR_ERR(p);
+
+ return 0;
+}
+
static int rave_sp_probe(struct device_d *dev)
{
struct serdev_device *serdev = to_serdev_device(dev->parent);
@@ -733,6 +798,7 @@ static int rave_sp_probe(struct device_d *dev)
sp = xzalloc(sizeof(*sp));
sp->serdev = serdev;
+ sp->ipaddr = RAVE_SP_IPADDR_INVALID;
dev->priv = sp;
serdev->dev = dev;
serdev->receive_buf = rave_sp_receive_buf;
@@ -773,6 +839,12 @@ static int rave_sp_probe(struct device_d *dev)
dev_info(dev, "Firmware version: %s", sp->part_number_firmware);
dev_info(dev, "Bootloader version: %s", sp->part_number_bootloader);
+ ret = rave_sp_add_params(sp);
+ if (ret) {
+ dev_err(dev, "Failed to add parameters to RAVE SP\n");
+ return ret;
+ }
+
return of_platform_populate(dev->device_node, NULL, dev);
}
diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
index d3cbe502fa..f44c6cfc69 100644
--- a/drivers/mtd/core.c
+++ b/drivers/mtd/core.c
@@ -141,15 +141,28 @@ static struct mtd_erase_region_info *mtd_find_erase_region(struct mtd_info *mtd,
return NULL;
}
+static loff_t __mtd_erase_round(loff_t x, uint32_t esize, int up)
+{
+ uint64_t dividend = x;
+ uint32_t mod = do_div(dividend, esize);
+ if (mod == 0)
+ return x;
+ if (up)
+ x += esize;
+ return x - mod;
+}
+#define mtd_erase_round_up(x, esize) __mtd_erase_round(x, esize, 1)
+#define mtd_erase_round_down(x, esize) __mtd_erase_round(x, esize, 0)
+
static int mtd_erase_align(struct mtd_info *mtd, loff_t *count, loff_t *offset)
{
struct mtd_erase_region_info *e;
loff_t ofs;
if (mtd->numeraseregions == 0) {
- ofs = *offset & ~(loff_t)(mtd->erasesize - 1);
- *count += (*offset - ofs);
- *count = ALIGN(*count, mtd->erasesize);
+ ofs = mtd_erase_round_down(*offset, mtd->erasesize);
+ *count += *offset - ofs;
+ *count = mtd_erase_round_up(*count, mtd->erasesize);
*offset = ofs;
return 0;
}
@@ -158,14 +171,14 @@ static int mtd_erase_align(struct mtd_info *mtd, loff_t *count, loff_t *offset)
if (!e)
return -EINVAL;
- ofs = *offset & ~(e->erasesize - 1);
- *count += (*offset - ofs);
+ ofs = mtd_erase_round_down(*offset, e->erasesize);
+ *count += *offset - ofs;
e = mtd_find_erase_region(mtd, *offset + *count);
if (!e)
return -EINVAL;
- *count = ALIGN(*count, e->erasesize);
+ *count = mtd_erase_round_up(*count, e->erasesize);
*offset = ofs;
return 0;
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index e0cf35f0b7..d904bd08f0 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -446,9 +446,18 @@ static int imx_ocotp_set_mac(struct param_d *param, void *priv)
{
char buf[MAC_BYTES];
struct ocotp_priv_ethaddr *ethaddr = priv;
+ int ret;
- ethaddr->data->format_mac(buf, ethaddr->value,
- OCOTP_MAC_TO_HW);
+ ret = regmap_bulk_read(ethaddr->map, ethaddr->offset, buf, MAC_BYTES);
+ if (ret < 0)
+ return ret;
+
+ if (ethaddr->offset != IMX6UL_MAC_OFFSET_1)
+ ethaddr->data->format_mac(buf, ethaddr->value,
+ OCOTP_MAC_TO_HW);
+ else
+ ethaddr->data->format_mac(buf + 2, ethaddr->value,
+ OCOTP_MAC_TO_HW);
return regmap_bulk_write(ethaddr->map, ethaddr->offset,
buf, MAC_BYTES);
diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c
index b2a67fcccc..5fadc84151 100644
--- a/drivers/pinctrl/imx-iomux-v3.c
+++ b/drivers/pinctrl/imx-iomux-v3.c
@@ -220,9 +220,6 @@ static struct imx_iomux_v3_data imx_iomux_imx7_lpsr_data = {
.flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR,
};
-static struct imx_iomux_v3_data imx_iomux_imx8_data = {
- .flags = SHARE_CONF,
-};
static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
{
@@ -250,7 +247,6 @@ static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
.data = &imx_iomux_imx7_lpsr_data,
}, {
.compatible = "fsl,imx8mq-iomuxc",
- .data = &imx_iomux_imx8_data,
}, {
/* sentinel */
}
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 10621d00c8..46e8955abb 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -605,17 +605,20 @@ static int imx_spi_probe(struct device_d *dev)
master = &imx->master;
master->dev = dev;
- master->bus_num = dev->id;
master->setup = imx_spi_setup;
master->transfer = imx_spi_transfer;
if (pdata) {
+ master->bus_num = dev->id;
master->num_chipselect = pdata->num_chipselect;
imx->cs_array = pdata->chipselect;
- } else {
- if (IS_ENABLED(CONFIG_OFDEVICE))
- imx_spi_dt_probe(imx);
+ } else if (IS_ENABLED(CONFIG_OFDEVICE)) {
+ ret = of_alias_get_id(dev->device_node, "spi");
+ if (ret < 0)
+ goto err_free;
+ master->bus_num = ret;
+ imx_spi_dt_probe(imx);
}
imx->clk = clk_get(dev, NULL);
diff --git a/drivers/video/rave-sp-backlight.c b/drivers/video/rave-sp-backlight.c
index 3a20def661..877a5feeb6 100644
--- a/drivers/video/rave-sp-backlight.c
+++ b/drivers/video/rave-sp-backlight.c
@@ -47,7 +47,7 @@ static int rave_sp_backlight_probe(struct device_d *dev)
bd = xzalloc(sizeof(*bd));
bd->dev.priv = dev->parent->priv;
bd->dev.parent = dev;
- bd->brightness_default = 50;
+ bd->brightness = bd->brightness_cur = bd->brightness_default = 50;
bd->brightness_max = 100;
bd->brightness_set = rave_sp_backlight_set;
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 8b8a5452b7..3d2e352a39 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -32,9 +32,13 @@ CFG_start_imx25_karo_tx25.pblb.imximg = $(board)/karo-tx25/flash-header-tx25.imx
FILE_barebox-karo-tx25-internal.img = start_imx25_karo_tx25.pblb.imximg
image-$(CONFIG_MACH_TX25) += barebox-karo-tx25-internal.img
-pblb-$(CONFIG_MACH_PCA100) += start_phytec_phycard_imx27
-FILE_barebox-phytec-phycard-imx27.img = start_phytec_phycard_imx27.pblb
-image-$(CONFIG_MACH_PCA100) += barebox-phytec-phycard-imx27.img
+pblb-$(CONFIG_MACH_PCA100) += start_phytec_phycard_imx27_64mb
+FILE_barebox-phytec-phycard-imx27-64mb.img = start_phytec_phycard_imx27_64mb.pblb
+image-$(CONFIG_MACH_PCA100) += barebox-phytec-phycard-imx27-64mb.img
+
+pblb-$(CONFIG_MACH_PCA100) += start_phytec_phycard_imx27_128mb
+FILE_barebox-phytec-phycard-imx27-128mb.img = start_phytec_phycard_imx27_128mb.pblb
+image-$(CONFIG_MACH_PCA100) += barebox-phytec-phycard-imx27-128mb.img
pblb-$(CONFIG_MACH_PCM038) += start_phytec_phycore_imx27
FILE_barebox-phytec-phycore-imx27.img = start_phytec_phycore_imx27.pblb
@@ -57,6 +61,11 @@ FILE_barebox-kindle-ey21.img = start_imx50_kindle_ey21.pblb.imximg
image-$(CONFIG_MACH_KINDLE_MX50) += barebox-kindle-ey21.img
# ----------------------- i.MX51 based boards ---------------------------
+pblb-$(CONFIG_MACH_CCMX51) += start_ccxmx51
+CFG_start_ccxmx51.pblb.imximg = $(board)/ccxmx51/flash-header.imxcfg
+FILE_barebox-imx51-ccxmx51.img = start_ccxmx51.pblb.imximg
+image-$(CONFIG_MACH_CCMX51) += barebox-imx51-ccxmx51.img
+
pblb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage
CFG_start_imx51_babbage.pblb.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
FILE_barebox-freescale-imx51-babbage.img = start_imx51_babbage.pblb.imximg
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
deleted file mode 100644
index 7f880629e0..0000000000
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
-#define __DT_BINDINGS_CLOCK_IMX8MQ_H
-
-#define IMX8MQ_CLK_DUMMY 0
-#define IMX8MQ_CLK_32K 1
-#define IMX8MQ_CLK_25M 2
-#define IMX8MQ_CLK_27M 3
-#define IMX8MQ_CLK_EXT1 4
-#define IMX8MQ_CLK_EXT2 5
-#define IMX8MQ_CLK_EXT3 6
-#define IMX8MQ_CLK_EXT4 7
-
-/* ANAMIX PLL clocks */
-/* FRAC PLLs */
-/* ARM PLL */
-#define IMX8MQ_ARM_PLL_REF_SEL 8
-#define IMX8MQ_ARM_PLL_REF_DIV 9
-#define IMX8MQ_ARM_PLL 10
-#define IMX8MQ_ARM_PLL_BYPASS 11
-#define IMX8MQ_ARM_PLL_OUT 12
-
-/* GPU PLL */
-#define IMX8MQ_GPU_PLL_REF_SEL 13
-#define IMX8MQ_GPU_PLL_REF_DIV 14
-#define IMX8MQ_GPU_PLL 15
-#define IMX8MQ_GPU_PLL_BYPASS 16
-#define IMX8MQ_GPU_PLL_OUT 17
-
-/* VPU PLL */
-#define IMX8MQ_VPU_PLL_REF_SEL 18
-#define IMX8MQ_VPU_PLL_REF_DIV 19
-#define IMX8MQ_VPU_PLL 20
-#define IMX8MQ_VPU_PLL_BYPASS 21
-#define IMX8MQ_VPU_PLL_OUT 22
-
-/* AUDIO PLL1 */
-#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
-#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
-#define IMX8MQ_AUDIO_PLL1 25
-#define IMX8MQ_AUDIO_PLL1_BYPASS 26
-#define IMX8MQ_AUDIO_PLL1_OUT 27
-
-/* AUDIO PLL2 */
-#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
-#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
-#define IMX8MQ_AUDIO_PLL2 30
-#define IMX8MQ_AUDIO_PLL2_BYPASS 31
-#define IMX8MQ_AUDIO_PLL2_OUT 32
-
-/* VIDEO PLL1 */
-#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
-#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
-#define IMX8MQ_VIDEO_PLL1 35
-#define IMX8MQ_VIDEO_PLL1_BYPASS 36
-#define IMX8MQ_VIDEO_PLL1_OUT 37
-
-/* SYS1 PLL */
-#define IMX8MQ_SYS1_PLL1_REF_SEL 38
-#define IMX8MQ_SYS1_PLL1_REF_DIV 39
-#define IMX8MQ_SYS1_PLL1 40
-#define IMX8MQ_SYS1_PLL1_OUT 41
-#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
-#define IMX8MQ_SYS1_PLL2 43
-#define IMX8MQ_SYS1_PLL2_DIV 44
-#define IMX8MQ_SYS1_PLL2_OUT 45
-
-/* SYS2 PLL */
-#define IMX8MQ_SYS2_PLL1_REF_SEL 46
-#define IMX8MQ_SYS2_PLL1_REF_DIV 47
-#define IMX8MQ_SYS2_PLL1 48
-#define IMX8MQ_SYS2_PLL1_OUT 49
-#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
-#define IMX8MQ_SYS2_PLL2 51
-#define IMX8MQ_SYS2_PLL2_DIV 52
-#define IMX8MQ_SYS2_PLL2_OUT 53
-
-/* SYS3 PLL */
-#define IMX8MQ_SYS3_PLL1_REF_SEL 54
-#define IMX8MQ_SYS3_PLL1_REF_DIV 55
-#define IMX8MQ_SYS3_PLL1 56
-#define IMX8MQ_SYS3_PLL1_OUT 57
-#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
-#define IMX8MQ_SYS3_PLL2 59
-#define IMX8MQ_SYS3_PLL2_DIV 60
-#define IMX8MQ_SYS3_PLL2_OUT 61
-
-/* DRAM PLL */
-#define IMX8MQ_DRAM_PLL1_REF_SEL 62
-#define IMX8MQ_DRAM_PLL1_REF_DIV 63
-#define IMX8MQ_DRAM_PLL1 64
-#define IMX8MQ_DRAM_PLL1_OUT 65
-#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
-#define IMX8MQ_DRAM_PLL2 67
-#define IMX8MQ_DRAM_PLL2_DIV 68
-#define IMX8MQ_DRAM_PLL2_OUT 69
-
-/* SYS PLL DIV */
-#define IMX8MQ_SYS1_PLL_40M 70
-#define IMX8MQ_SYS1_PLL_80M 71
-#define IMX8MQ_SYS1_PLL_100M 72
-#define IMX8MQ_SYS1_PLL_133M 73
-#define IMX8MQ_SYS1_PLL_160M 74
-#define IMX8MQ_SYS1_PLL_200M 75
-#define IMX8MQ_SYS1_PLL_266M 76
-#define IMX8MQ_SYS1_PLL_400M 77
-#define IMX8MQ_SYS1_PLL_800M 78
-
-#define IMX8MQ_SYS2_PLL_50M 79
-#define IMX8MQ_SYS2_PLL_100M 80
-#define IMX8MQ_SYS2_PLL_125M 81
-#define IMX8MQ_SYS2_PLL_166M 82
-#define IMX8MQ_SYS2_PLL_200M 83
-#define IMX8MQ_SYS2_PLL_250M 84
-#define IMX8MQ_SYS2_PLL_333M 85
-#define IMX8MQ_SYS2_PLL_500M 86
-#define IMX8MQ_SYS2_PLL_1000M 87
-
-/* CCM ROOT clocks */
-/* A53 */
-#define IMX8MQ_CLK_A53_SRC 88
-#define IMX8MQ_CLK_A53_CG 89
-#define IMX8MQ_CLK_A53_DIV 90
-/* M4 */
-#define IMX8MQ_CLK_M4_SRC 91
-#define IMX8MQ_CLK_M4_CG 92
-#define IMX8MQ_CLK_M4_DIV 93
-/* VPU */
-#define IMX8MQ_CLK_VPU_SRC 94
-#define IMX8MQ_CLK_VPU_CG 95
-#define IMX8MQ_CLK_VPU_DIV 96
-/* GPU CORE */
-#define IMX8MQ_CLK_GPU_CORE_SRC 97
-#define IMX8MQ_CLK_GPU_CORE_CG 98
-#define IMX8MQ_CLK_GPU_CORE_DIV 99
-/* GPU SHADER */
-#define IMX8MQ_CLK_GPU_SHADER_SRC 100
-#define IMX8MQ_CLK_GPU_SHADER_CG 101
-#define IMX8MQ_CLK_GPU_SHADER_DIV 102
-
-/* BUS TYPE */
-/* MAIN AXI */
-#define IMX8MQ_CLK_MAIN_AXI_SRC 103
-#define IMX8MQ_CLK_MAIN_AXI_CG 104
-#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
-#define IMX8MQ_CLK_MAIN_AXI_DIV 106
-/* ENET AXI */
-#define IMX8MQ_CLK_ENET_AXI_SRC 107
-#define IMX8MQ_CLK_ENET_AXI_CG 108
-#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
-#define IMX8MQ_CLK_ENET_AXI_DIV 110
-/* NAND_USDHC_BUS */
-#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
-#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
-#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
-#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
-/* VPU BUS */
-#define IMX8MQ_CLK_VPU_BUS_SRC 115
-#define IMX8MQ_CLK_VPU_BUS_CG 116
-#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
-#define IMX8MQ_CLK_VPU_BUS_DIV 118
-/* DISP_AXI */
-#define IMX8MQ_CLK_DISP_AXI_SRC 119
-#define IMX8MQ_CLK_DISP_AXI_CG 120
-#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
-#define IMX8MQ_CLK_DISP_AXI_DIV 122
-/* DISP APB */
-#define IMX8MQ_CLK_DISP_APB_SRC 123
-#define IMX8MQ_CLK_DISP_APB_CG 124
-#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
-#define IMX8MQ_CLK_DISP_APB_DIV 126
-/* DISP RTRM */
-#define IMX8MQ_CLK_DISP_RTRM_SRC 127
-#define IMX8MQ_CLK_DISP_RTRM_CG 128
-#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
-#define IMX8MQ_CLK_DISP_RTRM_DIV 130
-/* USB_BUS */
-#define IMX8MQ_CLK_USB_BUS_SRC 131
-#define IMX8MQ_CLK_USB_BUS_CG 132
-#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
-#define IMX8MQ_CLK_USB_BUS_DIV 134
-/* GPU_AXI */
-#define IMX8MQ_CLK_GPU_AXI_SRC 135
-#define IMX8MQ_CLK_GPU_AXI_CG 136
-#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
-#define IMX8MQ_CLK_GPU_AXI_DIV 138
-/* GPU_AHB */
-#define IMX8MQ_CLK_GPU_AHB_SRC 139
-#define IMX8MQ_CLK_GPU_AHB_CG 140
-#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
-#define IMX8MQ_CLK_GPU_AHB_DIV 142
-/* NOC */
-#define IMX8MQ_CLK_NOC_SRC 143
-#define IMX8MQ_CLK_NOC_CG 144
-#define IMX8MQ_CLK_NOC_PRE_DIV 145
-#define IMX8MQ_CLK_NOC_DIV 146
-/* NOC_APB */
-#define IMX8MQ_CLK_NOC_APB_SRC 147
-#define IMX8MQ_CLK_NOC_APB_CG 148
-#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
-#define IMX8MQ_CLK_NOC_APB_DIV 150
-
-/* AHB */
-#define IMX8MQ_CLK_AHB_SRC 151
-#define IMX8MQ_CLK_AHB_CG 152
-#define IMX8MQ_CLK_AHB_PRE_DIV 153
-#define IMX8MQ_CLK_AHB_DIV 154
-/* AUDIO AHB */
-#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
-#define IMX8MQ_CLK_AUDIO_AHB_CG 156
-#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
-#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
-
-/* DRAM_ALT */
-#define IMX8MQ_CLK_DRAM_ALT_SRC 159
-#define IMX8MQ_CLK_DRAM_ALT_CG 160
-#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
-#define IMX8MQ_CLK_DRAM_ALT_DIV 162
-/* DRAM APB */
-#define IMX8MQ_CLK_DRAM_APB_SRC 163
-#define IMX8MQ_CLK_DRAM_APB_CG 164
-#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
-#define IMX8MQ_CLK_DRAM_APB_DIV 166
-/* VPU_G1 */
-#define IMX8MQ_CLK_VPU_G1_SRC 167
-#define IMX8MQ_CLK_VPU_G1_CG 168
-#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
-#define IMX8MQ_CLK_VPU_G1_DIV 170
-/* VPU_G2 */
-#define IMX8MQ_CLK_VPU_G2_SRC 171
-#define IMX8MQ_CLK_VPU_G2_CG 172
-#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
-#define IMX8MQ_CLK_VPU_G2_DIV 174
-/* DISP_DTRC */
-#define IMX8MQ_CLK_DISP_DTRC_SRC 175
-#define IMX8MQ_CLK_DISP_DTRC_CG 176
-#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
-#define IMX8MQ_CLK_DISP_DTRC_DIV 178
-/* DISP_DC8000 */
-#define IMX8MQ_CLK_DISP_DC8000_SRC 179
-#define IMX8MQ_CLK_DISP_DC8000_CG 180
-#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
-#define IMX8MQ_CLK_DISP_DC8000_DIV 182
-/* PCIE_CTRL */
-#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
-#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
-#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
-#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
-/* PCIE_PHY */
-#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
-#define IMX8MQ_CLK_PCIE1_PHY_CG 188
-#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
-#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
-/* PCIE_AUX */
-#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
-#define IMX8MQ_CLK_PCIE1_AUX_CG 192
-#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
-#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
-/* DC_PIXEL */
-#define IMX8MQ_CLK_DC_PIXEL_SRC 195
-#define IMX8MQ_CLK_DC_PIXEL_CG 196
-#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
-#define IMX8MQ_CLK_DC_PIXEL_DIV 198
-/* LCDIF_PIXEL */
-#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
-#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
-#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
-#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
-/* SAI1~6 */
-#define IMX8MQ_CLK_SAI1_SRC 203
-#define IMX8MQ_CLK_SAI1_CG 204
-#define IMX8MQ_CLK_SAI1_PRE_DIV 205
-#define IMX8MQ_CLK_SAI1_DIV 206
-
-#define IMX8MQ_CLK_SAI2_SRC 207
-#define IMX8MQ_CLK_SAI2_CG 208
-#define IMX8MQ_CLK_SAI2_PRE_DIV 209
-#define IMX8MQ_CLK_SAI2_DIV 210
-
-#define IMX8MQ_CLK_SAI3_SRC 211
-#define IMX8MQ_CLK_SAI3_CG 212
-#define IMX8MQ_CLK_SAI3_PRE_DIV 213
-#define IMX8MQ_CLK_SAI3_DIV 214
-
-#define IMX8MQ_CLK_SAI4_SRC 215
-#define IMX8MQ_CLK_SAI4_CG 216
-#define IMX8MQ_CLK_SAI4_PRE_DIV 217
-#define IMX8MQ_CLK_SAI4_DIV 218
-
-#define IMX8MQ_CLK_SAI5_SRC 219
-#define IMX8MQ_CLK_SAI5_CG 220
-#define IMX8MQ_CLK_SAI5_PRE_DIV 221
-#define IMX8MQ_CLK_SAI5_DIV 222
-
-#define IMX8MQ_CLK_SAI6_SRC 223
-#define IMX8MQ_CLK_SAI6_CG 224
-#define IMX8MQ_CLK_SAI6_PRE_DIV 225
-#define IMX8MQ_CLK_SAI6_DIV 226
-/* SPDIF1 */
-#define IMX8MQ_CLK_SPDIF1_SRC 227
-#define IMX8MQ_CLK_SPDIF1_CG 228
-#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
-#define IMX8MQ_CLK_SPDIF1_DIV 230
-/* SPDIF2 */
-#define IMX8MQ_CLK_SPDIF2_SRC 231
-#define IMX8MQ_CLK_SPDIF2_CG 232
-#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
-#define IMX8MQ_CLK_SPDIF2_DIV 234
-/* ENET_REF */
-#define IMX8MQ_CLK_ENET_REF_SRC 235
-#define IMX8MQ_CLK_ENET_REF_CG 236
-#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
-#define IMX8MQ_CLK_ENET_REF_DIV 238
-/* ENET_TIMER */
-#define IMX8MQ_CLK_ENET_TIMER_SRC 239
-#define IMX8MQ_CLK_ENET_TIMER_CG 240
-#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
-#define IMX8MQ_CLK_ENET_TIMER_DIV 242
-/* ENET_PHY */
-#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
-#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
-#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
-#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
-/* NAND */
-#define IMX8MQ_CLK_NAND_SRC 247
-#define IMX8MQ_CLK_NAND_CG 248
-#define IMX8MQ_CLK_NAND_PRE_DIV 249
-#define IMX8MQ_CLK_NAND_DIV 250
-/* QSPI */
-#define IMX8MQ_CLK_QSPI_SRC 251
-#define IMX8MQ_CLK_QSPI_CG 252
-#define IMX8MQ_CLK_QSPI_PRE_DIV 253
-#define IMX8MQ_CLK_QSPI_DIV 254
-/* USDHC1 */
-#define IMX8MQ_CLK_USDHC1_SRC 255
-#define IMX8MQ_CLK_USDHC1_CG 256
-#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
-#define IMX8MQ_CLK_USDHC1_DIV 258
-/* USDHC2 */
-#define IMX8MQ_CLK_USDHC2_SRC 259
-#define IMX8MQ_CLK_USDHC2_CG 260
-#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
-#define IMX8MQ_CLK_USDHC2_DIV 262
-/* I2C1 */
-#define IMX8MQ_CLK_I2C1_SRC 263
-#define IMX8MQ_CLK_I2C1_CG 264
-#define IMX8MQ_CLK_I2C1_PRE_DIV 265
-#define IMX8MQ_CLK_I2C1_DIV 266
-/* I2C2 */
-#define IMX8MQ_CLK_I2C2_SRC 267
-#define IMX8MQ_CLK_I2C2_CG 268
-#define IMX8MQ_CLK_I2C2_PRE_DIV 269
-#define IMX8MQ_CLK_I2C2_DIV 270
-/* I2C3 */
-#define IMX8MQ_CLK_I2C3_SRC 271
-#define IMX8MQ_CLK_I2C3_CG 272
-#define IMX8MQ_CLK_I2C3_PRE_DIV 273
-#define IMX8MQ_CLK_I2C3_DIV 274
-/* I2C4 */
-#define IMX8MQ_CLK_I2C4_SRC 275
-#define IMX8MQ_CLK_I2C4_CG 276
-#define IMX8MQ_CLK_I2C4_PRE_DIV 277
-#define IMX8MQ_CLK_I2C4_DIV 278
-/* UART1 */
-#define IMX8MQ_CLK_UART1_SRC 279
-#define IMX8MQ_CLK_UART1_CG 280
-#define IMX8MQ_CLK_UART1_PRE_DIV 281
-#define IMX8MQ_CLK_UART1_DIV 282
-/* UART2 */
-#define IMX8MQ_CLK_UART2_SRC 283
-#define IMX8MQ_CLK_UART2_CG 284
-#define IMX8MQ_CLK_UART2_PRE_DIV 285
-#define IMX8MQ_CLK_UART2_DIV 286
-/* UART3 */
-#define IMX8MQ_CLK_UART3_SRC 287
-#define IMX8MQ_CLK_UART3_CG 288
-#define IMX8MQ_CLK_UART3_PRE_DIV 289
-#define IMX8MQ_CLK_UART3_DIV 290
-/* UART4 */
-#define IMX8MQ_CLK_UART4_SRC 291
-#define IMX8MQ_CLK_UART4_CG 292
-#define IMX8MQ_CLK_UART4_PRE_DIV 293
-#define IMX8MQ_CLK_UART4_DIV 294
-/* USB_CORE_REF */
-#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
-#define IMX8MQ_CLK_USB_CORE_REF_CG 296
-#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
-#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
-/* USB_PHY_REF */
-#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
-#define IMX8MQ_CLK_USB_PHY_REF_CG 300
-#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
-#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
-/* ECSPI1 */
-#define IMX8MQ_CLK_ECSPI1_SRC 303
-#define IMX8MQ_CLK_ECSPI1_CG 304
-#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
-#define IMX8MQ_CLK_ECSPI1_DIV 306
-/* ECSPI2 */
-#define IMX8MQ_CLK_ECSPI2_SRC 307
-#define IMX8MQ_CLK_ECSPI2_CG 308
-#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
-#define IMX8MQ_CLK_ECSPI2_DIV 310
-/* PWM1 */
-#define IMX8MQ_CLK_PWM1_SRC 311
-#define IMX8MQ_CLK_PWM1_CG 312
-#define IMX8MQ_CLK_PWM1_PRE_DIV 313
-#define IMX8MQ_CLK_PWM1_DIV 314
-/* PWM2 */
-#define IMX8MQ_CLK_PWM2_SRC 315
-#define IMX8MQ_CLK_PWM2_CG 316
-#define IMX8MQ_CLK_PWM2_PRE_DIV 317
-#define IMX8MQ_CLK_PWM2_DIV 318
-/* PWM3 */
-#define IMX8MQ_CLK_PWM3_SRC 319
-#define IMX8MQ_CLK_PWM3_CG 320
-#define IMX8MQ_CLK_PWM3_PRE_DIV 321
-#define IMX8MQ_CLK_PWM3_DIV 322
-/* PWM4 */
-#define IMX8MQ_CLK_PWM4_SRC 323
-#define IMX8MQ_CLK_PWM4_CG 324
-#define IMX8MQ_CLK_PWM4_PRE_DIV 325
-#define IMX8MQ_CLK_PWM4_DIV 326
-/* GPT1 */
-#define IMX8MQ_CLK_GPT1_SRC 327
-#define IMX8MQ_CLK_GPT1_CG 328
-#define IMX8MQ_CLK_GPT1_PRE_DIV 329
-#define IMX8MQ_CLK_GPT1_DIV 330
-/* WDOG */
-#define IMX8MQ_CLK_WDOG_SRC 331
-#define IMX8MQ_CLK_WDOG_CG 332
-#define IMX8MQ_CLK_WDOG_PRE_DIV 333
-#define IMX8MQ_CLK_WDOG_DIV 334
-/* WRCLK */
-#define IMX8MQ_CLK_WRCLK_SRC 335
-#define IMX8MQ_CLK_WRCLK_CG 336
-#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
-#define IMX8MQ_CLK_WRCLK_DIV 338
-/* DSI_CORE */
-#define IMX8MQ_CLK_DSI_CORE_SRC 339
-#define IMX8MQ_CLK_DSI_CORE_CG 340
-#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
-#define IMX8MQ_CLK_DSI_CORE_DIV 342
-/* DSI_PHY */
-#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
-#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
-#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
-#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
-/* DSI_DBI */
-#define IMX8MQ_CLK_DSI_DBI_SRC 347
-#define IMX8MQ_CLK_DSI_DBI_CG 348
-#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
-#define IMX8MQ_CLK_DSI_DBI_DIV 350
-/*DSI_ESC */
-#define IMX8MQ_CLK_DSI_ESC_SRC 351
-#define IMX8MQ_CLK_DSI_ESC_CG 352
-#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
-#define IMX8MQ_CLK_DSI_ESC_DIV 354
-/* CSI1_CORE */
-#define IMX8MQ_CLK_CSI1_CORE_SRC 355
-#define IMX8MQ_CLK_CSI1_CORE_CG 356
-#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
-#define IMX8MQ_CLK_CSI1_CORE_DIV 358
-/* CSI1_PHY */
-#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
-#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
-#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
-#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
-/* CSI_ESC */
-#define IMX8MQ_CLK_CSI1_ESC_SRC 363
-#define IMX8MQ_CLK_CSI1_ESC_CG 364
-#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
-#define IMX8MQ_CLK_CSI1_ESC_DIV 366
-/* CSI2_CORE */
-#define IMX8MQ_CLK_CSI2_CORE_SRC 367
-#define IMX8MQ_CLK_CSI2_CORE_CG 368
-#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
-#define IMX8MQ_CLK_CSI2_CORE_DIV 370
-/* CSI2_PHY */
-#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
-#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
-#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
-#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
-/* CSI2_ESC */
-#define IMX8MQ_CLK_CSI2_ESC_SRC 375
-#define IMX8MQ_CLK_CSI2_ESC_CG 376
-#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
-#define IMX8MQ_CLK_CSI2_ESC_DIV 378
-/* PCIE2_CTRL */
-#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
-#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
-#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
-#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
-/* PCIE2_PHY */
-#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
-#define IMX8MQ_CLK_PCIE2_PHY_CG 384
-#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
-#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
-/* PCIE2_AUX */
-#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
-#define IMX8MQ_CLK_PCIE2_AUX_CG 388
-#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
-#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
-/* ECSPI3 */
-#define IMX8MQ_CLK_ECSPI3_SRC 391
-#define IMX8MQ_CLK_ECSPI3_CG 392
-#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
-#define IMX8MQ_CLK_ECSPI3_DIV 394
-
-/* CCGR clocks */
-#define IMX8MQ_CLK_A53_ROOT 395
-#define IMX8MQ_CLK_DRAM_ROOT 396
-#define IMX8MQ_CLK_ECSPI1_ROOT 397
-#define IMX8MQ_CLK_ECSPI2_ROOT 398
-#define IMX8MQ_CLK_ECSPI3_ROOT 399
-#define IMX8MQ_CLK_ENET1_ROOT 400
-#define IMX8MQ_CLK_GPT1_ROOT 401
-#define IMX8MQ_CLK_I2C1_ROOT 402
-#define IMX8MQ_CLK_I2C2_ROOT 403
-#define IMX8MQ_CLK_I2C3_ROOT 404
-#define IMX8MQ_CLK_I2C4_ROOT 405
-#define IMX8MQ_CLK_M4_ROOT 406
-#define IMX8MQ_CLK_PCIE1_ROOT 407
-#define IMX8MQ_CLK_PCIE2_ROOT 408
-#define IMX8MQ_CLK_PWM1_ROOT 409
-#define IMX8MQ_CLK_PWM2_ROOT 410
-#define IMX8MQ_CLK_PWM3_ROOT 411
-#define IMX8MQ_CLK_PWM4_ROOT 412
-#define IMX8MQ_CLK_QSPI_ROOT 413
-#define IMX8MQ_CLK_SAI1_ROOT 414
-#define IMX8MQ_CLK_SAI2_ROOT 415
-#define IMX8MQ_CLK_SAI3_ROOT 416
-#define IMX8MQ_CLK_SAI4_ROOT 417
-#define IMX8MQ_CLK_SAI5_ROOT 418
-#define IMX8MQ_CLK_SAI6_ROOT 419
-#define IMX8MQ_CLK_UART1_ROOT 420
-#define IMX8MQ_CLK_UART2_ROOT 421
-#define IMX8MQ_CLK_UART3_ROOT 422
-#define IMX8MQ_CLK_UART4_ROOT 423
-#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
-#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
-#define IMX8MQ_CLK_USB1_PHY_ROOT 426
-#define IMX8MQ_CLK_USB2_PHY_ROOT 427
-#define IMX8MQ_CLK_USDHC1_ROOT 428
-#define IMX8MQ_CLK_USDHC2_ROOT 429
-#define IMX8MQ_CLK_WDOG1_ROOT 430
-#define IMX8MQ_CLK_WDOG2_ROOT 431
-#define IMX8MQ_CLK_WDOG3_ROOT 432
-#define IMX8MQ_CLK_GPU_ROOT 433
-#define IMX8MQ_CLK_HEVC_ROOT 434
-#define IMX8MQ_CLK_AVC_ROOT 435
-#define IMX8MQ_CLK_VP9_ROOT 436
-#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
-#define IMX8MQ_CLK_DISP_ROOT 438
-#define IMX8MQ_CLK_HDMI_ROOT 439
-#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
-#define IMX8MQ_CLK_VPU_DEC_ROOT 441
-#define IMX8MQ_CLK_CSI1_ROOT 442
-#define IMX8MQ_CLK_CSI2_ROOT 443
-#define IMX8MQ_CLK_RAWNAND_ROOT 444
-#define IMX8MQ_CLK_SDMA1_ROOT 445
-#define IMX8MQ_CLK_SDMA2_ROOT 446
-#define IMX8MQ_CLK_VPU_G1_ROOT 447
-#define IMX8MQ_CLK_VPU_G2_ROOT 448
-
-/* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT 449
-#define IMX8MQ_SYS2_PLL_OUT 450
-#define IMX8MQ_SYS3_PLL_OUT 451
-#define IMX8MQ_DRAM_PLL_OUT 452
-
-#define IMX8MQ_GPT_3M_CLK 453
-
-#define IMX8MQ_CLK_IPG_ROOT 454
-#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
-#define IMX8MQ_CLK_SAI1_IPG 456
-#define IMX8MQ_CLK_SAI2_IPG 457
-#define IMX8MQ_CLK_SAI3_IPG 458
-#define IMX8MQ_CLK_SAI4_IPG 459
-#define IMX8MQ_CLK_SAI5_IPG 460
-#define IMX8MQ_CLK_SAI6_IPG 461
-
-/* DSI AHB/IPG clocks */
-/* rxesc clock */
-#define IMX8MQ_CLK_DSI_AHB_SRC 462
-#define IMX8MQ_CLK_DSI_AHB_CG 463
-#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
-#define IMX8MQ_CLK_DSI_AHB_DIV 465
-/* txesc clock */
-#define IMX8MQ_CLK_DSI_IPG_DIV 466
-
-/* VIDEO2 PLL */
-#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
-#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
-#define IMX8MQ_VIDEO2_PLL1 469
-#define IMX8MQ_VIDEO2_PLL1_OUT 470
-#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
-#define IMX8MQ_VIDEO2_PLL2 472
-#define IMX8MQ_VIDEO2_PLL2_DIV 473
-#define IMX8MQ_VIDEO2_PLL2_OUT 474
-#define IMX8MQ_CLK_TMU_ROOT 475
-
-/* Display root clocks */
-#define IMX8MQ_CLK_DISP_AXI_ROOT 476
-#define IMX8MQ_CLK_DISP_APB_ROOT 477
-#define IMX8MQ_CLK_DISP_RTRM_ROOT 478
-
-#define IMX8MQ_CLK_OCOTP_ROOT 479
-
-#define IMX8MQ_CLK_DRAM_ALT_ROOT 480
-#define IMX8MQ_CLK_DRAM_CORE 481
-
-#define IMX8MQ_CLK_MU_ROOT 482
-#define IMX8MQ_VIDEO2_PLL_OUT 483
-
-#define IMX8MQ_CLK_CLKO2_SRC 484
-#define IMX8MQ_CLK_CLKO2_CG 485
-#define IMX8MQ_CLK_CLKO2_PRE_DIV 486
-#define IMX8MQ_CLK_CLKO2_DIV 487
-
-#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 488
-
-#define IMX8MQ_CLK_END 489
-#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 26da1114e8..978a0a8a9a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -197,6 +197,8 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
#ifdef CONFIG_COMMON_CLK
+#include <linux/list.h>
+
#define CLK_SET_RATE_PARENT (1 << 0) /* propagate rate change up one level */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE (1 << 12)
@@ -257,6 +259,11 @@ struct clk_divider {
extern struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width);
+
struct clk *clk_divider_alloc(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width, unsigned flags);
void clk_divider_free(struct clk *clk_divider);
@@ -280,6 +287,17 @@ struct clk *clk_fractional_divider(
u8 clk_divider_flags);
void clk_fractional_divider_free(struct clk *clk_fd);
+struct clk_mux {
+ struct clk clk;
+ void __iomem *reg;
+ int shift;
+ int width;
+};
+
+#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+
+extern struct clk_ops clk_mux_ops;
+
struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents, u8 num_parents,
unsigned flags);
@@ -288,6 +306,18 @@ struct clk *clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents, u8 num_parents,
unsigned flags);
+struct clk_gate {
+ struct clk clk;
+ void __iomem *reg;
+ int shift;
+ const char *parent;
+ unsigned flags;
+};
+
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
+extern struct clk_ops clk_gate_ops;
+
struct clk *clk_gate_alloc(const char *name, const char *parent,
void __iomem *reg, u8 shift, unsigned flags,
u8 clk_gate_flags);
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index cc6d6f7467..ee0b48e089 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -55,6 +55,11 @@
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define DIV_ROUND_DOWN_ULL(ll, d) \
+ ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+
+#define DIV_ROUND_UP_ULL(ll, d) DIV_ROUND_DOWN_ULL((ll) + (d) - 1, (d))
+
#define DIV_ROUND_CLOSEST(x, divisor)( \
{ \
typeof(divisor) __divisor = divisor; \
diff --git a/include/linux/mfd/rave-sp.h b/include/linux/mfd/rave-sp.h
index 50c9865c00..37a37788d8 100644
--- a/include/linux/mfd/rave-sp.h
+++ b/include/linux/mfd/rave-sp.h
@@ -28,6 +28,7 @@ enum rave_sp_command {
RAVE_SP_CMD_JUMP_TO_BOOTLOADER = 0xB0,
RAVE_SP_CMD_BOOTLOADER = 0xB1,
+ RAVE_SP_CMD_REQ_IP_ADDR = 0xB2,
RAVE_SP_CMD_REQ_COPPER_REV = 0xB6,
RAVE_SP_CMD_GET_I2C_DEVICE_STATUS = 0xBA,
RAVE_SP_CMD_GET_SP_SILICON_REV = 0xB9,
diff --git a/include/mfd/mc13892.h b/include/mfd/mc13892.h
index 8b522391b0..e9a41ba214 100644
--- a/include/mfd/mc13892.h
+++ b/include/mfd/mc13892.h
@@ -182,17 +182,18 @@
#define MC13892_MODE_1_VSDMODE (1 << 20)
/* Reg Power misc */
-#define MC13892_POWER_MISC_GPO1EN (1 << 6)
-#define MC13892_POWER_MISC_GPO1STBY (1 << 7)
-#define MC13892_POWER_MISC_GPO2EN (1 << 8)
-#define MC13892_POWER_MISC_GPO2STBY (1 << 9)
-#define MC13892_POWER_MISC_GPO3EN (1 << 10)
-#define MC13892_POWER_MISC_GPO3STBY (1 << 11)
-#define MC13892_POWER_MISC_GPO4EN (1 << 12)
-#define MC13892_POWER_MISC_GPO4STBY (1 << 13)
-#define MC13892_POWER_MISC_PWGT1SPIEN (1 << 15)
-#define MC13892_POWER_MISC_PWGT2SPIEN (1 << 16)
-#define MC13892_POWER_MISC_PWUP (1 << 21)
+#define MC13892_POWER_MISC_REGSCPEN (1 << 0)
+#define MC13892_POWER_MISC_GPO1EN (1 << 6)
+#define MC13892_POWER_MISC_GPO1STBY (1 << 7)
+#define MC13892_POWER_MISC_GPO2EN (1 << 8)
+#define MC13892_POWER_MISC_GPO2STBY (1 << 9)
+#define MC13892_POWER_MISC_GPO3EN (1 << 10)
+#define MC13892_POWER_MISC_GPO3STBY (1 << 11)
+#define MC13892_POWER_MISC_GPO4EN (1 << 12)
+#define MC13892_POWER_MISC_GPO4STBY (1 << 13)
+#define MC13892_POWER_MISC_PWGT1SPIEN (1 << 15)
+#define MC13892_POWER_MISC_PWGT2SPIEN (1 << 16)
+#define MC13892_POWER_MISC_GPO4ADIN (1 << 21)
/* Reg Power Control 2*/
#define MC13892_POWER_CONTROL_2_WDIRESET (1 << 12)