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authorAhmad Fatoum <a.fatoum@pengutronix.de>2021-03-22 14:39:16 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-03-23 12:16:26 +0100
commit06dd27fde7b5d398b032144ee52536278658bef6 (patch)
treef0dfcf38d04d570e510fe518aa32b3b42c5b422c
parent8eefecd0093a83e7ba2181502092a9fc2af73726 (diff)
downloadbarebox-06dd27fde7b5d398b032144ee52536278658bef6.tar.gz
barebox-06dd27fde7b5d398b032144ee52536278658bef6.tar.xz
RISC-V: add generic DT image
This barebox image implements the same header as Linux and receives the device tree in the same register. It can be booted from barebox or loaded by Qemu -kernel option. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/riscv/Kconfig9
-rw-r--r--arch/riscv/boot/Makefile1
-rw-r--r--arch/riscv/boot/board-dt-2nd.c36
3 files changed, 46 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 08a0e7cef4..e630ad4ceb 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -73,6 +73,15 @@ config 64BIT
source "arch/riscv/mach-erizo/Kconfig"
+config BOARD_RISCV_GENERIC_DT
+ select BOARD_GENERIC_DT
+ bool "Build generic RISC-V device tree 2nd stage image"
+ help
+ This enables compilation of a generic image that can be started 2nd
+ stage from barebox or from qemu. It picks up a device tree passed
+ in a1 like the Kernel does, so it could be used anywhere where a Kernel
+ image could be used. The image will be called images/barebox-dt-2nd.img
+
endmenu
menu "RISC-V specific settings"
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
index 70e5b11beb..968a826d16 100644
--- a/arch/riscv/boot/Makefile
+++ b/arch/riscv/boot/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += start.o
pbl-y += entry.o uncompress.o
+pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o
diff --git a/arch/riscv/boot/board-dt-2nd.c b/arch/riscv/boot/board-dt-2nd.c
new file mode 100644
index 0000000000..25fa7d4f2b
--- /dev/null
+++ b/arch/riscv/boot/board-dt-2nd.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <debug_ll.h>
+#include <pbl.h>
+
+#if __riscv_xlen == 64
+#define IMAGE_LOAD_OFFSET 0x200000 /* Image load offset(2MB) from start of RAM */
+#else
+#define IMAGE_LOAD_OFFSET 0x400000 /* Image load offset(4MB) from start of RAM */
+#endif
+
+/* because we can depend on being loaded at an offset, we can just use
+ * our load address as stack top
+ */
+#define __barebox_riscv_head() \
+ __barebox_riscv_header("auipc sp, 0", IMAGE_LOAD_OFFSET, \
+ RISCV_HEADER_VERSION, "RISCV", RISCV_IMAGE_MAGIC2)
+
+#include <asm/barebox-riscv.h>
+
+ENTRY_FUNCTION(start_dt_2nd, a0, _fdt, a2)
+{
+ unsigned long membase, memsize;
+ void *fdt = (void *)_fdt;
+
+ if (!fdt)
+ hang();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ fdt_find_mem(fdt, &membase, &memsize);
+
+ barebox_riscv_entry(membase, memsize, fdt);
+}