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authorAlexander Kurz <akurz@blala.de>2017-04-23 19:37:40 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-04-24 15:28:02 +0200
commit13ed8eeaf0e7efc72991b9d92d1758297aa9c338 (patch)
tree5c0dcd99a153e6051e91d4c85b1b917a0d5092dc
parent39a785fff14dfaecdc048b3a163988184b982b6b (diff)
downloadbarebox-13ed8eeaf0e7efc72991b9d92d1758297aa9c338.tar.gz
ARM: i.MX50 clock: add clock for USB physbase
Add the USB physbase clock entry for i.MX50 SoC to enable USB device creation via DT. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/imx/clk-imx5.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c
index c4c47a6..edebd25 100644
--- a/drivers/clk/imx/clk-imx5.c
+++ b/drivers/clk/imx/clk-imx5.c
@@ -313,6 +313,7 @@ int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs)
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX50_ESDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM1_BASE_ADDR, "per");
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM2_BASE_ADDR, "per");
+ clkdev_add_physbase(clks[IMX5_CLK_AHB], MX50_OTG_BASE_ADDR, NULL);
return 0;
}