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author | Antony Pavlov <antonynpavlov@gmail.com> | 2014-09-08 10:53:06 +0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-09 10:20:30 +0200 |
commit | 16b50fcd7f96a71a043e56fd3cfa745d44623e35 (patch) | |
tree | 460284e2a781106e4565faf9b5d17e1ae288c03e | |
parent | 9a585cd7327d0bdcfc51e120c1b7f5f45354116b (diff) | |
download | barebox-16b50fcd7f96a71a043e56fd3cfa745d44623e35.tar.gz barebox-16b50fcd7f96a71a043e56fd3cfa745d44623e35.tar.xz |
openrisc: dts: import or1ksim.dts from linux-3.16
There are some minor changes with original linux-3.16 file:
* the 'model' attribute is added (it used for barebox banner board name);
* all "opencores,*-rtlsvn*" 'compatible' attribute values are dropped;
these values are not actually used in the device drivers.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/openrisc/dts/or1ksim.dts | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/openrisc/dts/or1ksim.dts b/arch/openrisc/dts/or1ksim.dts new file mode 100644 index 0000000000..7316cc6770 --- /dev/null +++ b/arch/openrisc/dts/or1ksim.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/ { + model = "or1ksim"; + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <50000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethoc"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; |