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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:19:21 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:48 +0100 |
| commit | 203d2c0097938e426fdd0ca899183334d29bef7b (patch) | |
| tree | ba272d4246bc19913b17ffc7aac47a44342db63d | |
| parent | 8aff03ca6b1078dd6a77b3836320329380351b22 (diff) | |
| download | barebox-203d2c0097938e426fdd0ca899183334d29bef7b.tar.gz barebox-203d2c0097938e426fdd0ca899183334d29bef7b.tar.xz | |
PCI: dwc: Add accessors for write permission of DBI
Port of a Linux commit e44abfed6fcb750d24f4438dc9d5a02eebb5fcac
The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.
Add accessors to enable and disable write permission, and use them instead
of accessing MISC_CONTROL_1_OFF directly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | drivers/pci/pcie-designware.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h index 933c2b533d..0f16593198 100644 --- a/drivers/pci/pcie-designware.h +++ b/drivers/pci/pcie-designware.h @@ -83,6 +83,9 @@ #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN (0x1 << 0) + /* PCIe Port Logic registers */ #define PLR_OFFSET 0x700 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) @@ -174,4 +177,27 @@ static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) { return __dw_pcie_readl_dbi(pci, pci->dbi_base, reg, 0x4); } + +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val |= PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val &= ~PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + #endif /* _PCIE_DESIGNWARE_H */ |