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authorSascha Hauer <s.hauer@pengutronix.de>2015-06-30 15:58:21 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-07-02 08:20:44 +0200
commit302076b017f386a1cc51fcd405cdd6edcae9cd86 (patch)
tree1acf6aa7f11fa5874215ae38bb5ac0ceb6b35188
parent8d4606fd850ca127ec79855d838df0cfd0c29d32 (diff)
downloadbarebox-302076b017f386a1cc51fcd405cdd6edcae9cd86.tar.gz
barebox-302076b017f386a1cc51fcd405cdd6edcae9cd86.tar.xz
ARM: OMAP3: Change DSS divider to the one U-Boot uses
U-Boot uses 2 as the DSS divider, so do the same in barebox. This shouldn't currently have any effect to barebox, but makes porting some U-Boot code easier which makes assumptions about the DSS clock rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-omap/include/mach/omap3-clock.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index 1ef46aa3e5..7c52da754f 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -107,7 +107,7 @@
/* PER DPLL */
#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
-#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */
+#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))