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authorSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:24 +0200
commit355884b413b1c2546c04e397d6a480efb27ae811 (patch)
tree7831dfbd8ee4e61c69be7d101134eb54a5810281
parent6940ba22c66ac1c713500027bf5f6832442a1410 (diff)
downloadbarebox-355884b413b1c2546c04e397d6a480efb27ae811.tar.gz
dts: update to v5.3-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--dts/Bindings/arm/idle-states.txt2
-rw-r--r--dts/Bindings/arm/renesas.yaml2
-rw-r--r--dts/Bindings/arm/socionext/milbeaut.yaml2
-rw-r--r--dts/Bindings/arm/ti/ti,davinci.yaml2
-rw-r--r--dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml2
-rw-r--r--dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml2
-rw-r--r--dts/Bindings/iio/accel/adi,adxl345.yaml2
-rw-r--r--dts/Bindings/iio/accel/adi,adxl372.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/amazon,al-fic.txt16
-rw-r--r--dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml2
-rw-r--r--dts/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml (renamed from dts/Bindings/misc/intel,ixp4xx-queue-manager.yaml)2
-rw-r--r--dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml2
-rw-r--r--dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml4
-rw-r--r--dts/Bindings/nvmem/nvmem-consumer.yaml45
-rw-r--r--dts/Bindings/nvmem/nvmem.txt81
-rw-r--r--dts/Bindings/nvmem/nvmem.yaml93
-rw-r--r--dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml2
-rw-r--r--dts/Bindings/timer/intel,ixp4xx-timer.yaml2
-rw-r--r--dts/Bindings/usb/usb251xb.txt6
-rw-r--r--dts/src/arm/bcm47094-linksys-panamera.dts3
-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dtsi2
-rw-r--r--dts/src/arm/imx6ul-geam.dts2
-rw-r--r--dts/src/arm/imx6ul-isiot.dtsi2
-rw-r--r--dts/src/arm/imx6ul-pico-hobbit.dts2
-rw-r--r--dts/src/arm/imx6ul-pico-pi.dts4
-rw-r--r--dts/src/arm/imx7ulp.dtsi2
-rw-r--r--dts/src/arm64/freescale/imx8mm-pinfunc.h4
-rw-r--r--dts/src/arm64/freescale/imx8mq.dtsi3
-rw-r--r--dts/src/riscv/sifive/fu540-c000.dtsi15
-rw-r--r--dts/src/riscv/sifive/hifive-unleashed-a00.dts9
30 files changed, 200 insertions, 119 deletions
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index 326f29b..2d325be 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -703,4 +703,4 @@ cpus {
https://www.devicetree.org/specifications/
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
- Documentation/arm64/booting.txt
+ Documentation/arm64/booting.rst
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index 08c923f..28eb458 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/shmobile.yaml#
+$id: http://devicetree.org/schemas/arm/renesas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
diff --git a/dts/Bindings/arm/socionext/milbeaut.yaml b/dts/Bindings/arm/socionext/milbeaut.yaml
index aae53fc..2bd519d 100644
--- a/dts/Bindings/arm/socionext/milbeaut.yaml
+++ b/dts/Bindings/arm/socionext/milbeaut.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
+$id: http://devicetree.org/schemas/arm/socionext/milbeaut.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Milbeaut platforms device tree bindings
diff --git a/dts/Bindings/arm/ti/ti,davinci.yaml b/dts/Bindings/arm/ti/ti,davinci.yaml
index 4326d2c..a8765ba 100644
--- a/dts/Bindings/arm/ti/ti,davinci.yaml
+++ b/dts/Bindings/arm/ti/ti,davinci.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/ti/davinci.yaml#
+$id: http://devicetree.org/schemas/arm/ti/ti,davinci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments DaVinci Platforms Device Tree Bindings
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
index c935405..fa4d143 100644
--- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml#
+$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner Clock Control Unit Device Tree Bindings
diff --git a/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
index 8cb136c..4f0db8e 100644
--- a/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+++ b/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
@@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"
+$id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx Network Processing Engine
diff --git a/dts/Bindings/iio/accel/adi,adxl345.yaml b/dts/Bindings/iio/accel/adi,adxl345.yaml
index 7ba167e..c602b6f 100644
--- a/dts/Bindings/iio/accel/adi,adxl345.yaml
+++ b/dts/Bindings/iio/accel/adi,adxl345.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/iio/accelerometers/adi,adxl345.yaml#
+$id: http://devicetree.org/schemas/iio/accel/adi,adxl345.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers
diff --git a/dts/Bindings/iio/accel/adi,adxl372.yaml b/dts/Bindings/iio/accel/adi,adxl372.yaml
index a7fafb9..e7daffe 100644
--- a/dts/Bindings/iio/accel/adi,adxl372.yaml
+++ b/dts/Bindings/iio/accel/adi,adxl372.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/iio/accelerometers/adi,adxl372.yaml#
+$id: http://devicetree.org/schemas/iio/accel/adi,adxl372.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer
diff --git a/dts/Bindings/interrupt-controller/amazon,al-fic.txt b/dts/Bindings/interrupt-controller/amazon,al-fic.txt
index 4e82fd5..c676b03 100644
--- a/dts/Bindings/interrupt-controller/amazon,al-fic.txt
+++ b/dts/Bindings/interrupt-controller/amazon,al-fic.txt
@@ -5,21 +5,19 @@ Required properties:
- compatible: should be "amazon,al-fic"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: must be 2.
- First cell defines the index of the interrupt within the controller.
- Second cell is used to specify the trigger type and must be one of the
- following:
- - bits[3:0] trigger type and level flags
- 1 = low-to-high edge triggered
- 4 = active high level-sensitive
-- interrupt-parent: specifies the parent interrupt controller.
+- #interrupt-cells : must be 2. Specifies the number of cells needed to encode
+ an interrupt source. Supported trigger types are low-to-high edge
+ triggered and active high level-sensitive.
- interrupts: describes which input line in the interrupt parent, this
fic's output is connected to. This field property depends on the parent's
binding
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
Example:
-amazon_fic: interrupt-controller@0xfd8a8500 {
+amazon_fic: interrupt-controller@fd8a8500 {
compatible = "amazon,al-fic";
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
index bae10e2..507c141 100644
--- a/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
+++ b/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
@@ -2,7 +2,7 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#"
+$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx XScale Networking Processors Interrupt Controller
diff --git a/dts/Bindings/misc/intel,ixp4xx-queue-manager.yaml b/dts/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
index d2313b1..0ea21a6 100644
--- a/dts/Bindings/misc/intel,ixp4xx-queue-manager.yaml
+++ b/dts/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
@@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#"
+$id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx AHB Queue Manager
diff --git a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
index d4084c1..3fb0714 100644
--- a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-gmac.yaml#
+$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83t EMAC Device Tree Bindings
diff --git a/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml
index c9efd6e..1084e9d 100644
--- a/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml
+++ b/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml
@@ -37,13 +37,13 @@ required:
examples:
- |
- sid@1c23800 {
+ efuse@1c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
- |
- sid@1c23800 {
+ efuse@1c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>;
};
diff --git a/dts/Bindings/nvmem/nvmem-consumer.yaml b/dts/Bindings/nvmem/nvmem-consumer.yaml
new file mode 100644
index 0000000..b7c00ed
--- /dev/null
+++ b/dts/Bindings/nvmem/nvmem-consumer.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nvmem-consumer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM (Non Volatile Memory) Consumer Device Tree Bindings
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+select: true
+
+properties:
+ nvmem:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ List of phandle to the nvmem providers.
+
+ nvmem-cells:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ List of phandle to the nvmem data cells.
+
+ nvmem-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ Names for the each nvmem provider.
+
+ nvmem-cell-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ Names for each nvmem-cells specified.
+
+dependencies:
+ nvmem-names: [ nvmem ]
+ nvmem-cell-names: [ nvmem-cells ]
+
+examples:
+ - |
+ tsens {
+ /* ... */
+ nvmem-cells = <&tsens_calibration>;
+ nvmem-cell-names = "calibration";
+ };
diff --git a/dts/Bindings/nvmem/nvmem.txt b/dts/Bindings/nvmem/nvmem.txt
index fd06c09..46a7ef4 100644
--- a/dts/Bindings/nvmem/nvmem.txt
+++ b/dts/Bindings/nvmem/nvmem.txt
@@ -1,80 +1 @@
-= NVMEM(Non Volatile Memory) Data Device Tree Bindings =
-
-This binding is intended to represent the location of hardware
-configuration data stored in NVMEMs like eeprom, efuses and so on.
-
-On a significant proportion of boards, the manufacturer has stored
-some data on NVMEM, for the OS to be able to retrieve these information
-and act upon it. Obviously, the OS has to know about where to retrieve
-these data from, and where they are stored on the storage device.
-
-This document is here to document this.
-
-= Data providers =
-Contains bindings specific to provider drivers and data cells as children
-of this node.
-
-Optional properties:
- read-only: Mark the provider as read only.
-
-= Data cells =
-These are the child nodes of the provider which contain data cell
-information like offset and size in nvmem provider.
-
-Required properties:
-reg: specifies the offset in byte within the storage device.
-
-Optional properties:
-
-bits: Is pair of bit location and number of bits, which specifies offset
- in bit and number of bits within the address range specified by reg property.
- Offset takes values from 0-7.
-
-For example:
-
- /* Provider */
- qfprom: qfprom@700000 {
- ...
-
- /* Data cells */
- tsens_calibration: calib@404 {
- reg = <0x404 0x10>;
- };
-
- tsens_calibration_bckp: calib_bckp@504 {
- reg = <0x504 0x11>;
- bits = <6 128>
- };
-
- pvs_version: pvs-version@6 {
- reg = <0x6 0x2>
- bits = <7 2>
- };
-
- speed_bin: speed-bin@c{
- reg = <0xc 0x1>;
- bits = <2 3>;
-
- };
- ...
- };
-
-= Data consumers =
-Are device nodes which consume nvmem data cells/providers.
-
-Required-properties:
-nvmem-cells: list of phandle to the nvmem data cells.
-nvmem-cell-names: names for the each nvmem-cells specified. Required if
- nvmem-cells is used.
-
-Optional-properties:
-nvmem : list of phandles to nvmem providers.
-nvmem-names: names for the each nvmem provider. required if nvmem is used.
-
-For example:
-
- tsens {
- ...
- nvmem-cells = <&tsens_calibration>;
- nvmem-cell-names = "calibration";
- };
+This file has been moved to nvmem.yaml and nvmem-consumer.yaml.
diff --git a/dts/Bindings/nvmem/nvmem.yaml b/dts/Bindings/nvmem/nvmem.yaml
new file mode 100644
index 0000000..1c75a05
--- /dev/null
+++ b/dts/Bindings/nvmem/nvmem.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVMEM (Non Volatile Memory) Device Tree Bindings
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding is intended to represent the location of hardware
+ configuration data stored in NVMEMs like eeprom, efuses and so on.
+
+ On a significant proportion of boards, the manufacturer has stored
+ some data on NVMEM, for the OS to be able to retrieve these
+ information and act upon it. Obviously, the OS has to know about
+ where to retrieve these data from, and where they are stored on the
+ storage device.
+
+properties:
+ $nodename:
+ pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$"
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ read-only:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Mark the provider as read only.
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ maxItems: 1
+ description:
+ Offset and size in bytes within the storage device.
+
+ bits:
+ maxItems: 1
+ items:
+ items:
+ - minimum: 0
+ maximum: 7
+ description:
+ Offset in bit within the address range specified by reg.
+ - minimum: 1
+ description:
+ Size in bit within the address range specified by reg.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+examples:
+ - |
+ qfprom: eeprom@700000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* ... */
+
+ /* Data cells */
+ tsens_calibration: calib@404 {
+ reg = <0x404 0x10>;
+ };
+
+ tsens_calibration_bckp: calib_bckp@504 {
+ reg = <0x504 0x11>;
+ bits = <6 128>;
+ };
+
+ pvs_version: pvs-version@6 {
+ reg = <0x6 0x2>;
+ bits = <7 2>;
+ };
+
+ speed_bin: speed-bin@c{
+ reg = <0xc 0x1>;
+ bits = <2 3>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index 250f9d5..fa46670 100644
--- a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dphy.yaml#
+$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings
diff --git a/dts/Bindings/timer/intel,ixp4xx-timer.yaml b/dts/Bindings/timer/intel,ixp4xx-timer.yaml
index a36a074..2807225 100644
--- a/dts/Bindings/timer/intel,ixp4xx-timer.yaml
+++ b/dts/Bindings/timer/intel,ixp4xx-timer.yaml
@@ -2,7 +2,7 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#"
+$id: "http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Intel IXP4xx XScale Networking Processors Timers
diff --git a/dts/Bindings/usb/usb251xb.txt b/dts/Bindings/usb/usb251xb.txt
index bc7945e..17915f6 100644
--- a/dts/Bindings/usb/usb251xb.txt
+++ b/dts/Bindings/usb/usb251xb.txt
@@ -64,10 +64,8 @@ Optional properties :
- power-on-time-ms : Specifies the time it takes from the time the host
initiates the power-on sequence to a port until the port has adequate
power. The value is given in ms in a 0 - 510 range (default is 100ms).
- - swap-dx-lanes : Specifies the downstream ports which will swap the
- differential-pair (D+/D-), default is not-swapped.
- - swap-us-lanes : Selects the upstream port differential-pair (D+/D-)
- swapping (boolean, default is not-swapped)
+ - swap-dx-lanes : Specifies the ports which will swap the differential-pair
+ (D+/D-), default is not-swapped.
Examples:
usb2512b@2c {
diff --git a/dts/src/arm/bcm47094-linksys-panamera.dts b/dts/src/arm/bcm47094-linksys-panamera.dts
index 18d0ae4..0faae89 100644
--- a/dts/src/arm/bcm47094-linksys-panamera.dts
+++ b/dts/src/arm/bcm47094-linksys-panamera.dts
@@ -124,6 +124,9 @@
};
mdio-bus-mux {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
/* BIT(9) = 1 => external mdio */
mdio_ext: mdio@200 {
reg = <0x200>;
diff --git a/dts/src/arm/imx6ul-14x14-evk.dtsi b/dts/src/arm/imx6ul-14x14-evk.dtsi
index cbe61b6..c2a9dd5 100644
--- a/dts/src/arm/imx6ul-14x14-evk.dtsi
+++ b/dts/src/arm/imx6ul-14x14-evk.dtsi
@@ -112,7 +112,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6ul-geam.dts b/dts/src/arm/imx6ul-geam.dts
index 21ddd35..9f63706 100644
--- a/dts/src/arm/imx6ul-geam.dts
+++ b/dts/src/arm/imx6ul-geam.dts
@@ -156,7 +156,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6ul-isiot.dtsi b/dts/src/arm/imx6ul-isiot.dtsi
index b26d4f5..cc9adce 100644
--- a/dts/src/arm/imx6ul-isiot.dtsi
+++ b/dts/src/arm/imx6ul-isiot.dtsi
@@ -148,7 +148,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6ul-pico-hobbit.dts b/dts/src/arm/imx6ul-pico-hobbit.dts
index 39eeedd..09f7ffa 100644
--- a/dts/src/arm/imx6ul-pico-hobbit.dts
+++ b/dts/src/arm/imx6ul-pico-hobbit.dts
@@ -43,7 +43,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/dts/src/arm/imx6ul-pico-pi.dts b/dts/src/arm/imx6ul-pico-pi.dts
index de07357..6cd7d58 100644
--- a/dts/src/arm/imx6ul-pico-pi.dts
+++ b/dts/src/arm/imx6ul-pico-pi.dts
@@ -43,7 +43,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
@@ -58,7 +58,7 @@
};
&i2c3 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
diff --git a/dts/src/arm/imx7ulp.dtsi b/dts/src/arm/imx7ulp.dtsi
index 992747a..56907bb 100644
--- a/dts/src/arm/imx7ulp.dtsi
+++ b/dts/src/arm/imx7ulp.dtsi
@@ -186,7 +186,7 @@
reg = <0x40330200 0x200>;
};
- usbphy1: usb-phy@0x40350000 {
+ usbphy1: usb-phy@40350000 {
compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
reg = <0x40350000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/src/arm64/freescale/imx8mm-pinfunc.h b/dts/src/arm64/freescale/imx8mm-pinfunc.h
index e25f7fc..cffa899 100644
--- a/dts/src/arm64/freescale/imx8mm-pinfunc.h
+++ b/dts/src/arm64/freescale/imx8mm-pinfunc.h
@@ -462,7 +462,7 @@
#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
-#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
@@ -472,7 +472,7 @@
#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
-#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi
index d09b808..52aae34 100644
--- a/dts/src/arm64/freescale/imx8mq.dtsi
+++ b/dts/src/arm64/freescale/imx8mq.dtsi
@@ -715,8 +715,7 @@
sai2: sai@308b0000 {
#sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai",
- "fsl,imx6sx-sai";
+ compatible = "fsl,imx8mq-sai";
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
diff --git a/dts/src/riscv/sifive/fu540-c000.dtsi b/dts/src/riscv/sifive/fu540-c000.dtsi
index 4098349..9bf63f0 100644
--- a/dts/src/riscv/sifive/fu540-c000.dtsi
+++ b/dts/src/riscv/sifive/fu540-c000.dtsi
@@ -217,5 +217,20 @@
#size-cells = <0>;
status = "disabled";
};
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
};
};
diff --git a/dts/src/riscv/sifive/hifive-unleashed-a00.dts b/dts/src/riscv/sifive/hifive-unleashed-a00.dts
index 0b55c53..93d68cb 100644
--- a/dts/src/riscv/sifive/hifive-unleashed-a00.dts
+++ b/dts/src/riscv/sifive/hifive-unleashed-a00.dts
@@ -76,3 +76,12 @@
disable-wp;
};
};
+
+&eth0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};