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authorSascha Hauer <s.hauer@pengutronix.de>2020-01-14 13:52:01 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-01-14 13:52:01 +0100
commit3645a9f0d0ca785c51fd533bdb0a8fecd050d736 (patch)
tree2aa99efa1f7a12a584879522206c1283259f89e5
parent089b0370ba1d9080428f7298e586a24e51ba12d3 (diff)
downloadbarebox-3645a9f0d0ca785c51fd533bdb0a8fecd050d736.tar.gz
dts: update to v5.5-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--dts/src/riscv/sifive/fu540-c000.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/dts/src/riscv/sifive/fu540-c000.dtsi b/dts/src/riscv/sifive/fu540-c000.dtsi
index 70a1891..a2e3d54 100644
--- a/dts/src/riscv/sifive/fu540-c000.dtsi
+++ b/dts/src/riscv/sifive/fu540-c000.dtsi
@@ -54,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -253,6 +257,17 @@
#pwm-cells = <3>;
status = "disabled";
};
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
};
};