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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-07-09 08:21:19 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-07-09 08:21:19 +0200 |
| commit | 49b5c5a7e148600a98ce1730c76e23246cbd755c (patch) | |
| tree | 49c13b6847ba58e27fee737c771d1a0ba04039d4 | |
| parent | 7ad77a3b86078d6a2468111c1b9986dadcccf89b (diff) | |
| parent | 5adbb4b01249184d353d27a40cab9964907b246b (diff) | |
| download | barebox-49b5c5a7e148600a98ce1730c76e23246cbd755c.tar.gz barebox-49b5c5a7e148600a98ce1730c76e23246cbd755c.tar.xz | |
Merge branch 'for-next/vfxxx'
8 files changed, 468 insertions, 498 deletions
diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg index 8dd62be210..71150802bf 100644 --- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg +++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg @@ -2,277 +2,14 @@ soc vf610 loadaddr 0x80000000 dcdofs 0x400 -#define VF610_DDR_PAD_CTRL 0x00000180 /* 25 Ohm drive strength */ -#define VF610_DDR_PAD_CTRL_1 0x00010180 /* 25 Ohm drive strength + differential input */ +#include <mach/vf610-iomux-regs.h> +#include <mach/vf610-ddrmc-regs.h> -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x00210000 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00002000 -#define DDRMC_PHY_OFF 0x00000000 -#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 +#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg> +#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg> +#include <mach/flash-header/vf610-ddr-cr-default.imxcfg> +#include <mach/flash-header/vf610-ddr-phy-default.imxcfg> -#ifdef DEBUG -#define CHECKPOINT(n) wm 32 0x3f040000 n -#else -#define CHECKPOINT(n) -#endif - -CHECKPOINT(1) - -/* ======================= Clock initialization =======================*/ - -/* - * Ungate all IP block clocks - */ -wm 32 0x4006b040 0xffffffff -wm 32 0x4006b044 0xffffffff -wm 32 0x4006b048 0xffffffff -wm 32 0x4006b04c 0xffffffff -wm 32 0x4006b050 0xffffffff -wm 32 0x4006b058 0xffffffff -wm 32 0x4006b05c 0xffffffff -wm 32 0x4006b060 0xffffffff -wm 32 0x4006b064 0xffffffff -wm 32 0x4006b068 0xffffffff -wm 32 0x4006b06c 0xffffffff - - -/* - * We have to options to clock DDR controller: - * - * - Use Core-A5 clock - * - Use PLL2 PFD2 clock - * - - * Using first option without changing PLL settings doesn't seem to be - * possible given that DDRMC requires minimum of 300Mhz and MaskROM - * configures it to be clocked at 264Mhz. Changing PLL1 settings - * proved to be challenging becuase MaskROM code executing this DCD - * will also be fetching the rest of the bootloader via some - * peripheral interface whose clock is derived from Cortex-A5 clock. - * - * As a result this DCD configuration code uses the second option of - * clocking DDR wiht PLL2 PFD2 clock output - * - * Turn PLL2 on - */ -wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */ - -CHECKPOINT(2) - -/* - * Wait for PLLs to lock - */ -check 32 until_any_bit_set 0x40050030 0x80000000 - - -CHECKPOINT(3) - -/* - * Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output - */ -clear_bits 32 0x4006b008 0x00000040 -set_bits 32 0x4006b008 0x00002000 - - - -/* ======================= DDR IOMUX ======================= */ - -CHECKPOINT(4) - -wm 32 0x40048220 VF610_DDR_PAD_CTRL -wm 32 0x40048224 VF610_DDR_PAD_CTRL -wm 32 0x40048228 VF610_DDR_PAD_CTRL -wm 32 0x4004822c VF610_DDR_PAD_CTRL -wm 32 0x40048230 VF610_DDR_PAD_CTRL -wm 32 0x40048234 VF610_DDR_PAD_CTRL -wm 32 0x40048238 VF610_DDR_PAD_CTRL -wm 32 0x4004823c VF610_DDR_PAD_CTRL -wm 32 0x40048240 VF610_DDR_PAD_CTRL -wm 32 0x40048244 VF610_DDR_PAD_CTRL -wm 32 0x40048248 VF610_DDR_PAD_CTRL -wm 32 0x4004824c VF610_DDR_PAD_CTRL -wm 32 0x40048250 VF610_DDR_PAD_CTRL -wm 32 0x40048254 VF610_DDR_PAD_CTRL -wm 32 0x40048258 VF610_DDR_PAD_CTRL -wm 32 0x4004825c VF610_DDR_PAD_CTRL -wm 32 0x40048260 VF610_DDR_PAD_CTRL -wm 32 0x40048264 VF610_DDR_PAD_CTRL -wm 32 0x40048268 VF610_DDR_PAD_CTRL -wm 32 0x4004826c VF610_DDR_PAD_CTRL -wm 32 0x40048270 VF610_DDR_PAD_CTRL -wm 32 0x40048274 VF610_DDR_PAD_CTRL -wm 32 0x40048278 VF610_DDR_PAD_CTRL -wm 32 0x4004827c VF610_DDR_PAD_CTRL_1 -wm 32 0x40048280 VF610_DDR_PAD_CTRL_1 -wm 32 0x40048284 VF610_DDR_PAD_CTRL_1 -wm 32 0x40048288 VF610_DDR_PAD_CTRL_1 -wm 32 0x4004828c VF610_DDR_PAD_CTRL_1 -wm 32 0x40048290 VF610_DDR_PAD_CTRL_1 -wm 32 0x40048294 VF610_DDR_PAD_CTRL_1 -wm 32 0x40048298 VF610_DDR_PAD_CTRL_1 -wm 32 0x4004829c VF610_DDR_PAD_CTRL_1 -wm 32 0x400482a0 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482a4 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482a8 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482ac VF610_DDR_PAD_CTRL_1 -wm 32 0x400482b0 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482b4 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482b8 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482bc VF610_DDR_PAD_CTRL_1 -wm 32 0x400482c0 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482c4 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482c8 VF610_DDR_PAD_CTRL_1 -wm 32 0x400482cc VF610_DDR_PAD_CTRL -wm 32 0x400482d0 VF610_DDR_PAD_CTRL -wm 32 0x400482d4 VF610_DDR_PAD_CTRL -wm 32 0x400482d8 VF610_DDR_PAD_CTRL -wm 32 0x4004821c VF610_DDR_PAD_CTRL - -/* ======================= DDR Controller =======================*/ - -CHECKPOINT(5) - -wm 32 0x400ae000 0x00000600 -wm 32 0x400ae008 0x00000020 -wm 32 0x400ae028 0x00013880 -wm 32 0x400ae02c 0x00030d40 -wm 32 0x400ae030 0x0000050c -wm 32 0x400ae034 0x15040400 -wm 32 0x400ae038 0x1406040f -wm 32 0x400ae040 0x04040000 -wm 32 0x400ae044 0x006db00c -wm 32 0x400ae048 0x00000403 -wm 32 0x400ae050 0x01000000 -wm 32 0x400ae054 0x00060001 -wm 32 0x400ae058 0x000c0000 -wm 32 0x400ae05c 0x03000200 -wm 32 0x400ae060 0x00000006 -wm 32 0x400ae064 0x00010000 -wm 32 0x400ae068 0x0c30002c -wm 32 0x400ae070 0x00000000 -wm 32 0x400ae074 0x00000003 -wm 32 0x400ae078 0x0000000a -wm 32 0x400ae07c 0x003001d4 -wm 32 0x400ae084 0x00010000 -wm 32 0x400ae088 0x00050500 -wm 32 0x400ae098 0x00000000 -wm 32 0x400ae09c 0x04001002 -wm 32 0x400ae0a4 0x00000001 -wm 32 0x400ae0c0 0x00460420 -wm 32 0x400ae108 0x01000200 -wm 32 0x400ae10c 0x00000040 -wm 32 0x400ae114 0x00000200 -wm 32 0x400ae118 0x00000040 -wm 32 0x400ae120 0x00000000 -wm 32 0x400ae124 0x0a010300 -wm 32 0x400ae128 0x01014040 -wm 32 0x400ae12c 0x01010101 -wm 32 0x400ae130 0x03030100 -wm 32 0x400ae134 0x01000101 -wm 32 0x400ae138 0x0700000c -wm 32 0x400ae13c 0x00000000 -wm 32 0x400ae148 0x10000000 -wm 32 0x400ae15c 0x01000000 -wm 32 0x400ae160 0x00040000 -wm 32 0x400ae164 0x00000002 -wm 32 0x400ae16c 0x00020000 -wm 32 0x400ae180 0x00002819 -wm 32 0x400ae184 0x01000000 -wm 32 0x400ae188 0x00000000 -wm 32 0x400ae18c 0x00000000 -wm 32 0x400ae198 0x00010100 -wm 32 0x400ae1a4 0x00000000 -wm 32 0x400ae1a8 0x00000004 -wm 32 0x400ae1b8 0x00040000 -wm 32 0x400ae1c8 0x00000000 -wm 32 0x400ae1cc 0x00000000 -wm 32 0x400ae1d4 0x00000000 -wm 32 0x400ae1d8 0x01010000 -wm 32 0x400ae1e0 0x02020000 -wm 32 0x400ae1e4 0x00000202 -wm 32 0x400ae1e8 0x01010064 -wm 32 0x400ae1ec 0x00010101 -wm 32 0x400ae1f0 0x00000064 -wm 32 0x400ae1f8 0x00000800 -wm 32 0x400ae210 0x00000506 -wm 32 0x400ae224 0x00020000 -wm 32 0x400ae228 0x01000000 -wm 32 0x400ae22c 0x04070303 -wm 32 0x400ae230 0x00000040 -wm 32 0x400ae23c 0x06000080 -wm 32 0x400ae240 0x04070303 -wm 32 0x400ae244 0x00000040 -wm 32 0x400ae248 0x00000040 -wm 32 0x400ae24c 0x000f0000 -wm 32 0x400ae250 0x000f0000 -wm 32 0x400ae25c 0x00000101 -wm 32 0x400ae268 0x682c4000 -wm 32 0x400ae26c 0x00000012 -wm 32 0x400ae278 0x00000006 -wm 32 0x400ae284 0x00010202 - -/* ======================= DDR PHY =======================*/ - -CHECKPOINT(6) - -wm 32 0x400ae400 DDRMC_PHY_DQ_TIMING -wm 32 0x400ae440 DDRMC_PHY_DQ_TIMING -wm 32 0x400ae480 DDRMC_PHY_DQ_TIMING -wm 32 0x400ae404 DDRMC_PHY_DQS_TIMING -wm 32 0x400ae444 DDRMC_PHY_DQS_TIMING -wm 32 0x400ae408 DDRMC_PHY_CTRL -wm 32 0x400ae448 DDRMC_PHY_CTRL -wm 32 0x400ae488 DDRMC_PHY_CTRL -wm 32 0x400ae40c DDRMC_PHY_MASTER_CTRL -wm 32 0x400ae44c DDRMC_PHY_MASTER_CTRL -wm 32 0x400ae48c DDRMC_PHY_MASTER_CTRL -wm 32 0x400ae410 DDRMC_PHY_SLAVE_CTRL -wm 32 0x400ae450 DDRMC_PHY_SLAVE_CTRL -wm 32 0x400ae490 DDRMC_PHY_SLAVE_CTRL -wm 32 0x400ae4c4 DDRMC_PHY_OFF -wm 32 0x400ae4c8 0x00001100 -wm 32 0x400ae4d0 DDRMC_PHY_PROC_PAD_ODT - -wm 32 0x400ae000 0x00000601 - -CHECKPOINT(7) +wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START check 32 until_any_bit_set 0x400ae140 0x100 - -CHECKPOINT(8) - -/* - * Cargo cult DDR controller initialization here we come! - * - * Experemintation with VF610 Tower Board shows that without the - * following code the board would not boot off of SD card when - * power-cycled. It will however happily boot when reset via SW3/Reset - * button. For whatever reason the following actions appear to be - * necessary: - * - * - Initialize DDRMC as usual - * - Issue a read to location in DDR address space - * - Disable DDRMC - * - Enable DDRMC and wait for it to finish initializing - * - * I am sure this is all going to be extrememly embarrassing to read - * if/when the real problem and real solution is found. - */ - -/* - * Because there's no standalone read command what we do here instead - * is write a pattern to memory and then checking that memory address - * against that pattern - */ -wm 32 0x80000000 0xa5a5a5a5 -check 32 until_any_bit_set 0x80000000 0xa5a5a5a5 - -wm 32 0x400ae000 0x00000600 -wm 32 0x400ae000 0x00000601 - -check 32 until_any_bit_set 0x400ae140 0x100 - -CHECKPOINT(9) diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index bb858907a4..7076a6431f 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -2,242 +2,27 @@ soc vf610 loadaddr 0x80000000 dcdofs 0x400 -#define VF610_DDR_PAD_CTRL 0x00000180 /* 25 Ohm drive strength */ -#define VF610_DDR_PAD_CTRL_1 0x00010180 /* 25 Ohm drive strength + differential input */ +#include <mach/vf610-iomux-regs.h> +#include <mach/vf610-ddrmc-regs.h> -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x00210000 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00002000 -#define DDRMC_PHY_OFF 0x00000000 -#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 +#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg> +#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg> +#include <mach/flash-header/vf610-ddr-cr-default.imxcfg> -#define CHECKPOINT(n) wm 32 0x3f000000 n - -CHECKPOINT(1) - -/* ======================= Clock initialization =======================*/ - -/* - * Ungate all IP block clocks - */ -wm 32 0x4006b040 0xffffffff -wm 32 0x4006b044 0xffffffff -wm 32 0x4006b048 0xffffffff -wm 32 0x4006b04c 0xffffffff -wm 32 0x4006b050 0xffffffff -wm 32 0x4006b058 0xffffffff -wm 32 0x4006b05c 0xffffffff -wm 32 0x4006b060 0xffffffff -wm 32 0x4006b064 0xffffffff -wm 32 0x4006b068 0xffffffff -wm 32 0x4006b06c 0xffffffff - - -/* - * Turn PLL2 on - */ -wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */ - -CHECKPOINT(2) +wm 32 DDRMC_CR26 0x0c300068 +wm 32 DDRMC_CR31 0x006c0200 +wm 32 DDRMC_CR73 0x0a010100 /* - * Wait for PLLs to lock + * zii-vf610-dev derivatives come with 512MiB of RAM, so we need to + * adjust, DDR chip's capacity. */ -check 32 until_any_bit_set 0x40050030 0x80000000 - - -CHECKPOINT(3) - -clear_bits 32 0x4006b008 0x00000040 -set_bits 32 0x4006b008 0x00002000 - +wm 32 DDRMC_CR73 0x0a010100 +#include <mach/flash-header/vf610-ddr-phy-default.imxcfg> -/* ======================= DDR IOMUX =======================*/ - -CHECKPOINT(4) - -wm 32 0x40048220 0x00000180 -wm 32 0x40048224 0x00000180 -wm 32 0x40048228 0x00000180 -wm 32 0x4004822c 0x00000180 -wm 32 0x40048230 0x00000180 -wm 32 0x40048234 0x00000180 -wm 32 0x40048238 0x00000180 -wm 32 0x4004823c 0x00000180 -wm 32 0x40048240 0x00000180 -wm 32 0x40048244 0x00000180 -wm 32 0x40048248 0x00000180 -wm 32 0x4004824c 0x00000180 -wm 32 0x40048250 0x00000180 -wm 32 0x40048254 0x00000180 -wm 32 0x40048258 0x00000180 -wm 32 0x4004825c 0x00000180 -wm 32 0x40048260 0x00000180 -wm 32 0x40048264 0x00000180 -wm 32 0x40048268 0x00000180 -wm 32 0x4004826c 0x00000180 -wm 32 0x40048270 0x00000180 -wm 32 0x40048274 0x00000180 -wm 32 0x40048278 0x00000180 -wm 32 0x4004827c 0x00010180 -wm 32 0x40048280 0x00010180 -wm 32 0x40048284 0x00010180 -wm 32 0x40048288 0x00010180 -wm 32 0x4004828c 0x00010180 -wm 32 0x40048290 0x00010180 -wm 32 0x40048294 0x00010180 -wm 32 0x40048298 0x00010180 -wm 32 0x4004829c 0x00010180 -wm 32 0x400482a0 0x00010180 -wm 32 0x400482a4 0x00010180 -wm 32 0x400482a8 0x00010180 -wm 32 0x400482ac 0x00010180 -wm 32 0x400482b0 0x00010180 -wm 32 0x400482b4 0x00010180 -wm 32 0x400482b8 0x00010180 -wm 32 0x400482bc 0x00010180 -wm 32 0x400482c0 0x00010180 -wm 32 0x400482c4 0x00010180 -wm 32 0x400482c8 0x00010180 -wm 32 0x400482cc 0x00000180 -wm 32 0x400482d0 0x00000180 -wm 32 0x400482d4 0x00000180 -wm 32 0x400482d8 0x00000180 -wm 32 0x4004821c 0x00000180 - -/* ======================= DDR Controller =======================*/ - -CHECKPOINT(5) -wm 32 0x400ae000 0x00000600 -wm 32 0x400ae008 0x00000005 -wm 32 0x400ae028 0x00013880 -wm 32 0x400ae02c 0x00030d40 -wm 32 0x400ae030 0x00000506 -wm 32 0x400ae034 0x06040400 -wm 32 0x400ae038 0x1006040e -wm 32 0x400ae040 0x04040000 -wm 32 0x400ae044 0x006db00c -wm 32 0x400ae048 0x00000403 -wm 32 0x400ae050 0x01000000 -wm 32 0x400ae054 0x00060001 -wm 32 0x400ae058 0x000c0000 -wm 32 0x400ae05c 0x03000200 -wm 32 0x400ae060 0x00000006 -wm 32 0x400ae064 0x00010000 -wm 32 0x400ae068 0x0c300068 -wm 32 0x400ae070 0x00000000 -wm 32 0x400ae074 0x00000003 -wm 32 0x400ae078 0x0000000a -wm 32 0x400ae07c 0x006c0200 -wm 32 0x400ae084 0x00010000 -wm 32 0x400ae088 0x00050500 -wm 32 0x400ae098 0x00000000 -wm 32 0x400ae09c 0x04001002 -wm 32 0x400ae0a4 0x00000001 -wm 32 0x400ae0c0 0x00460420 -wm 32 0x400ae0c4 0x00000000 -wm 32 0x400ae0cc 0x00000000 -wm 32 0x400ae0e4 0x02000000 -wm 32 0x400ae108 0x01000200 -wm 32 0x400ae10c 0x00000040 -wm 32 0x400ae114 0x00000200 -wm 32 0x400ae118 0x00000040 -wm 32 0x400ae120 0x00000000 -wm 32 0x400ae124 0x0a010100 -wm 32 0x400ae128 0x01014040 -wm 32 0x400ae12c 0x01010101 -wm 32 0x400ae130 0x03030000 -wm 32 0x400ae134 0x01000101 -wm 32 0x400ae138 0x0700000c -wm 32 0x400ae13c 0x00000000 -wm 32 0x400ae148 0x10000000 -wm 32 0x400ae15c 0x01000000 -wm 32 0x400ae160 0x00040000 -wm 32 0x400ae164 0x00000002 -wm 32 0x400ae16c 0x00020000 -wm 32 0x400ae180 0x00002819 -wm 32 0x400ae184 0x01000000 -wm 32 0x400ae188 0x00000000 -wm 32 0x400ae18c 0x00000000 -wm 32 0x400ae198 0x00000000 -wm 32 0x400ae1a4 0x00000c00 -wm 32 0x400ae1a8 0x00000000 -wm 32 0x400ae1b8 0x0000000c -wm 32 0x400ae1c8 0x00000000 -wm 32 0x400ae1cc 0x00000000 -wm 32 0x400ae1d4 0x00000000 -wm 32 0x400ae1d8 0x01010000 -wm 32 0x400ae1e0 0x02020000 -wm 32 0x400ae1e4 0x00000202 -wm 32 0x400ae1e8 0x01010064 -wm 32 0x400ae1ec 0x00010101 -wm 32 0x400ae1f0 0x00000064 -wm 32 0x400ae1f8 0x00000800 -wm 32 0x400ae210 0x00000506 -wm 32 0x400ae224 0x00020000 -wm 32 0x400ae228 0x01000000 -wm 32 0x400ae22c 0x04070303 -wm 32 0x400ae230 0x00000040 -wm 32 0x400ae23c 0x06000080 -wm 32 0x400ae240 0x04070303 -wm 32 0x400ae244 0x00000040 -wm 32 0x400ae248 0x00000040 -wm 32 0x400ae24c 0x000f0000 -wm 32 0x400ae250 0x000f0000 -wm 32 0x400ae25c 0x00000101 -wm 32 0x400ae268 0x682c4000 -wm 32 0x400ae26c 0x00000012 -wm 32 0x400ae278 0x00000006 -wm 32 0x400ae284 0x00010202 - -/* ======================= DDR PHY =======================*/ - -CHECKPOINT(6) - -wm 32 0x400ae400 0x00002613 -wm 32 0x400ae440 0x00002613 -wm 32 0x400ae480 0x00002613 -wm 32 0x400ae404 0x00002615 -wm 32 0x400ae444 0x00002615 -wm 32 0x400ae408 0x00210000 -wm 32 0x400ae448 0x00210000 -wm 32 0x400ae488 0x00210000 -wm 32 0x400ae40c 0x0001012a -wm 32 0x400ae44c 0x0001012a -wm 32 0x400ae48c 0x0001012a -wm 32 0x400ae410 0x00002000 -wm 32 0x400ae450 0x00002000 -wm 32 0x400ae490 0x00002000 -wm 32 0x400ae4c4 0x00000000 -wm 32 0x400ae4c8 0x00001100 -wm 32 0x400ae4d0 0x00010101 -wm 32 0x400ae000 0x00000601 - -CHECKPOINT(7) +wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START check 32 until_any_bit_set 0x400ae140 0x100 -# check 32 until_any_bit_set 0x400ae42c 0x1 -# check 32 until_any_bit_set 0x400ae46c 0x1 -# check 32 until_any_bit_set 0x400ae4ac 0x1 - -CHECKPOINT(8) - -wm 32 0x80000000 0xa5a5a5a5 -check 32 until_any_bit_set 0x80000000 0xa5a5a5a5 - -wm 32 0x400ae000 0x00000600 -wm 32 0x400ae000 0x00000601 - -check 32 until_any_bit_set 0x400ae140 0x100 -# check 32 until_any_bit_set 0x400ae42c 0x1 -# check 32 until_any_bit_set 0x400ae46c 0x1 -# check 32 until_any_bit_set 0x400ae4ac 0x1 - -/* wm 32 0x3f040000 0xf0 - check 32 until_any_bit_set 0x3f040000 0x0f */ -CHECKPOINT(9) diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg new file mode 100644 index 0000000000..8c411ddc7e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg @@ -0,0 +1,131 @@ +/* + + The following table contains DDR3 memory timing parameters derived + form memory module (Samsung K4B4G1646E) datasheet: + +| CL | 6 | @400Mhz | +| WRLAT | 5 | | +| t_RC | 21 | | +| t_RRD | 4 | [5] | +| t_CCD | 4 | | +| t_FAW | 16(1KB page)/20(2KB page) | | +| t_RP | 6 | | +| t_WTR | 4 | [6] | +| t_RAS(MIN) | 15 | | +| t_MRD | 4 | | +| t_RTP | 4 | [1] | +| t_MOD | 12 | [7] | +| t_RAS(MAX) | 28080 | [8] | +| t_CKESR | 4 | [9] | +| t_CKE | 3 | [10] | +| t_RCD | 6 | | +| t_DAL | 12 | [11] | +| t_DDLK | 512 | | +| t_RP(AB) | 6 | n/a in datasheet | +| t_REFI | 3120 | | +| t_RFC | 44 @ 1Gb, 64@2Gb, 104@4Gb, 140@8Gb | | +| t_XP | 3 | [4] | +| t_XPDLL | 10 | [12] | +| t_XS | 48 @ 1Gb, 68@2Gb, 108@4Gb, 148@8Gb | [2] | +| t_XSDLL | 512 | | +| t_CKSRX | 5 | [3] | +| t_CKSRE | 5 | [3] | +| MR0 | | | +| MR1 | | | +| MR2 | | | +| MR3 | | | +| t_ZQoper | 256 | | +| t_ZQinit | 512 | | +| t_ZQCS | 64 | | +| ODTL_off | 3 | [14] | +| t_WLMRD | 40 | | +| t_WLDQSEN | 25 | | +| t_WR | 6 | | +| t_ODTH8(R) | 6 | n/a in datasheet | +| t_ODTH8(W) | 6 | | + + +[1] t_RTP = max(4nCK, 7.5ns) = max(10ns, 7.5ns)@400Mhz = 4nCK +[2] t_XS = max(5nCK, t_RFC + 10ns) +[3] t_CKSRX = t_CKSRE = max(5nCK, 10ns) = max(12.5ns, 7.5ns)@400Mhz = 5nCK +[4] t_XP = max(3nCK, 7.5ns) = max(7.5ns, 7.5ns)@400Mhz = 3nCK +[5] t_RRD = max(4nCK, 10ns) = max(10ns, 10ns)@400Mhz = 4nCK +[6] t_WTR = max(4nCK, 7.5ns) = 4nCK (see [1] for calculation) +[7] t_MOD = max(12nCK, 15ns) = max(30ns, 15ns)@400Mhz = 12nCK +[8] t_RAS(MAX) = 9 * t_REFI = 9 * 7.8us = 28080nCK +[9] t_CKESR = t_CKE(min) + 1tCK = 4nCK +[10] t_CKE = max(3nCK, 7.5ns) = 3nCK (see [4]) +[11] t_DAL = t_WR + roundup(t_RP/t_CK(AVG)) = 6nCK + 6nCK = 12nCK +[12] t_XPDLL = max(10nCK, 24ns) = max(25ns, 25ns)@400Mhz = 10nCK +[13] WRLAT = AL + CWL = 0 (not supported by controller) + 5nCK = 5nCK +[14] ODTL_off = WRLAT - 2 = 3nCK + +*/ + +wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3 +wm 32 DDRMC_CR02 0x00000005 +wm 32 DDRMC_CR10 0x00013880 +wm 32 DDRMC_CR11 0x00030d40 +wm 32 DDRMC_CR12 0x0000050c +wm 32 DDRMC_CR13 0x15040400 +wm 32 DDRMC_CR14 0x1406040f +wm 32 DDRMC_CR16 0x04040000 +wm 32 DDRMC_CR17 0x006db00c +wm 32 DDRMC_CR18 0x00000403 +wm 32 DDRMC_CR20 0x01000000 +wm 32 DDRMC_CR21 0x00060001 +wm 32 DDRMC_CR22 0x000c0000 +wm 32 DDRMC_CR23 0x03000200 +wm 32 DDRMC_CR24 0x00000006 +wm 32 DDRMC_CR25 0x00010000 +wm 32 DDRMC_CR26 0x0c30002c +wm 32 DDRMC_CR28 0x00000000 +wm 32 DDRMC_CR29 0x00000003 +wm 32 DDRMC_CR30 0x0000000a +wm 32 DDRMC_CR31 0x00300200 +wm 32 DDRMC_CR33 0x00010000 +wm 32 DDRMC_CR34 0x00050500 +wm 32 DDRMC_CR38 0x00000000 +wm 32 DDRMC_CR39 0x04001002 +wm 32 DDRMC_CR41 0x00000001 +wm 32 DDRMC_CR48 0x00460420 +wm 32 DDRMC_CR66 0x01000200 +wm 32 DDRMC_CR67 0x00000040 +wm 32 DDRMC_CR69 0x00000200 +wm 32 DDRMC_CR70 0x00000040 +wm 32 DDRMC_CR72 0x00000000 +wm 32 DDRMC_CR73 0x0a010300 +wm 32 DDRMC_CR74 0x01014040 +wm 32 DDRMC_CR75 0x01010101 +wm 32 DDRMC_CR76 0x03030100 +wm 32 DDRMC_CR77 0x01000101 +wm 32 DDRMC_CR78 0x0700000c +wm 32 DDRMC_CR79 0x00000000 +wm 32 DDRMC_CR82 0x10000000 +wm 32 DDRMC_CR87 0x01000000 +wm 32 DDRMC_CR88 0x00040000 +wm 32 DDRMC_CR89 0x00000002 +wm 32 DDRMC_CR91 0x00020000 +wm 32 DDRMC_CR96 0x00002819 +wm 32 DDRMC_CR117 0x00000000 +wm 32 DDRMC_CR118 0x01010000 +wm 32 DDRMC_CR120 0x02020000 +wm 32 DDRMC_CR121 0x00000202 +wm 32 DDRMC_CR122 0x01010064 +wm 32 DDRMC_CR123 0x00010101 +wm 32 DDRMC_CR124 0x00000064 +wm 32 DDRMC_CR126 0x00000800 +/* + * Despite the RM insisting on setting RDLAT_ADJ to CASLAT_LIN - 1 in + * two places: p 1459 (section 10.1.5.133 "Control Register 132 + * (DDRMC_CR132)") and p. 1587 (section 10.1.6.15.10 "Configure the + * 'output enable' of I/O Control") changing it from current 6 to + * recommended 5 results in non-working DDR. + */ +wm 32 DDRMC_CR132 0x00000506 +wm 32 DDRMC_CR137 0x00020000 +wm 32 DDRMC_CR138 0x01000100 +wm 32 DDRMC_CR154 0x682c4000 +wm 32 DDRMC_CR155 0x00000009 +wm 32 DDRMC_CR158 0x00000006 +wm 32 DDRMC_CR161 0x00010606
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg new file mode 100644 index 0000000000..e9d5ab0ca2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-phy-default.imxcfg @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * VFxxx shared DDR PHY DCD code. Intended use is to share code + * between all board that copy VF610 Tower Board DDR reference + * layout/design + * + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +#define DDRMC_PHY_DQ_TIMING 0x00002613 +#define DDRMC_PHY_DQS_TIMING 0x00002615 +#define DDRMC_PHY_CTRL 0x00210000 +#define DDRMC_PHY_MASTER_CTRL 0x0001012a +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 +#define DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE 0x00001100 + + +wm 32 DDRMC_PHY00 DDRMC_PHY_DQ_TIMING +wm 32 DDRMC_PHY16 DDRMC_PHY_DQ_TIMING +wm 32 DDRMC_PHY32 DDRMC_PHY_DQ_TIMING + +wm 32 DDRMC_PHY01 DDRMC_PHY_DQS_TIMING +wm 32 DDRMC_PHY17 DDRMC_PHY_DQS_TIMING + +wm 32 DDRMC_PHY02 DDRMC_PHY_CTRL +wm 32 DDRMC_PHY18 DDRMC_PHY_CTRL +wm 32 DDRMC_PHY34 DDRMC_PHY_CTRL + +wm 32 DDRMC_PHY03 DDRMC_PHY_MASTER_CTRL +wm 32 DDRMC_PHY19 DDRMC_PHY_MASTER_CTRL +wm 32 DDRMC_PHY35 DDRMC_PHY_MASTER_CTRL + +wm 32 DDRMC_PHY04 DDRMC_PHY_SLAVE_CTRL +wm 32 DDRMC_PHY20 DDRMC_PHY_SLAVE_CTRL +wm 32 DDRMC_PHY36 DDRMC_PHY_SLAVE_CTRL + +wm 32 DDRMC_PHY49 DDRMC_PHY_OFF +wm 32 DDRMC_PHY50 DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE +wm 32 DDRMC_PHY52 DDRMC_PHY_PROC_PAD_ODT diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg new file mode 100644 index 0000000000..74d119b59e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg @@ -0,0 +1,46 @@ +/* + * Ungate all IP block clocks + */ +wm 32 0x4006b040 0xffffffff +wm 32 0x4006b044 0xffffffff +wm 32 0x4006b048 0xffffffff +wm 32 0x4006b04c 0xffffffff +wm 32 0x4006b050 0xffffffff +wm 32 0x4006b058 0xffffffff +wm 32 0x4006b05c 0xffffffff +wm 32 0x4006b060 0xffffffff +wm 32 0x4006b064 0xffffffff +wm 32 0x4006b068 0xffffffff +wm 32 0x4006b06c 0xffffffff + +/* + * We have to options to clock DDR controller: + * + * - Use Core-A5 clock + * - Use PLL2 PFD2 clock + * + + * Using first option without changing PLL settings doesn't seem to be + * possible given that DDRMC requires minimum of 300Mhz and MaskROM + * configures it to be clocked at 264Mhz. Changing PLL1 settings + * proved to be challenging becuase MaskROM code executing this DCD + * will also be fetching the rest of the bootloader via some + * peripheral interface whose clock is derived from Cortex-A5 clock. + * + * As a result this DCD configuration code uses the second option of + * clocking DDR wiht PLL2 PFD2 clock output + * + * Turn PLL2 on + */ +wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */ + +/* + * Wait for PLLs to lock + */ +check 32 until_any_bit_set 0x40050030 0x80000000 + +/* + * Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output + */ +clear_bits 32 0x4006b008 0x00000040 +set_bits 32 0x4006b008 0x00002000 diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg new file mode 100644 index 0000000000..742275b92f --- /dev/null +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * VFxxx shared DDR IOMUX DCD code. Intended use is to share code + * between all board that copy VF610 Tower Board DDR reference + * layout/design + * + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +#define VF610_DDR_PAD_CTRL 0x00000180 /* 40 Ohm drive strength */ +#define VF610_DDR_PAD_CTRL_1 0x00010180 /* ditto + differential input */ + +wm 32 VF610_PAD_DDR_A15__DDR_A_15 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A14__DDR_A_14 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A13__DDR_A_13 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A12__DDR_A_12 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A11__DDR_A_11 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A10__DDR_A_10 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A9__DDR_A_9 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A8__DDR_A_8 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A7__DDR_A_7 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A6__DDR_A_6 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A5__DDR_A_5 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A4__DDR_A_4 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A3__DDR_A_3 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A2__DDR_A_2 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A1__DDR_A_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_A0__DDR_A_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_BA2__DDR_BA_2 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_BA1__DDR_BA_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_BA0__DDR_BA_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL_1 +wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1 VF610_DDR_PAD_CTRL_1 +wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0 VF610_DDR_PAD_CTRL_1 +wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_WE__DDR_WE_B VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_RESETB VF610_DDR_PAD_CTRL + +wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL +wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
\ No newline at end of file diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h new file mode 100644 index 0000000000..33c1aaddf3 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610-ddrmc-regs.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * VFxxx DDRMC register addresses definitions for use in DCD + * + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +#define DDRMC_CR00 0x400ae000 +#define DDRMC_CR02 0x400ae008 +#define DDRMC_CR10 0x400ae028 +#define DDRMC_CR11 0x400ae02c +#define DDRMC_CR12 0x400ae030 +#define DDRMC_CR13 0x400ae034 +#define DDRMC_CR14 0x400ae038 +#define DDRMC_CR16 0x400ae040 +#define DDRMC_CR17 0x400ae044 +#define DDRMC_CR18 0x400ae048 +#define DDRMC_CR20 0x400ae050 +#define DDRMC_CR21 0x400ae054 +#define DDRMC_CR22 0x400ae058 +#define DDRMC_CR23 0x400ae05c +#define DDRMC_CR24 0x400ae060 +#define DDRMC_CR25 0x400ae064 +#define DDRMC_CR26 0x400ae068 +#define DDRMC_CR28 0x400ae070 +#define DDRMC_CR29 0x400ae074 +#define DDRMC_CR30 0x400ae078 +#define DDRMC_CR31 0x400ae07c +#define DDRMC_CR33 0x400ae084 +#define DDRMC_CR34 0x400ae088 +#define DDRMC_CR38 0x400ae098 +#define DDRMC_CR39 0x400ae09c +#define DDRMC_CR41 0x400ae0a4 +#define DDRMC_CR48 0x400ae0c0 +#define DDRMC_CR49 0x400ae0c4 +#define DDRMC_CR51 0x400ae0cc +#define DDRMC_CR57 0x400ae0e4 +#define DDRMC_CR66 0x400ae108 +#define DDRMC_CR67 0x400ae10c +#define DDRMC_CR69 0x400ae114 +#define DDRMC_CR70 0x400ae118 +#define DDRMC_CR72 0x400ae120 +#define DDRMC_CR73 0x400ae124 +#define DDRMC_CR74 0x400ae128 +#define DDRMC_CR75 0x400ae12c +#define DDRMC_CR76 0x400ae130 +#define DDRMC_CR77 0x400ae134 +#define DDRMC_CR78 0x400ae138 +#define DDRMC_CR79 0x400ae13c +#define DDRMC_CR82 0x400ae148 +#define DDRMC_CR87 0x400ae15c +#define DDRMC_CR88 0x400ae160 +#define DDRMC_CR89 0x400ae164 +#define DDRMC_CR91 0x400ae16c +#define DDRMC_CR96 0x400ae180 +#define DDRMC_CR97 0x400ae184 +#define DDRMC_CR98 0x400ae188 +#define DDRMC_CR99 0x400ae18c +#define DDRMC_CR102 0x400ae198 +#define DDRMC_CR105 0x400ae1a4 +#define DDRMC_CR106 0x400ae1a8 +#define DDRMC_CR110 0x400ae1b8 +#define DDRMC_CR114 0x400ae1c8 +#define DDRMC_CR115 0x400ae1cc +#define DDRMC_CR117 0x400ae1d4 +#define DDRMC_CR118 0x400ae1d8 +#define DDRMC_CR120 0x400ae1e0 +#define DDRMC_CR121 0x400ae1e4 +#define DDRMC_CR122 0x400ae1e8 +#define DDRMC_CR123 0x400ae1ec +#define DDRMC_CR124 0x400ae1f0 +#define DDRMC_CR126 0x400ae1f8 +#define DDRMC_CR132 0x400ae210 +#define DDRMC_CR137 0x400ae224 +#define DDRMC_CR138 0x400ae228 +#define DDRMC_CR139 0x400ae22c +#define DDRMC_CR140 0x400ae230 +#define DDRMC_CR143 0x400ae23c +#define DDRMC_CR144 0x400ae240 +#define DDRMC_CR145 0x400ae244 +#define DDRMC_CR146 0x400ae248 +#define DDRMC_CR147 0x400ae24c +#define DDRMC_CR148 0x400ae250 +#define DDRMC_CR151 0x400ae25c +#define DDRMC_CR154 0x400ae268 +#define DDRMC_CR155 0x400ae26c +#define DDRMC_CR158 0x400ae278 +#define DDRMC_CR161 0x400ae284 + +#define DDRMC_CR00_DRAM_CLASS_DDR3 0x00000600 +#define DDRMC_CR00_DRAM_CLASS_DDR3_START 0x00000601 + +#define DDRMC_PHY00 0x400ae400 +#define DDRMC_PHY01 0x400ae404 +#define DDRMC_PHY02 0x400ae408 +#define DDRMC_PHY03 0x400ae40c +#define DDRMC_PHY04 0x400ae410 +#define DDRMC_PHY16 0x400ae440 +#define DDRMC_PHY17 0x400ae444 +#define DDRMC_PHY18 0x400ae448 +#define DDRMC_PHY19 0x400ae44c +#define DDRMC_PHY20 0x400ae450 +#define DDRMC_PHY32 0x400ae480 +#define DDRMC_PHY34 0x400ae488 +#define DDRMC_PHY35 0x400ae48c +#define DDRMC_PHY36 0x400ae490 +#define DDRMC_PHY49 0x400ae4c4 +#define DDRMC_PHY50 0x400ae4c8 +#define DDRMC_PHY52 0x400ae4d0 diff --git a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h new file mode 100644 index 0000000000..c85f0b74b9 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * VFxxx IOMUX register addresses definitions for use in DCD + * + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +#define VF610_PAD_DDR_RESETB 0x4004821c +#define VF610_PAD_DDR_A15__DDR_A_15 0x40048220 +#define VF610_PAD_DDR_A14__DDR_A_14 0x40048224 +#define VF610_PAD_DDR_A13__DDR_A_13 0x40048228 +#define VF610_PAD_DDR_A12__DDR_A_12 0x4004822c +#define VF610_PAD_DDR_A11__DDR_A_11 0x40048230 +#define VF610_PAD_DDR_A10__DDR_A_10 0x40048234 +#define VF610_PAD_DDR_A9__DDR_A_9 0x40048238 +#define VF610_PAD_DDR_A8__DDR_A_8 0x4004823c +#define VF610_PAD_DDR_A7__DDR_A_7 0x40048240 +#define VF610_PAD_DDR_A6__DDR_A_6 0x40048244 +#define VF610_PAD_DDR_A5__DDR_A_5 0x40048248 +#define VF610_PAD_DDR_A4__DDR_A_4 0x4004824c +#define VF610_PAD_DDR_A3__DDR_A_3 0x40048250 +#define VF610_PAD_DDR_A2__DDR_A_2 0x40048254 +#define VF610_PAD_DDR_A1__DDR_A_1 0x40048258 +#define VF610_PAD_DDR_A0__DDR_A_0 0x4004825c +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x40048260 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x40048264 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x40048268 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x4004826c +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x40048270 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x40048274 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x40048278 +#define VF610_PAD_DDR_D15__DDR_D_15 0x4004827c +#define VF610_PAD_DDR_D14__DDR_D_14 0x40048280 +#define VF610_PAD_DDR_D13__DDR_D_13 0x40048284 +#define VF610_PAD_DDR_D12__DDR_D_12 0x40048288 +#define VF610_PAD_DDR_D11__DDR_D_11 0x4004828c +#define VF610_PAD_DDR_D10__DDR_D_10 0x40048290 +#define VF610_PAD_DDR_D9__DDR_D_9 0x40048294 +#define VF610_PAD_DDR_D8__DDR_D_8 0x40048298 +#define VF610_PAD_DDR_D7__DDR_D_7 0x4004829c +#define VF610_PAD_DDR_D6__DDR_D_6 0x400482a0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x400482a4 +#define VF610_PAD_DDR_D4__DDR_D_4 0x400482a8 +#define VF610_PAD_DDR_D3__DDR_D_3 0x400482ac +#define VF610_PAD_DDR_D2__DDR_D_2 0x400482b0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x400482b4 +#define VF610_PAD_DDR_D0__DDR_D_0 0x400482b8 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x400482bc +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x400482c0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x400482c4 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x400482c8 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x400482cc +#define VF610_PAD_DDR_WE__DDR_WE_B 0x400482d0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x400482d4 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x400482d8 + +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x400482dc +#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 0x400482e0 |