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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-05-04 12:45:12 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 08:29:42 +0200 |
| commit | 4a0edad5d6b057fc117ab01727cc4ab682f36d4d (patch) | |
| tree | c23fc9a7d1a5421b9361fab921bc348ebb86ec09 | |
| parent | 7000b90984a0ca50443f1bd84c058e129c05f229 (diff) | |
| download | barebox-4a0edad5d6b057fc117ab01727cc4ab682f36d4d.tar.gz barebox-4a0edad5d6b057fc117ab01727cc4ab682f36d4d.tar.xz | |
RISC-V: asm: barebox-riscv-head: use load-offset of 0
Incoming RISC-V bootm implementation will use the same bootm handler for
booting both kernel and barebox. For this to work, the load offset in
the header needs to make sense. As non-generic DT barebox images have
enough knowledge about the platform to know where to place the stack,
they don't require a load offset, thus set it to zero.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210504104513.2640-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/riscv/include/asm/barebox-riscv-head.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/barebox-riscv-head.h b/arch/riscv/include/asm/barebox-riscv-head.h index f681ec8bce..a4c33472cd 100644 --- a/arch/riscv/include/asm/barebox-riscv-head.h +++ b/arch/riscv/include/asm/barebox-riscv-head.h @@ -30,7 +30,7 @@ #ifndef __barebox_riscv_head #define __barebox_riscv_head() \ - __barebox_riscv_header("nop", 0x55555555FFFFFFFF, 0x0, "barebox", "RSCV") + __barebox_riscv_header("nop", 0x0, 0x0, "barebox", "RSCV") #endif #endif /* __ASM_RISCV_HEAD_H */ |