diff options
| author | michael grassmann <michael.grassmann@phytec.de> | 2018-02-21 08:54:58 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-04-16 09:58:07 +0200 |
| commit | 4cdafeb43b44e0951112590bf49bfcb597e36569 (patch) | |
| tree | 592047efb3d08ccaa6204d2bfd833910b8f7eb71 | |
| parent | b6bebb7acabf24d4ef7d39d7736ca267583c5b5b (diff) | |
| download | barebox-4cdafeb43b44e0951112590bf49bfcb597e36569.tar.gz barebox-4cdafeb43b44e0951112590bf49bfcb597e36569.tar.xz | |
ARM: i.MX: phyFLEX: Change Ram Timing for i.MX6 DualLite\Solo (400 MHz)
The actual RAM timings in the phyFLEX BSP are generated for 528 MHz RAM clock
frequency, but the i.MX 6Solo/DualLite has only a 400 MHz RAM clock. These new
timings are accompanied by a speed increase of approx 10%.
Signed-off-by: michael grassmann <michael.grassmann@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
6 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg index 156eea971e..7b64e5d2fd 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000027; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index e76867004a..04c489d7e8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x8c929b85 + wm 32 0x021b000c 0x2d307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index 405529ddf8..b0f3faa0b7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 wm 32 MX6_MMDC_P0_MDMISC 0x00091740 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg index 26fe2b2f7d..ebe5a968b1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000B; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg index babb0dfe24..5f1585a40b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000F; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg index 6a46cd958f..5ff3ec69d7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ |