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authorAndrey Smirnov <andrew.smirnov@gmail.com>2019-02-11 18:27:49 -0800
committerSascha Hauer <s.hauer@pengutronix.de>2019-02-12 21:27:30 +0100
commit527422a4ad764c46bc958f91603e6b5e9860d4ba (patch)
tree5f4ec1ca3d9b4b7417ff3791d0f095c332baec36
parentb53cab812b92f8691089f7765857044aebba461e (diff)
downloadbarebox-527422a4ad764c46bc958f91603e6b5e9860d4ba.tar.gz
barebox-527422a4ad764c46bc958f91603e6b5e9860d4ba.tar.xz
ARM: i.MX8MQ: Add corner case for Rev 2.1 silicon
Rev 2.1 of i.MX8MQ silicon needs a special check different from predecessor. Add all of the neccessary code to do just that (based on similar code in vendor U-Boot tree). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/include/mach/imx8mq.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
index d69ec8145b..08dc06fdb4 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq.h
@@ -9,6 +9,8 @@
#define IMX8MQ_ROM_VERSION_A0 0x800
#define IMX8MQ_ROM_VERSION_B0 0x83C
+#define IMX8MQ_OCOTP_VERSION_B1 0x40
+#define IMX8MQ_OCOTP_VERSION_B1_MAGIC 0xff0055aa
#define MX8MQ_ANATOP_DIGPROG 0x6c
@@ -20,6 +22,7 @@
static inline int imx8mq_cpu_revision(void)
{
void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+ void __iomem *ocotp = IOMEM(MX8MQ_OCOTP_BASE_ADDR);
uint32_t revision = FIELD_GET(DIGPROG_MINOR,
readl(anatop + MX8MQ_ANATOP_DIGPROG));
uint32_t rom_version;
@@ -27,6 +30,12 @@ static inline int imx8mq_cpu_revision(void)
if (revision != IMX_CHIP_REV_1_0)
return revision;
/*
+ * For B1 chip we need to check OCOTP
+ */
+ if (readl(ocotp + IMX8MQ_OCOTP_VERSION_B1) ==
+ IMX8MQ_OCOTP_VERSION_B1_MAGIC)
+ return IMX_CHIP_REV_2_1;
+ /*
* For B0 chip, the DIGPROG is not updated, still TO1.0.
* we have to check ROM version further
*/