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| author | Teresa Remmet <t.remmet@phytec.de> | 2022-05-20 16:23:37 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-05-24 09:08:38 +0200 |
| commit | 6cf197fa61f9cc7dbc0f3de4c529b95071099fd1 (patch) | |
| tree | ce347794b5bc5c76e28254e2fd3be2c10e6b5cab | |
| parent | 870a0ef748ef3c4644a4072acf13e9f7f2e052f5 (diff) | |
| download | barebox-6cf197fa61f9cc7dbc0f3de4c529b95071099fd1.tar.gz barebox-6cf197fa61f9cc7dbc0f3de4c529b95071099fd1.tar.xz | |
arm: imx: mmdc_size: Increase row_max for imx8m
As DDRC_ADDRMAP7_ROW_B16 and DDRC_ADDRMAP7_ROW_B17 are used
now for the row size calculation we need to increase row_max to 18.
For LPDDR4 this only works in combination with ram timings
created with recent configuration spreadsheet versions.
With older versions the register DDRC_ADDRMAP7 may not be set and
calculation will lead to wrong results even with this patch.
Fixes: dad2b5636bd8 ("ARM: imx: Add imx8 support for 18 bit SDRAM row size handle")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Link: https://lore.barebox.org/20220520142337.993417-1-t.remmet@phytec.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/esdctl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 8dd0ddbbc9..b070ebc62a 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -488,7 +488,7 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) return imx_ddrc_sdram_size(ddrc, addrmap, 12, ARRAY_AND_SIZE(col_b), - 16, ARRAY_AND_SIZE(row_b), + 18, ARRAY_AND_SIZE(row_b), reduced_adress_space, true); } |