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authorLucas Stach <l.stach@pengutronix.de>2017-03-01 15:26:41 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-03-03 07:06:06 +0100
commit7497685b05706ee521ff2b38096c878e19bfcd61 (patch)
tree2b58424d41141611bc99fefb4f805626d8789f46
parentd92ce9b36a363ead3549343be800fe1dfac8ca2c (diff)
downloadbarebox-7497685b05706ee521ff2b38096c878e19bfcd61.tar.gz
ARM: execute DMB before trying to flush cache
The CPU write buffer needs to be coherent with the cache, otherwise we might flush stale entries with the actual data stuck in the cache. This is really important on newer CPU core with bigger write buffers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/cpu/cache-armv7.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index c19618b..aaa8bf8 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -68,6 +68,7 @@ ENTRY(v7_mmu_cache_flush)
ENDPROC(v7_mmu_cache_flush)
ENTRY(__v7_mmu_cache_flush_invalidate)
+ mcr p15, 0, r12, c7, c10, 5 @ DMB
mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1
tst r12, #0xf << 16 @ hierarchical cache (ARMv7)
mov r12, #0