Merge branch 'for-next/omap'

20 files changed, 303 insertions, 416 deletions

diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c
index de40f6c5af..7c94b19c9f 100644
--- a/arch/arm/boards/afi-gf/lowlevel.c
+++ b/arch/arm/boards/afi-gf/lowlevel.c
@@ -10,11 +10,12 @@
 #include <mach/am33xx-generic.h>
 #include <mach/am33xx-silicon.h>
 #include <mach/am33xx-clock.h>
+#include <mach/emif4.h>
+#include <mach/generic.h>
 #include <mach/sdrc.h>
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
 #include <mach/am33xx-mux.h>
-#include <mach/wdt.h>
 #include <debug_ll.h>
 
 /* AM335X EMIF Register values */
@@ -130,34 +131,35 @@ static void board_config_vtp(void)
 
 static void board_config_emif_ddr(void)
 {
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
 	u32 i;
 
 	/*Program EMIF0 CFG Registers*/
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
+
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
+
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
 	for (i = 0; i < 5000; i++) {
 
 	}
 
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
 }
 
 static void board_config_ddr(void)
@@ -209,13 +211,7 @@ static noinline int gf_sram_init(void)
 
 	fdt = __dtb_z_am335x_afi_gf_start;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200);
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index 544e396e03..ebec4b5419 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -15,7 +15,6 @@
 #include <mach/syslib.h>
 #include <mach/am33xx-mux.h>
 #include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
 
 #include "beaglebone.h"
 
@@ -118,13 +117,7 @@ static noinline int beaglebone_sram_init(void)
 	else
 		sdram_size = SZ_256M;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	if (is_beaglebone_black()) {
diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c b/arch/arm/boards/myirtech-x335x/lowlevel.c
index c43761ca23..c394253320 100644
--- a/arch/arm/boards/myirtech-x335x/lowlevel.c
+++ b/arch/arm/boards/myirtech-x335x/lowlevel.c
@@ -14,7 +14,6 @@
 #include <mach/generic.h>
 #include <mach/sdrc.h>
 #include <mach/sys_info.h>
-#include <mach/wdt.h>
 
 #define AM335X_ZCZ_1000		0x1c2f
 
@@ -70,13 +69,7 @@ ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2)
 
 	fdt = __dtb_z_am335x_myirtech_myd_start;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	mpupll = MPUPLL_M_800;
 	if (am33xx_get_cpu_rev() == AM335X_ES2_1) {
diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c
index bffb3ad880..8e506bc4ed 100644
--- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
@@ -15,7 +15,6 @@
 #include <mach/syslib.h>
 #include <mach/am33xx-mux.h>
 #include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
 #include <debug_ll.h>
 
 #include "ram-timings.h"
@@ -136,15 +135,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family)
 	struct am335x_sdram_timings *timing = NULL;
 	u32 ramsize;
 
-	/*
-	 * WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-
-	writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
 
diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c
index 7da2f92efb..2fa8a0fdc3 100644
--- a/arch/arm/boards/vscom-baltos/lowlevel.c
+++ b/arch/arm/boards/vscom-baltos/lowlevel.c
@@ -16,7 +16,6 @@
 #include <mach/syslib.h>
 #include <mach/am33xx-mux.h>
 #include <mach/am33xx-generic.h>
-#include <mach/wdt.h>
 
 static const struct am33xx_ddr_data ddr3_data = {
 	.rd_slave_ratio0        = 0x38,
@@ -86,13 +85,7 @@ static noinline void baltos_sram_init(void)
 
 	fdt = __dtb_z_am335x_baltos_minimal_start;
 
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE));
 
 	/* Setup the PLLs and the clocks for the peripherals */
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
index 7da8fd0331..9018bedf22 100644
--- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
+++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
@@ -16,7 +16,6 @@
 #include <mach/sdrc.h>
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
-#include <mach/wdt.h>
 #include <mach/omap3-mux.h>
 #include <mach/omap3-silicon.h>
 #include <mach/omap3-generic.h>
@@ -200,7 +199,7 @@ static noinline void pfc200_board_init(void)
 
 	/* Dont reconfigure SDRAM while running in SDRAM */
 	if (!in_sdram)
-		am35xx_emif4_init();
+		am35xx_emif4_init(IOMEM(OMAP3_SDRC_BASE));
 
 	barebox_arm_entry(0x80000000, SZ_256M, NULL);
 }
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index e81284ec3b..6b42196b23 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -16,13 +16,13 @@
 #
 #
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o
-pbl-$(CONFIG_ARCH_OMAP) += syslib.o
+pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_generic.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
-obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o
-obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o
+obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o emif4.o
+obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o emif4.o
 obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 3c5cdf065c..bfe5b3dc73 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -23,6 +23,7 @@
 #include <asm/barebox-arm.h>
 #include <mach/am33xx-silicon.h>
 #include <mach/am33xx-clock.h>
+#include <mach/emif4.h>
 #include <mach/generic.h>
 #include <mach/sys_info.h>
 #include <mach/am33xx-generic.h>
@@ -307,18 +308,20 @@ void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl)
 
 void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 {
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
+
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
 
 	if (regs->ocp_config)
-		writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG));
+		writel(regs->ocp_config, emif4 + EMIF4_OCP_CONFIG);
 
 	if (regs->zq_config) {
 		/*
@@ -326,75 +329,23 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 		 * about 570us for a delay, which will be long enough
 		 * to configure things.
 		 */
-		writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
+		writel(0x2800, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->zq_config, emif4 + EMIF4_ZQ_CONFIG);
 		writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
-		writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-		writel(regs->sdram_ref_ctrl,
-				AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->sdram_ref_ctrl,
-			AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
+		writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 	}
 
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-	writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-}
-
-/**
- * am335x_sdram_size - read back SDRAM size from sdram_config register
- *
- * @return: The SDRAM size
- */
-unsigned long am335x_sdram_size(void)
-{
-	int rows, cols, width, banks;
-	unsigned long size;
-	uint32_t sdram_config = readl(CM_EMIF_SDRAM_CONFIG);
-
-	rows = ((sdram_config >> 7) & 0x7) + 9;
-	cols = (sdram_config & 0x7) + 8;
-
-	switch ((sdram_config >> 14) & 0x3) {
-	case 0:
-		width = 4;
-		break;
-	case 1:
-		width = 2;
-		break;
-	default:
-		return 0;
-	}
-
-	switch ((sdram_config >> 4) & 0x7) {
-	case 0:
-		banks = 1;
-		break;
-	case 1:
-		banks = 2;
-		break;
-	case 2:
-		banks = 4;
-		break;
-	case 3:
-		banks = 8;
-		break;
-	default:
-		return 0;
-	}
-
-	size = (1 << rows) * (1 << cols) * banks * width;
-
-	debug("%s: sdram_config: 0x%08x cols: %2d rows: %2d width: %2d banks: %2d size: 0x%08lx\n",
-			__func__, sdram_config, cols, rows, width, banks, size);
-
-	return size;
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
+	writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
 }
 
 void __noreturn am335x_barebox_entry(void *boarddata)
 {
-	barebox_arm_entry(0x80000000, am335x_sdram_size(), boarddata);
+	barebox_arm_entry(0x80000000,
+			  emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)), boarddata);
 }
 
 void am33xx_config_io_ctrl(int ioctrl)
diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c
index 0f13a9deb6..e10e80ce31 100644
--- a/arch/arm/mach-omap/am33xx_scrm.c
+++ b/arch/arm/mach-omap/am33xx_scrm.c
@@ -21,10 +21,12 @@
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
 #include <mach/am33xx-silicon.h>
+#include <mach/emif4.h>
 
 static int am33xx_scrm_probe(struct device_d *dev)
 {
-	return arm_add_mem_device("ram0", 0x80000000, am335x_sdram_size());
+	return arm_add_mem_device("ram0", 0x80000000,
+				  emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE)));
 }
 
 static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = {
diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c
deleted file mode 100644
index 678a338fd6..0000000000
--- a/arch/arm/mach-omap/am35xx_emif4.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Author :
- *     Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <io.h>
-#include <mach/emif4.h>
-#include <mach/omap3-silicon.h>
-
-/*
- * do_pac200_emif4_init -
- *  - Init the emif4 module for DDR access
- *  - Early init routines, called from flash or SRAM.
- */
-void am35xx_emif4_init(void)
-{
-	unsigned int regval;
-	struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE);
-
-	/* Set the DDR PHY parameters in PHY ctrl registers */
-	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
-		EMIF4_DDR1_EXT_STRB_DIS);
-	writel(regval, &emif4_base->ddr_phyctrl1);
-	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
-	writel(0, &emif4_base->ddr_phyctrl2);
-
-	/* Reset the DDR PHY and wait till completed */
-	regval = readl(&emif4_base->sdram_iodft_tlgc);
-	regval |= (1 << 10);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-
-	/* Wait till that bit clears*/
-	while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10));
-
-	/* Re-verify the DDR PHY status*/
-	while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0);
-
-	regval |= (1 << 0);
-	writel(regval, &emif4_base->sdram_iodft_tlgc);
-
-	/* Set SDR timing registers */
-	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
-		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
-		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
-		EMIF4_TIM1_T_RP);
-	writel(regval, &emif4_base->sdram_time1);
-	writel(regval, &emif4_base->sdram_time1_shdw);
-
-	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
-		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
-		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
-	writel(regval, &emif4_base->sdram_time2);
-	writel(regval, &emif4_base->sdram_time2_shdw);
-
-	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
-	writel(regval, &emif4_base->sdram_time3);
-	writel(regval, &emif4_base->sdram_time3_shdw);
-
-	/* Set the PWR control register */
-	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
-		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
-	writel(regval, &emif4_base->sdram_pwr_mgmt);
-	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
-	/* Set the DDR refresh rate control register */
-	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
-	writel(regval, &emif4_base->sdram_refresh_ctrl);
-	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
-	/* set the SDRAM configuration register */
-	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
-		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
-		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
-		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
-		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
-		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
-	writel(regval, &emif4_base->sdram_config);
-}
diff --git a/arch/arm/mach-omap/emif4.c b/arch/arm/mach-omap/emif4.c
new file mode 100644
index 0000000000..b5a53e8c63
--- /dev/null
+++ b/arch/arm/mach-omap/emif4.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <io.h>
+#include <mach/emif4.h>
+
+/*
+ * AM35xx configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x7 << 12)
+#define EMIF4_TIM1_T_RC		(0xa << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1c << 16)
+#define EMIF4_TIM2_T_XSRD	(0xc8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x15 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0xf)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x257)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x3 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+/**
+ * emif4_sdram_size - read back SDRAM size from sdram_config register
+ *
+ * @return: The SDRAM size
+ */
+unsigned long emif4_sdram_size(const void __iomem *emif4)
+{
+	uint32_t sdram_config = readl(emif4 + EMIF4_SDRAM_CONFIG);
+	int rows, cols, width, banks;
+	unsigned long size;
+
+	rows = ((sdram_config >> 7) & 0x7) + 9;
+	cols = (sdram_config & 0x7) + 8;
+
+	switch ((sdram_config >> 14) & 0x3) {
+	case 0:
+		width = 4;
+		break;
+	case 1:
+		width = 2;
+		break;
+	default:
+		return 0;
+	}
+
+	switch ((sdram_config >> 4) & 0x7) {
+	case 0:
+		banks = 1;
+		break;
+	case 1:
+		banks = 2;
+		break;
+	case 2:
+		banks = 4;
+		break;
+	case 3:
+		banks = 8;
+		break;
+	default:
+		return 0;
+	}
+
+	size = (1 << rows) * (1 << cols) * banks * width;
+
+	debug("SDRAM_CONFIG: 0x%08x, cols: %2d, rows: %2d, width: %2d, banks: %2d, size: 0x%08lx\n",
+	      sdram_config, cols, rows, width, banks, size);
+
+	return size;
+}
+
+/*
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void am35xx_emif4_init(const void __iomem *emif4)
+{
+	unsigned int regval;
+
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	writel(0, emif4 + EMIF4_DDR_PHY_CTRL_2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(emif4 + EMIF4_IODFT_TLGC);
+	regval |= (1 << 10);
+	writel(regval, emif4 + EMIF4_IODFT_TLGC);
+
+	/* Wait till that bit clears*/
+	while (readl(emif4 + EMIF4_IODFT_TLGC) & (1 << 10));
+
+	/* Re-verify the DDR PHY status*/
+	while ((readl(emif4 + EMIF4_STATUS) & (1 << 2)) == 0x0);
+
+	regval |= (1 << 0);
+	writel(regval, emif4 + EMIF4_IODFT_TLGC);
+
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_1);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_2);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_3);
+	writel(regval, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL);
+	writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL_SHADOW);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL);
+	writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, emif4 + EMIF4_SDRAM_CONFIG);
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 0467dac03b..74b0b7638e 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -37,9 +37,6 @@
 #define AM33XX_GPIO2_BASE		(AM33XX_L4_PER_BASE + 0x1AC000 + 0x100)
 #define AM33XX_GPIO3_BASE		(AM33XX_L4_PER_BASE + 0x1AE000 + 0x100)
 
-/* EMFI Registers */
-#define AM33XX_EMFI0_BASE		0x4C000000
-
 #define AM33XX_DRAM_ADDR_SPACE_START	0x80000000
 #define AM33XX_DRAM_ADDR_SPACE_END	0xC0000000
 
@@ -83,8 +80,8 @@
 #define AM33XX_WDT_BASE			0x44E35000
 
 /* EMIF Base address */
-#define AM33XX_EMIF4_0_CFG_BASE		0x4C000000
-#define AM33XX_EMIF4_1_CFG_BASE		0x4D000000
+#define AM33XX_EMIF4_BASE		0x4c000000
+
 #define AM33XX_DMM_BASE			0x4E000000
 
 #define AM335X_CPSW_BASE		0x4A100000
@@ -97,30 +94,6 @@
 #define AM33XX_DMM_LISA_MAP__3		(AM33XX_DMM_BASE + 0x4C)
 #define AM33XX_DMM_PAT_BASE_ADDR	(AM33XX_DMM_BASE + 0x460)
 
-#define AM33XX_EMIF4_0_REG(REGNAME)	(AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME)
-#define AM33XX_EMIF4_1_REG(REGNAME)	(AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME)
-
-#define EMIF4_MOD_ID_REV		0x0
-#define EMIF4_SDRAM_STATUS		0x04
-#define EMIF4_SDRAM_CONFIG		0x08
-#define EMIF4_SDRAM_CONFIG2		0x0C
-#define EMIF4_SDRAM_REF_CTRL		0x10
-#define EMIF4_SDRAM_REF_CTRL_SHADOW	0x14
-#define EMIF4_SDRAM_TIM_1		0x18
-#define EMIF4_SDRAM_TIM_1_SHADOW	0x1C
-#define EMIF4_SDRAM_TIM_2		0x20
-#define EMIF4_SDRAM_TIM_2_SHADOW	0x24
-#define EMIF4_SDRAM_TIM_3		0x28
-#define EMIF4_SDRAM_TIM_3_SHADOW	0x2C
-#define EMIF0_SDRAM_MGMT_CTRL		0x38
-#define EMIF0_SDRAM_MGMT_CTRL_SHD	0x3C
-#define EMIF4_OCP_CONFIG		0x54
-#define EMIF4_ZQ_CONFIG			0xC8
-#define EMIF4_DDR_PHY_CTRL_1		0xE4
-#define EMIF4_DDR_PHY_CTRL_1_SHADOW	0xE8
-#define EMIF4_DDR_PHY_CTRL_2		0xEC
-#define EMIF4_IODFT_TLGC		0x60
-
 #define AM33XX_VTP0_CTRL_REG		0x44E10E0C
 #define AM33XX_VTP1_CTRL_REG		0x48140E10
 
@@ -247,7 +220,6 @@ void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr);
 void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
 			const struct am33xx_emif_regs *emif_regs,
 			const struct am33xx_ddr_data *ddr_data);
-unsigned long am335x_sdram_size(void);
 void am335x_barebox_entry(void *boarddata);
 
 #endif
diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h
index 1f9c2938a1..00702e60e8 100644
--- a/arch/arm/mach-omap/include/mach/emif4.h
+++ b/arch/arm/mach-omap/include/mach/emif4.h
@@ -24,82 +24,29 @@
 #ifndef _EMIF_H_
 #define _EMIF_H_
 
-/*
- * Configuration values
- */
-#define EMIF4_TIM1_T_RP		(0x3 << 25)
-#define EMIF4_TIM1_T_RCD	(0x3 << 21)
-#define EMIF4_TIM1_T_WR		(0x3 << 17)
-#define EMIF4_TIM1_T_RAS	(0x7 << 12) /* 8->7 */
-#define EMIF4_TIM1_T_RC		(0xA << 6)
-#define EMIF4_TIM1_T_RRD	(0x2 << 3)
-#define EMIF4_TIM1_T_WTR	(0x2)
-
-#define EMIF4_TIM2_T_XP		(0x2 << 28)
-#define EMIF4_TIM2_T_ODT	(0x0 << 25) /* 2? */
-#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
-#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
-#define EMIF4_TIM2_T_RTP	(0x1 << 3)
-#define EMIF4_TIM2_T_CKE	(0x2)
-
-#define EMIF4_TIM3_T_RFC	(0x15 << 4) /* 25->15 */
-#define EMIF4_TIM3_T_RAS_MAX	(0xf)	    /* 7->f */
-
-#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
-#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
-#define EMIF4_PWR_DPD_EN	(0x1 << 10)
-#define EMIF4_PWR_LP_MODE	(0x0 << 8)
-#define EMIF4_PWR_PM_TIM	(0x0)
-
-#define EMIF4_INITREF_DIS	(0x0 << 31)
-#define EMIF4_REFRESH_RATE	(0x257) /* 50f->257 */
-
-#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
-#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
-#define EMIF4_CFG_DDR_TERM	(0x3 << 24) /* --> 0x3 */
-#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
-#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
-#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
-#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
-#define EMIF4_CFG_CL		(0x5 << 10)
-#define EMIF4_CFG_ROWSIZE	(0x0 << 7) /* --> 0x4: a0..a12 */
-#define EMIF4_CFG_IBANK		(0x3 << 4)
-#define EMIF4_CFG_EBANK		(0x0 << 3)
-#define EMIF4_CFG_PGSIZE	(0x2)      /* 10 columns */
-
-/*
- * EMIF4 PHY Control 1 register configuration
- */
-#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
-#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
-#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
-#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
-#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
-
-struct emif4 {
-	unsigned int emif_mod_id_rev;
-	unsigned int sdram_sts;
-	unsigned int sdram_config;
-	unsigned int res1;
-	unsigned int sdram_refresh_ctrl;
-	unsigned int sdram_refresh_ctrl_shdw;
-	unsigned int sdram_time1;
-	unsigned int sdram_time1_shdw;
-	unsigned int sdram_time2;
-	unsigned int sdram_time2_shdw;
-	unsigned int sdram_time3;
-	unsigned int sdram_time3_shdw;
-	unsigned char res2[8];
-	unsigned int sdram_pwr_mgmt;
-	unsigned int sdram_pwr_mgmt_shdw;
-	unsigned char res3[32];
-	unsigned int sdram_iodft_tlgc;
-	unsigned char res4[128];
-	unsigned int ddr_phyctrl1;
-	unsigned int ddr_phyctrl1_shdw;
-	unsigned int ddr_phyctrl2;
-};
-
-void am35xx_emif4_init(void);
+#define EMIF4_MOD_ID_REV					0x0
+#define EMIF4_STATUS						0x04
+#define EMIF4_SDRAM_CONFIG					0x08
+#define EMIF4_SDRAM_CONFIG2					0x0c
+#define EMIF4_SDRAM_REF_CTRL					0x10
+#define EMIF4_SDRAM_REF_CTRL_SHADOW				0x14
+#define EMIF4_SDRAM_TIM_1					0x18
+#define EMIF4_SDRAM_TIM_1_SHADOW				0x1c
+#define EMIF4_SDRAM_TIM_2					0x20
+#define EMIF4_SDRAM_TIM_2_SHADOW				0x24
+#define EMIF4_SDRAM_TIM_3					0x28
+#define EMIF4_SDRAM_TIM_3_SHADOW				0x2c
+#define EMIF4_POWER_MANAGEMENT_CTRL				0x38
+#define EMIF4_POWER_MANAGEMENT_CTRL_SHADOW			0x3c
+#define EMIF4_OCP_CONFIG					0x54
+#define EMIF4_ZQ_CONFIG						0xc8
+#define EMIF4_DDR_PHY_CTRL_1					0xe4
+#define EMIF4_DDR_PHY_CTRL_1_SHADOW				0xe8
+#define EMIF4_DDR_PHY_CTRL_2					0xec
+#define EMIF4_IODFT_TLGC					0x60
+
+unsigned long emif4_sdram_size(const void __iomem *emif4);
+
+void am35xx_emif4_init(const void __iomem *emif4);
 
 #endif /* endif _EMIF_H_ */
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
index fa391c8d48..8b2b7a4f0c 100644
--- a/arch/arm/mach-omap/include/mach/generic.h
+++ b/arch/arm/mach-omap/include/mach/generic.h
@@ -79,6 +79,8 @@ static inline int omap_set_mmc_dev(const char *mmcdev)
 
 void __noreturn omap_start_barebox(void *barebox);
 
+void omap_watchdog_disable(const void __iomem *wdt);
+
 void omap_set_bootmmc_devname(const char *devname);
 const char *omap_get_bootmmc_devname(void);
 
diff --git a/arch/arm/mach-omap/include/mach/wdt.h b/arch/arm/mach-omap/include/mach/wdt.h
deleted file mode 100644
index 9a5288d386..0000000000
--- a/arch/arm/mach-omap/include/mach/wdt.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * @file
- * @brief This file contains the Watchdog timer specific register definitions
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Nishanth Menon <x0nishan@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_OMAP_WDT_H
-#define __ASM_ARCH_OMAP_WDT_H
-
-/** Watchdog Register defines */
-#define OMAP3_WDT_REG(REGNAME)	(OMAP3_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME)
-#define AM33XX_WDT_REG(REGNAME)	(AM33XX_WDT_BASE + OMAP_WDT_##REGNAME)
-
-#define OMAP_WDT_WIDR		(0x000)
-#define OMAP_WDT_SYSCONFIG	(0x010)
-#define OMAP_WDT_WD_SYSSTATUS	(0x014)
-#define OMAP_WDT_WISR		(0x018)
-#define OMAP_WDT_WIER		(0x01C)
-#define OMAP_WDT_WCLR		(0x024)
-#define OMAP_WDT_WCRR		(0x028)
-#define OMAP_WDT_WLDR		(0x02C)
-#define OMAP_WDT_WTGR		(0x030)
-#define OMAP_WDT_WWPS		(0x034)
-#define OMAP_WDT_WSPR		(0x048)
-
-/* Unlock Code for Watchdog timer to disable the same */
-#define WDT_DISABLE_CODE1	0xAAAA
-#define WDT_DISABLE_CODE2	0x5555
-
-#endif /* __ASM_ARCH_OMAP_WDT_H */
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 3f6a346277..69f2d51a62 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -40,7 +40,6 @@
 #include <mach/omap3-smx.h>
 #include <mach/clocks.h>
 #include <mach/omap3-clock.h>
-#include <mach/wdt.h>
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
 #include <mach/omap3-generic.h>
@@ -379,19 +378,10 @@ static void secureworld_exit(void)
  */
 static void watchdog_init(void)
 {
-	int pending = 1;
-
 	sr32(OMAP3_CM_REG(FCLKEN_WKUP), 5, 1, 1);
 	sr32(OMAP3_CM_REG(ICLKEN_WKUP), 5, 1, 1);
-	wait_on_value((0x1 << 5), 0x20, OMAP3_CM_REG(IDLEST_WKUP), 5);
-
-	writel(WDT_DISABLE_CODE1, OMAP3_WDT_REG(WSPR));
-
-	do {
-		pending = readl(OMAP3_WDT_REG(WWPS));
-	} while (pending);
 
-	writel(WDT_DISABLE_CODE2, OMAP3_WDT_REG(WSPR));
+	omap_watchdog_disable(IOMEM(OMAP3_MPU_WDTIMER_BASE));
 }
 
 /**
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 406b686318..6d165b7f68 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -65,18 +65,6 @@ void omap4_set_warmboot_order(u32 *device_list)
 	writel(OMAP44XX_SAR_CH_START, OMAP44XX_SAR_CH_ADDRESS);
 }
 
-#define WATCHDOG_WSPR	0x48
-#define WATCHDOG_WWPS	0x34
-
-static void wait_for_command_complete(void)
-{
-	int pending = 1;
-
-	do {
-		pending = readl(OMAP44XX_WDT2_BASE + WATCHDOG_WWPS);
-	} while (pending);
-}
-
 /* EMIF */
 #define EMIF_MOD_ID_REV			0x0000
 #define EMIF_STATUS			0x0004
@@ -463,14 +451,8 @@ unsigned int omap4_revision(void)
  */
 static int watchdog_init(void)
 {
-	void __iomem *wd2_base = (void *)OMAP44XX_WDT2_BASE;
-
-	if (!cpu_is_omap4())
-		return 0;
-
-	writel(WD_UNLOCK1, wd2_base + WATCHDOG_WSPR);
-	wait_for_command_complete();
-	writel(WD_UNLOCK2, wd2_base + WATCHDOG_WSPR);
+	if (cpu_is_omap4())
+		omap_watchdog_disable(IOMEM(OMAP44XX_WDT2_BASE));
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c
index a1c0aeb595..6bb26a6ef0 100644
--- a/arch/arm/mach-omap/omap_generic.c
+++ b/arch/arm/mach-omap/omap_generic.c
@@ -70,6 +70,24 @@ void __noreturn omap_start_barebox(void *barebox)
 	hang();
 }
 
+#define OMAP_WDT_WWPS		0x34
+#define OMAP_WDT_WSPR		0x48
+#define WDT_DISABLE_CODE1	0xaaaa
+#define WDT_DISABLE_CODE2	0x5555
+
+void omap_watchdog_disable(const void __iomem *wdt)
+{
+	/* WDT is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	__raw_writel(WDT_DISABLE_CODE1, wdt + OMAP_WDT_WSPR);
+
+	do {
+	} while (__raw_readl(wdt + OMAP_WDT_WWPS));
+
+	__raw_writel(WDT_DISABLE_CODE2, wdt + OMAP_WDT_WSPR);
+}
+
 #ifdef CONFIG_BOOTM
 static int do_bootm_omap_barebox(struct image_data *data)
 {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9d4a534580..6fda32d44c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -92,13 +92,6 @@ config DRIVER_SERIAL_ATMEL
 	default y
 	bool "Atmel serial driver"
 
-config DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS
-	bool "OMAP Extensions for NS16550"
-	depends on DRIVER_SERIAL_NS16550
-	depends on ARCH_OMAP
-	help
-	  Say Y here if you are using OMAP extensions to NS16550
-
 config DRIVER_SERIAL_NS16550_PCI
 	depends on DRIVER_SERIAL_NS16550
 	depends on PCI
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 8da53ab5aa..f7cab8db4b 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -46,6 +46,7 @@ struct ns16550_drvdata {
         void (*init_port)(struct console_device *cdev);
         const char *linux_console_name;
         const char *linux_earlycon_name;
+	unsigned int clk_default;
 };
 
 static inline struct ns16550_priv *to_ns16550_priv(struct console_device *cdev)
@@ -371,6 +372,12 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
 	.linux_earlycon_name = "omap8250",
 };
 
+static __maybe_unused struct ns16550_drvdata am43xx_drvdata = {
+	.init_port = ns16550_omap_init_port,
+	.linux_console_name = "ttyO",
+	.clk_default = 48000000,
+};
+
 static __maybe_unused struct ns16550_drvdata jz_drvdata = {
 	.init_port = ns16550_jz_init_port,
 	.linux_earlycon_name = "jz4740_uart",
@@ -488,6 +495,9 @@ static int ns16550_probe(struct device_d *dev)
 	else
 		ns16550_probe_dt(dev, priv);
 
+	if (devtype->clk_default && !priv->plat.clock)
+		priv->plat.clock = devtype->clk_default;
+
 	if (!priv->plat.clock) {
 		priv->clk = clk_get(dev, NULL);
 		if (IS_ERR(priv->clk)) {
@@ -536,16 +546,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 		.data = &ns16450_drvdata,
 	}, {
 		.compatible = "ns16550a",
-		.data = &ns16550_drvdata,
 	}, {
 		.compatible = "snps,dw-apb-uart",
-		.data = &ns16550_drvdata,
 	}, {
 		.compatible = "marvell,armada-38x-uart",
-		.data = &ns16550_drvdata,
 	}, {
 		.compatible = "nvidia,tegra20-uart",
-		.data = &ns16550_drvdata,
 	},
 #if IS_ENABLED(CONFIG_ARCH_OMAP)
 	{
@@ -557,6 +563,9 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 	}, {
 		.compatible = "ti,omap4-uart",
 		.data = &omap_drvdata,
+	}, {
+		.compatible = "ti,am4372-uart",
+		.data = &am43xx_drvdata,
 	},
 #endif
 #if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)