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authorSascha Hauer <s.hauer@pengutronix.de>2013-09-05 10:40:04 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-09-05 10:40:04 +0200
commit7f6b6d25d899fea83412255d1d819e3b6450f144 (patch)
tree4da546d3b4045c842af7ccad3004c6476cb4d523
parent1729b1798e1bfd4614a9cf7cf651cee8b6923283 (diff)
parentf1cf4433bfc2d2e7bfdab8eacc401a0ccf2fe08d (diff)
downloadbarebox-7f6b6d25d899fea83412255d1d819e3b6450f144.tar.gz
barebox-7f6b6d25d899fea83412255d1d819e3b6450f144.tar.xz
Merge branch 'for-next/omap'
Conflicts: arch/arm/boards/pcm051/env/config
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boards/archosg9/lowlevel.c3
-rw-r--r--arch/arm/boards/beagle/lowlevel.c3
-rw-r--r--arch/arm/boards/beaglebone/beaglebone.h9
-rw-r--r--arch/arm/boards/beaglebone/board.c70
-rw-r--r--arch/arm/boards/beaglebone/lowlevel.c311
-rw-r--r--arch/arm/boards/omap343xdsp/lowlevel.c3
-rw-r--r--arch/arm/boards/omap3evm/lowlevel.c3
-rw-r--r--arch/arm/boards/panda/lowlevel.c3
-rw-r--r--arch/arm/boards/pcm049/lowlevel.c3
-rw-r--r--arch/arm/boards/pcm051/board.c11
-rw-r--r--arch/arm/boards/pcm051/env/boot/mmc (renamed from arch/arm/boards/pcm051/env/boot/sd)0
-rw-r--r--arch/arm/boards/pcm051/env/boot/nand (renamed from arch/arm/boards/pcm051/env/boot/nand-ubi)2
-rw-r--r--arch/arm/boards/pcm051/env/boot/spi11
-rw-r--r--arch/arm/boards/pcm051/env/boot/spi-nor12
-rw-r--r--arch/arm/boards/pcm051/env/config20
-rw-r--r--arch/arm/boards/pcm051/env/config-board7
-rw-r--r--arch/arm/boards/pcm051/lowlevel.c214
-rw-r--r--arch/arm/boards/pcm051/mux.c23
-rw-r--r--arch/arm/boards/pcm051/mux.h1
-rw-r--r--arch/arm/boards/phycard-a-l1/lowlevel.c3
-rw-r--r--arch/arm/boards/phycard-a-xl2/lowlevel.c3
-rw-r--r--arch/arm/boards/tqma6x/lowlevel.c4
-rw-r--r--arch/arm/configs/am335x_beaglebone_defconfig17
-rw-r--r--arch/arm/configs/am335x_beaglebone_mlo_small_defconfig6
-rw-r--r--arch/arm/configs/pcm051_defconfig1
-rw-r--r--arch/arm/configs/pcm051_mlo_defconfig2
-rw-r--r--arch/arm/cpu/cpuinfo.c33
-rw-r--r--arch/arm/mach-imx/include/mach/debug_ll.h4
-rw-r--r--arch/arm/mach-omap/Kconfig8
-rw-r--r--arch/arm/mach-omap/Makefile1
-rw-r--r--arch/arm/mach-omap/am33xx_bbu_spi_mlo.c88
-rw-r--r--arch/arm/mach-omap/am33xx_clock.c28
-rw-r--r--arch/arm/mach-omap/am33xx_generic.c199
-rw-r--r--arch/arm/mach-omap/include/mach/am33xx-clock.h11
-rw-r--r--arch/arm/mach-omap/include/mach/am33xx-devices.h6
-rw-r--r--arch/arm/mach-omap/include/mach/am33xx-generic.h19
-rw-r--r--arch/arm/mach-omap/include/mach/am33xx-silicon.h52
-rw-r--r--arch/arm/mach-omap/include/mach/bbu.h15
-rw-r--r--arch/arm/mach-omap/include/mach/debug_ll.h4
-rw-r--r--arch/arm/mach-omap/include/mach/generic.h10
-rw-r--r--arch/arm/mach-omap/include/mach/omap3-generic.h21
-rw-r--r--arch/arm/mach-omap/include/mach/omap4-generic.h21
-rw-r--r--arch/arm/mach-omap/include/mach/omap_hsmmc.h1
-rw-r--r--arch/arm/mach-omap/include/mach/sys_info.h10
-rw-r--r--arch/arm/mach-omap/omap_generic.c31
-rw-r--r--arch/arm/mach-omap/xload.c19
-rw-r--r--arch/mips/boot/main_entry-pbl.c2
-rw-r--r--common/console.c8
-rw-r--r--common/console_simple.c2
-rw-r--r--drivers/mci/omap_hsmmc.c26
-rw-r--r--include/debug_ll.h61
52 files changed, 920 insertions, 507 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4f45d57ad2..590a0d8f7b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -165,7 +165,7 @@ KBUILD_IMAGE := barebox.ubl
endif
quiet_cmd_am35xx_spi_image = SPI-IMG $@
- cmd_am35xx_spi_image = scripts/mk-am35xx-spi-image $< > $@
+ cmd_am35xx_spi_image = scripts/mk-am35xx-spi-image -a $(TEXT_BASE) $< > $@
barebox.spi: $(KBUILD_BINARY) FORCE
$(call if_changed,am35xx_spi_image)
diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index 8be345b531..6c939928d6 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -17,6 +17,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -67,7 +68,7 @@ static noinline void archosg9_init_lowlevel(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
index ef7e3c0a3e..ad46386d59 100644
--- a/arch/arm/boards/beagle/lowlevel.c
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -6,6 +6,7 @@
#include <mach/control.h>
#include <mach/generic.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
#include <mach/syslib.h>
@@ -182,7 +183,7 @@ static int beagle_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/beaglebone/beaglebone.h b/arch/arm/boards/beaglebone/beaglebone.h
new file mode 100644
index 0000000000..25c5b0eebc
--- /dev/null
+++ b/arch/arm/boards/beaglebone/beaglebone.h
@@ -0,0 +1,9 @@
+#ifndef __BOARD_BEAGLEBONE_H
+#define __BOARD_BEAGLEBONE_H
+
+static inline int is_beaglebone_black(void)
+{
+ return am33xx_get_cpu_rev() != AM335X_ES1_0;
+}
+
+#endif /* __BOARD_BEAGLEBONE_H */
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index 52b3ec8f5c..dfeb47cee2 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -26,10 +26,13 @@
#include <init.h>
#include <driver.h>
#include <envfs.h>
+#include <environment.h>
+#include <globalvar.h>
#include <sizes.h>
#include <io.h>
#include <ns16550.h>
#include <net.h>
+#include <bootsource.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/am33xx-silicon.h>
@@ -49,6 +52,8 @@
#include <mach/am33xx-generic.h>
#include <mach/cpsw.h>
+#include "beaglebone.h"
+
#ifdef CONFIG_DRIVER_SERIAL_NS16550
/**
@@ -71,7 +76,10 @@ console_initcall(beaglebone_console_init);
static int beaglebone_mem_init(void)
{
- omap_add_ram0(SZ_256M);
+ if (is_beaglebone_black())
+ omap_add_ram0(SZ_512M);
+ else
+ omap_add_ram0(SZ_256M);
return 0;
}
@@ -100,16 +108,72 @@ static void beaglebone_eth_init(void)
am33xx_add_cpsw(&cpsw_data);
}
+static struct i2c_board_info i2c0_devices[] = {
+ {
+ I2C_BOARD_INFO("24c256", 0x50)
+ },
+};
+
+static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE)}, /* MMC1_DAT4 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {-1},
+};
+
+static struct omap_hsmmc_platform_data beaglebone_sd = {
+ .devname = "sd",
+};
+
+static struct omap_hsmmc_platform_data beaglebone_emmc = {
+ .devname = "emmc",
+};
+
static int beaglebone_devices_init(void)
{
- am33xx_add_mmc0(NULL);
+ am33xx_enable_mmc0_pin_mux();
+ am33xx_add_mmc0(&beaglebone_sd);
+
+ if (is_beaglebone_black()) {
+ configure_module_pin_mux(mmc1_pin_mux);
+ am33xx_add_mmc1(&beaglebone_emmc);
+ }
+
+ if (bootsource_get() == BOOTSOURCE_MMC) {
+ if (bootsource_get_instance() == 0)
+ omap_set_bootmmc_devname("sd");
+ else
+ omap_set_bootmmc_devname("emmc");
+ }
am33xx_enable_i2c0_pin_mux();
+ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+ am33xx_add_i2c0(NULL);
+
beaglebone_eth_init();
+ return 0;
+}
+device_initcall(beaglebone_devices_init);
+
+static int beaglebone_env_init(void)
+{
+ int black = is_beaglebone_black();
+
+ globalvar_add_simple("board.variant", black ? "boneblack" : "bone");
+
+ printf("detected 'BeagleBone %s'\n", black ? "Black" : "White");
+
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_BEAGLEBONE);
return 0;
}
-device_initcall(beaglebone_devices_init);
+late_initcall(beaglebone_env_init);
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index d871ca1504..2ff7c7169c 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -1,6 +1,7 @@
#include <init.h>
#include <sizes.h>
#include <io.h>
+#include <debug_ll.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/am33xx-silicon.h>
@@ -10,213 +11,96 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/am33xx-mux.h>
+#include <mach/am33xx-generic.h>
#include <mach/wdt.h>
-/* UART Defines */
-#define UART_SYSCFG_OFFSET (0x54)
-#define UART_SYSSTS_OFFSET (0x58)
+#include "beaglebone.h"
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-/* AM335X EMIF Register values */
-#define EMIF_SDMGT 0x80000000
-#define EMIF_SDRAM 0x00004650
-#define EMIF_PHYCFG 0x2
-#define DDR_PHY_RESET (0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN 0x1
-#define DDR_PHY_READY (0x1 << 2)
-#define VTP_CTRL_READY (0x1 << 5)
-#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_LOCK_EN (0x1 << 4)
-#define VTP_CTRL_START_EN (0x1)
-#define DDR2_RATIO 0x80 /* for mDDR */
-#define CMD_FORCE 0x00 /* common #def */
-#define CMD_DELAY 0x00
-
-#define EMIF_READ_LATENCY 0x05
-#define EMIF_TIM1 0x0666B3D6
-#define EMIF_TIM2 0x143731DA
-#define EMIF_TIM3 0x00000347
-#define EMIF_SDCFG 0x43805332
-#define EMIF_SDREF 0x0000081a
-#define DDR2_DLL_LOCK_DIFF 0x0
#define DDR2_RD_DQS 0x12
#define DDR2_PHY_FIFO_WE 0x80
-
-#define DDR2_INVERT_CLKOUT 0x00
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
-#define PHY_RANK0_DELAY 0x01
-#define PHY_DLL_LOCK_DIFF 0x0
-#define DDR_IOCTRL_VALUE 0x18B
-
-static void beaglebone_data_macro_config(int dataMacroNum)
-{
- u32 BaseAddrOffset = 0x00;
-
- if (dataMacroNum == 1)
- BaseAddrOffset = 0xA4;
-
- __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_RD_DQS>>2,
- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_WR_DQS>>2,
- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
- (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_WRLVL>>2,
- (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
- (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_GATELVL>>2,
- (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_FIFO_WE>>2,
- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_WR_DATA>>2,
- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(PHY_DLL_LOCK_DIFF,
- (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
-}
-
-static void beaglebone_cmd_macro_config(void)
-{
- __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
-
- __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
-
- __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
-}
-
-static void beaglebone_config_vtp(void)
-{
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
- AM33XX_VTP0_CTRL_REG);
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
- AM33XX_VTP0_CTRL_REG);
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
- AM33XX_VTP0_CTRL_REG);
-
- /* Poll for READY */
- while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
-}
-
-static void beaglebone_config_emif_ddr2(void)
-{
- u32 i;
-
- /*Program EMIF0 CFG Registers*/
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
- for (i = 0; i < 5000; i++) {
-
- }
-
- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-}
-
-static void beaglebone_config_ddr(void)
-{
- enable_ddr_clocks();
-
- beaglebone_config_vtp();
-
- beaglebone_cmd_macro_config();
- beaglebone_data_macro_config(0);
- beaglebone_data_macro_config(1);
-
- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
-
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
-
- __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
- __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
-
- beaglebone_config_emif_ddr2();
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void beaglebone_sram_init(void)
-{
- u32 regVal, uart_base;
-
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init(MPUPLL_M_500);
-
- beaglebone_config_ddr();
-
- /* UART softreset */
- uart_base = AM33XX_UART0_BASE;
-
- regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
- regVal |= UART_RESET;
- __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
- while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
-
- /* Disable smart idle */
- regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
- regVal |= UART_SMART_IDLE_EN;
- __raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
-}
+static const struct am33xx_cmd_control ddr2_cmd_ctrl = {
+ .slave_ratio0 = 0x80,
+ .dll_lock_diff0 = 0x0,
+ .invert_clkout0 = 0x0,
+ .slave_ratio1 = 0x80,
+ .dll_lock_diff1 = 0x0,
+ .invert_clkout1 = 0x0,
+ .slave_ratio2 = 0x80,
+ .dll_lock_diff2 = 0x0,
+ .invert_clkout2 = 0x0,
+};
+
+static const struct am33xx_emif_regs ddr2_regs = {
+ .emif_read_latency = 0x5,
+ .emif_tim1 = 0x0666B3D6,
+ .emif_tim2 = 0x143731DA,
+ .emif_tim3 = 0x00000347,
+ .sdram_config = 0x43805332,
+ .sdram_config2 = 0x43805332,
+ .sdram_ref_ctrl = 0x0000081a,
+};
+
+static const struct am33xx_ddr_data ddr2_data = {
+ .rd_slave_ratio0 = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
+ (DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
+ .wr_dqs_slave_ratio0 = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
+ (DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
+ .wrlvl_init_ratio0 = (DDR2_PHY_WRLVL << 30) |
+ (DDR2_PHY_WRLVL << 20) |
+ (DDR2_PHY_WRLVL << 10) |
+ (DDR2_PHY_WRLVL << 0),
+ .gatelvl_init_ratio0 = (DDR2_PHY_GATELVL << 30) |
+ (DDR2_PHY_GATELVL << 20) |
+ (DDR2_PHY_GATELVL << 10) |
+ (DDR2_PHY_GATELVL << 0),
+ .fifo_we_slave_ratio0 = (DDR2_PHY_FIFO_WE << 30) |
+ (DDR2_PHY_FIFO_WE << 20) |
+ (DDR2_PHY_FIFO_WE << 10) |
+ (DDR2_PHY_FIFO_WE << 0),
+ .wr_slave_ratio0 = (DDR2_PHY_WR_DATA << 30) |
+ (DDR2_PHY_WR_DATA << 20) |
+ (DDR2_PHY_WR_DATA << 10) |
+ (DDR2_PHY_WR_DATA << 0),
+ .use_rank0_delay = 0x01,
+ .dll_lock_diff0 = 0x0,
+};
+
+static const struct am33xx_ddr_data ddr3_data = {
+ .rd_slave_ratio0 = 0x38,
+ .wr_dqs_slave_ratio0 = 0x44,
+ .fifo_we_slave_ratio0 = 0x94,
+ .wr_slave_ratio0 = 0x7D,
+ .use_rank0_delay = 0x01,
+ .dll_lock_diff0 = 0x0,
+};
+
+static const struct am33xx_cmd_control ddr3_cmd_ctrl = {
+ .slave_ratio0 = 0x80,
+ .dll_lock_diff0 = 0x1,
+ .invert_clkout0 = 0x0,
+ .slave_ratio1 = 0x80,
+ .dll_lock_diff1 = 0x1,
+ .invert_clkout1 = 0x0,
+ .slave_ratio2 = 0x80,
+ .dll_lock_diff2 = 0x1,
+ .invert_clkout2 = 0x0,
+};
+
+static const struct am33xx_emif_regs ddr3_regs = {
+ .emif_read_latency = 0x100007,
+ .emif_tim1 = 0x0AAAD4DB,
+ .emif_tim2 = 0x266B7FDA,
+ .emif_tim3 = 0x501F867F,
+ .zq_config = 0x50074BE4,
+ .sdram_config = 0x61C05332,
+ .sdram_config2 = 0x0,
+ .sdram_ref_ctrl = 0xC30,
+};
/**
* @brief The basic entry point for board initialization.
@@ -229,8 +113,6 @@ void beaglebone_sram_init(void)
*/
static int beaglebone_board_init(void)
{
- int in_sdram = running_in_sdram();
-
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
@@ -239,23 +121,42 @@ static int beaglebone_board_init(void)
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
- /* Dont reconfigure SDRAM while running in SDRAM! */
- if (!in_sdram)
- beaglebone_sram_init();
+ if (running_in_sdram())
+ return 0;
+
+ /* Setup the PLLs and the clocks for the peripherals */
+ if (is_beaglebone_black()) {
+ pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
+ am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs,
+ &ddr3_data);
+ } else {
+ pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
+ am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs,
+ &ddr2_data);
+ }
- /* Enable pin mux */
+ am33xx_uart0_soft_reset();
am33xx_enable_uart0_pin_mux();
+ omap_uart_lowlevel_init();
+ putc_ll('>');
return 0;
}
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ unsigned sdram;
+
+ am33xx_save_bootinfo(data);
arm_cpu_lowlevel_init();
beaglebone_board_init();
- barebox_arm_entry(0x80000000, SZ_256M, 0);
+ if (is_beaglebone_black())
+ sdram = SZ_512M;
+ else
+ sdram = SZ_256M;
+
+ barebox_arm_entry(0x80000000, sdram, 0);
}
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
index 61b7f99a17..fcb9571506 100644
--- a/arch/arm/boards/omap343xdsp/lowlevel.c
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -10,6 +10,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
/**
@@ -549,7 +550,7 @@ static int sdp343x_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
index ea928357b4..98f1476bb5 100644
--- a/arch/arm/boards/omap3evm/lowlevel.c
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -9,6 +9,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
@@ -162,7 +163,7 @@ static int omap3_evm_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index a21d55928c..205aaaf817 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -80,7 +81,7 @@ static void noinline panda_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 07cc1d7931..4f39600436 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -110,7 +111,7 @@ static void noinline pcm049_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/pcm051/board.c b/arch/arm/boards/pcm051/board.c
index 2a65b3c535..e7a7b79fad 100644
--- a/arch/arm/boards/pcm051/board.c
+++ b/arch/arm/boards/pcm051/board.c
@@ -39,6 +39,7 @@
#include <spi/flash.h>
#include <i2c/i2c.h>
#include <i2c/at24.h>
+#include <mach/bbu.h>
#include "mux.h"
@@ -69,11 +70,6 @@ static int pcm051_mem_init(void)
}
mem_initcall(pcm051_mem_init);
-static struct flash_platform_data pcm051_spi_flash = {
- .name = "m25p",
- .type = "w25q64",
-};
-
/*
* SPI Flash works at 80Mhz however the SPI controller runs with 48MHz.
* So setup Max speed to be less than the controller speed.
@@ -81,7 +77,6 @@ static struct flash_platform_data pcm051_spi_flash = {
static struct spi_board_info pcm051_spi_board_info[] = {
{
.name = "m25p80",
- .platform_data = &pcm051_spi_flash,
.max_speed_hz = 24000000,
.bus_num = 0,
.chip_select = 0,
@@ -165,7 +160,7 @@ static void pcm051_i2c_init(void)
static void pcm051_nand_init(void)
{
- am33xx_enable_nand_pin_mux();
+ pcm051_enable_nand_pin_mux();
gpmc_generic_init(0x12);
@@ -212,6 +207,8 @@ static int pcm051_devices_init(void)
armlinux_set_bootparams((void *)(AM33XX_DRAM_ADDR_SPACE_START + 0x100));
armlinux_set_architecture(MACH_TYPE_PCM051);
+ am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
+
return 0;
}
device_initcall(pcm051_devices_init);
diff --git a/arch/arm/boards/pcm051/env/boot/sd b/arch/arm/boards/pcm051/env/boot/mmc
index 93a2357448..93a2357448 100644
--- a/arch/arm/boards/pcm051/env/boot/sd
+++ b/arch/arm/boards/pcm051/env/boot/mmc
diff --git a/arch/arm/boards/pcm051/env/boot/nand-ubi b/arch/arm/boards/pcm051/env/boot/nand
index efea518e10..22d657ed9d 100644
--- a/arch/arm/boards/pcm051/env/boot/nand-ubi
+++ b/arch/arm/boards/pcm051/env/boot/nand
@@ -7,4 +7,4 @@ fi
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
-bootargs-root-ubi -r root -m nand0.root,2048
+global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs"
diff --git a/arch/arm/boards/pcm051/env/boot/spi b/arch/arm/boards/pcm051/env/boot/spi
new file mode 100644
index 0000000000..2d10184236
--- /dev/null
+++ b/arch/arm/boards/pcm051/env/boot/spi
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "SPI NOR Flash"
+ exit
+fi
+
+global.bootm.image="/dev/m25p0.kernel"
+
+# Use rootfs form NAND for now as rootfs partition < 4MB
+global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs"
diff --git a/arch/arm/boards/pcm051/env/boot/spi-nor b/arch/arm/boards/pcm051/env/boot/spi-nor
deleted file mode 100644
index 9273b8439b..0000000000
--- a/arch/arm/boards/pcm051/env/boot/spi-nor
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- boot-menu-add-entry "$0" "SPI NOR Flash"
- exit
-fi
-
-global.bootm.image="/dev/m25p0.kernel"
-
-# Use rootfs form SD-Card for now as rootfs partition < 4MB
-global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
-
diff --git a/arch/arm/boards/pcm051/env/config b/arch/arm/boards/pcm051/env/config
deleted file mode 100644
index a9fe44018d..0000000000
--- a/arch/arm/boards/pcm051/env/config
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-# change network settings in /env/network/eth0
-# change mtd partition settings and automountpoints in /env/init/*
-
-# set to false if you do not want to have colors
-global.allow_color=true
-
-# user (used for network filenames)
-global.user=none
-
-# timeout in seconds before the default boot entry is started
-global.autoboot_timeout=3
-
-# default boot entry (one of /env/boot/*)
-global.boot.default=sd
-
-# base bootargs
-global.linux.bootargs.base="console=ttyO0,115200n8"
-
diff --git a/arch/arm/boards/pcm051/env/config-board b/arch/arm/boards/pcm051/env/config-board
new file mode 100644
index 0000000000..7f0b2b797d
--- /dev/null
+++ b/arch/arm/boards/pcm051/env/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=pcm051
+global.linux.bootargs.base="console=ttyO0,115200"
diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c
index f4a1742a74..48578cd46c 100644
--- a/arch/arm/boards/pcm051/lowlevel.c
+++ b/arch/arm/boards/pcm051/lowlevel.c
@@ -11,173 +11,39 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/am33xx-mux.h>
+#include <mach/am33xx-generic.h>
#include <mach/wdt.h>
-/* UART Defines */
-#define UART_SYSCFG_OFFSET (0x54)
-#define UART_SYSSTS_OFFSET (0x58)
-
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-/* AM335X EMIF Register values */
-#define VTP_CTRL_READY (0x1 << 5)
-#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_START_EN (0x1)
-#define CMD_FORCE 0x00 /* common #def */
-#define CMD_DELAY 0x00
-
-#define EMIF_READ_LATENCY 0x06
-#define EMIF_SDCFG 0x61C04832 /* CL 5, CWL 5 */
-#define EMIF_SDREF 0x0000093B
-
-#define EMIF_TIM1 0x0668A39B
-#define EMIF_TIM2 0x26337FDA
-#define EMIF_TIM3 0x501F830F
-
-#define DLL_LOCK_DIFF 0x0
-#define PHY_WR_DATA 0xC1
-#define RD_DQS 0x3B
-#define WR_DQS 0x85
-#define PHY_FIFO_WE 0x100
-#define INVERT_CLKOUT 0x1
-#define PHY_RANK0_DELAY 0x01
-#define DDR_IOCTRL_VALUE 0x18B
-#define CTRL_SLAVE_RATIO 0x40
-#define PHY_LVL_MODE 0x1
-#define DDR_ZQ_CFG 0x50074BE4
-
-static void Cmd_Macro_Config(void)
-{
- writel(CTRL_SLAVE_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
- writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
- writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
- writel(DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
- writel(INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
-
- writel(CTRL_SLAVE_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
- writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
- writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
- writel(DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
- writel(INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
-
- writel(CTRL_SLAVE_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
- writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
- writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
- writel(DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
- writel(INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
-}
-
-static void config_vtp(void)
-{
- writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
- AM33XX_VTP0_CTRL_REG);
- writel(readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
- AM33XX_VTP0_CTRL_REG);
- writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
- AM33XX_VTP0_CTRL_REG);
-
- /* Poll for READY */
- while ((readl(AM33XX_VTP0_CTRL_REG) &
- VTP_CTRL_READY) != VTP_CTRL_READY);
-}
-
-static void phy_config_data(void)
-{
- writel(RD_DQS, AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0);
- writel(WR_DQS, AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0);
- writel(PHY_FIFO_WE, AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0);
- writel(PHY_WR_DATA, AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0);
-
- writel(RD_DQS, AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0);
- writel(WR_DQS, AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0);
- writel(PHY_FIFO_WE, AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0);
- writel(PHY_WR_DATA, AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0);
-}
-
-static void config_emif(void)
-{
- /*Program EMIF0 CFG Registers*/
- writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
- writel(EMIF_READ_LATENCY,
- AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
- writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
- writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
- writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
- writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
- writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
- writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
- writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
- writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
- writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
- writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
- writel(DDR_ZQ_CFG, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
-
- while ((readl(AM33XX_EMIF4_0_REG(SDRAM_STATUS)) & 0x4) != 0x4);
-}
-
-static void pcm051_config_ddr(void)
-{
- enable_ddr_clocks();
-
- config_vtp();
-
- /* init mode */
- writel(PHY_LVL_MODE, AM33XX_DATA0_WRLVL_INIT_MODE_0);
- writel(PHY_LVL_MODE, AM33XX_DATA0_GATELVL_INIT_MODE_0);
- writel(PHY_LVL_MODE, AM33XX_DATA1_WRLVL_INIT_MODE_0);
- writel(PHY_LVL_MODE, AM33XX_DATA1_GATELVL_INIT_MODE_0);
-
- Cmd_Macro_Config();
- phy_config_data();
-
- writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
- writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
-
- writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
- writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
- writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
- writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
- writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
-
- writel(readl(AM33XX_DDR_IO_CTRL) &
- 0xefffffff, AM33XX_DDR_IO_CTRL);
- writel(readl(AM33XX_DDR_CKE_CTRL) |
- 0x00000001, AM33XX_DDR_CKE_CTRL);
-
- config_emif();
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void pcm051_sram_init(void)
-{
- u32 regVal, uart_base;
-
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init(MPUPLL_M_600);
-
- pcm051_config_ddr();
-
- /* UART softreset */
- am33xx_enable_uart0_pin_mux();
- uart_base = AM33XX_UART0_BASE;
-
- regVal = readl(uart_base + UART_SYSCFG_OFFSET);
- regVal |= UART_RESET;
- writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
- while ((readl(uart_base + UART_SYSSTS_OFFSET) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
-
- /* Disable smart idle */
- regVal = readl((uart_base + UART_SYSCFG_OFFSET));
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
-}
+static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
+ .slave_ratio0 = 0x40,
+ .dll_lock_diff0 = 0x0,
+ .invert_clkout0 = 0x1,
+ .slave_ratio1 = 0x40,
+ .dll_lock_diff1 = 0x0,
+ .invert_clkout1 = 0x1,
+ .slave_ratio2 = 0x40,
+ .dll_lock_diff2 = 0x0,
+ .invert_clkout2 = 0x1,
+};
+
+static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = {
+ .emif_read_latency = 0x6,
+ .emif_tim1 = 0x0668A39B,
+ .emif_tim2 = 0x26337FDA,
+ .emif_tim3 = 0x501F830F,
+ .sdram_config = 0x61C04832,
+ .zq_config = 0x50074BE4,
+ .sdram_ref_ctrl = 0x0000093B,
+};
+
+static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = {
+ .rd_slave_ratio0 = 0x3B,
+ .wr_dqs_slave_ratio0 = 0x85,
+ .fifo_we_slave_ratio0 = 0x100,
+ .wr_slave_ratio0 = 0xC1,
+ .use_rank0_delay = 0x01,
+ .dll_lock_diff0 = 0x0,
+};
/**
* @brief The basic entry point for board initialization.
@@ -190,8 +56,6 @@ void pcm051_sram_init(void)
*/
static int pcm051_board_init(void)
{
- int in_sdram = running_in_sdram();
-
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
@@ -201,16 +65,24 @@ static int pcm051_board_init(void)
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
- /* Dont reconfigure SDRAM while running in SDRAM! */
- if (!in_sdram)
- pcm051_sram_init();
+ if (running_in_sdram())
+ return 0;
+
+ pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
+
+ am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
+ &MT41J256M8HX15E_2x256M8_regs,
+ &MT41J256M8HX15E_2x256M8_data);
+
+ am33xx_uart0_soft_reset();
+ am33xx_enable_uart0_pin_mux();
return 0;
}
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ am33xx_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/pcm051/mux.c b/arch/arm/boards/pcm051/mux.c
index b54f3d5a69..e1127ac6f2 100644
--- a/arch/arm/boards/pcm051/mux.c
+++ b/arch/arm/boards/pcm051/mux.c
@@ -14,6 +14,24 @@ static const struct module_pin_mux mmc0_pin_mux[] = {
{-1},
};
+static const struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
static const struct module_pin_mux user_led_pin_mux[] = {
{OFFSET(gpmc_csn1), MODE(7) | PULLUDEN}, /* USER LED1 */
{OFFSET(gpmc_csn2), MODE(7) | PULLUDEN}, /* USER LED2 */
@@ -31,6 +49,11 @@ void pcm051_enable_mmc0_pin_mux(void)
configure_module_pin_mux(mmc0_pin_mux);
}
+void pcm051_enable_nand_pin_mux(void)
+{
+ configure_module_pin_mux(nand_pin_mux);
+}
+
void pcm051_enable_user_led_pin_mux(void)
{
configure_module_pin_mux(user_led_pin_mux);
diff --git a/arch/arm/boards/pcm051/mux.h b/arch/arm/boards/pcm051/mux.h
index 4008376795..5cdbe0ca52 100644
--- a/arch/arm/boards/pcm051/mux.h
+++ b/arch/arm/boards/pcm051/mux.h
@@ -1,3 +1,4 @@
extern void pcm051_enable_mmc0_pin_mux(void);
+extern void pcm051_enable_nand_pin_mux(void);
extern void pcm051_enable_user_led_pin_mux(void);
extern void pcm051_enable_user_btn_pin_mux(void);
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
index 78550408b7..353b58fad6 100644
--- a/arch/arm/boards/phycard-a-l1/lowlevel.c
+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c
@@ -10,6 +10,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
/* Slower full frequency range default timings for x32 operation */
@@ -253,7 +254,7 @@ static int pcaal1_board_init(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 9a794b7272..1ddf8a07ed 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -90,7 +91,7 @@ static noinline void pcaaxl2_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c
index 8c8684123a..8a16abba3a 100644
--- a/arch/arm/boards/tqma6x/lowlevel.c
+++ b/arch/arm/boards/tqma6x/lowlevel.c
@@ -54,7 +54,7 @@ ENTRY_FUNCTION(start_imx6q_mba6x)(void)
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
writel(0x2, 0x020e0338);
setup_uart();
- PUTC_LL('a');
+ putc_ll('a');
}
arm_early_mmu_cache_invalidate();
@@ -77,7 +77,7 @@ ENTRY_FUNCTION(start_imx6dl_mba6x)(void)
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
writel(0x2, 0x020e035c);
setup_uart();
- PUTC_LL('a');
+ putc_ll('a');
}
arm_early_mmu_cache_invalidate();
diff --git a/arch/arm/configs/am335x_beaglebone_defconfig b/arch/arm/configs/am335x_beaglebone_defconfig
index 4e37e0163b..4bcee241fe 100644
--- a/arch/arm/configs/am335x_beaglebone_defconfig
+++ b/arch/arm/configs/am335x_beaglebone_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
-CONFIG_AEABI=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x81000000
+CONFIG_TEXT_BASE=0x8f000000
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_PROMPT="barebox> "
CONFIG_LONGHELP=y
@@ -25,14 +28,13 @@ CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_DIRNAME=y
CONFIG_CMD_LN=y
-CONFIG_CMD_READLINK=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
@@ -45,13 +47,17 @@ CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_DETECT=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
@@ -61,8 +67,9 @@ CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
CONFIG_DRIVER_NET_CPSW=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_OMAP=y
CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
diff --git a/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig b/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
index 886dad9a60..ea29c24594 100644
--- a/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
+++ b/arch/arm/configs/am335x_beaglebone_mlo_small_defconfig
@@ -9,11 +9,9 @@ CONFIG_THUMB2_BAREBOX=y
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x402F0400
-CONFIG_MEMORY_LAYOUT_FIXED=y
-CONFIG_STACK_BASE=0x4030B800
CONFIG_STACK_SIZE=0x1600
-CONFIG_MALLOC_BASE=0x8F000000
CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="MLO>"
CONFIG_SHELL_NONE=y
# CONFIG_ERRNO_MESSAGES is not set
@@ -23,7 +21,7 @@ CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
CONFIG_MCI_OMAP_HSMMC=y
# CONFIG_FS_RAMFS is not set
# CONFIG_FS_DEVFS is not set
diff --git a/arch/arm/configs/pcm051_defconfig b/arch/arm/configs/pcm051_defconfig
index 0bc7c90b8b..97e0940697 100644
--- a/arch/arm/configs/pcm051_defconfig
+++ b/arch/arm/configs/pcm051_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
+CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y
CONFIG_MACH_PCM051=y
CONFIG_OMAP_UART1=y
CONFIG_AEABI=y
diff --git a/arch/arm/configs/pcm051_mlo_defconfig b/arch/arm/configs/pcm051_mlo_defconfig
index f97a7c701a..ea65979ba3 100644
--- a/arch/arm/configs/pcm051_mlo_defconfig
+++ b/arch/arm/configs/pcm051_mlo_defconfig
@@ -5,7 +5,6 @@ CONFIG_MACH_PCM051=y
CONFIG_OMAP_UART1=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_CMD_ARM_CPUINFO is not set
-# CONFIG_BANNER is not set
# CONFIG_MEMINFO is not set
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_MMU=y
@@ -16,6 +15,7 @@ CONFIG_PROMPT="MLO>"
CONFIG_SHELL_NONE=y
# CONFIG_ERRNO_MESSAGES is not set
# CONFIG_TIMESTAMP is not set
+CONFIG_CONSOLE_SIMPLE=y
# CONFIG_DEFAULT_ENVIRONMENT is not set
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index 8aea4b472d..260d47b02a 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -31,6 +31,12 @@
#define CPU_ARCH_ARMv6 8
#define CPU_ARCH_ARMv7 9
+#define ARM_CPU_PART_CORTEX_A5 0xC050
+#define ARM_CPU_PART_CORTEX_A7 0xC070
+#define ARM_CPU_PART_CORTEX_A8 0xC080
+#define ARM_CPU_PART_CORTEX_A9 0xC090
+#define ARM_CPU_PART_CORTEX_A15 0xC0F0
+
static void decode_cache(unsigned long size)
{
int linelen = 1 << ((size & 0x3) + 3);
@@ -154,6 +160,33 @@ static int do_cpuinfo(int argc, char *argv[])
printf("implementer: %s\narchitecture: %s\n",
implementer, architecture);
+ if (cpu_arch == CPU_ARCH_ARMv7) {
+ unsigned int major, minor;
+ char *part;
+ major = (mainid >> 20) & 0xf;
+ minor = mainid & 0xf;
+ switch (mainid & 0xfff0) {
+ case ARM_CPU_PART_CORTEX_A5:
+ part = "Cortex-A5";
+ break;
+ case ARM_CPU_PART_CORTEX_A7:
+ part = "Cortex-A7";
+ break;
+ case ARM_CPU_PART_CORTEX_A8:
+ part = "Cortex-A8";
+ break;
+ case ARM_CPU_PART_CORTEX_A9:
+ part = "Cortex-A9";
+ break;
+ case ARM_CPU_PART_CORTEX_A15:
+ part = "Cortex-A15";
+ break;
+ default:
+ part = "unknown";
+ }
+ printf("core: %s r%up%u\n", part, major, minor);
+ }
+
if (cache & (1 << 24)) {
/* separate I/D cache */
printf("I-cache: ");
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 0bb28ee6ea..f34eaa139f 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -13,6 +13,8 @@
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
+#ifdef CONFIG_DEBUG_LL
+
#ifdef CONFIG_DEBUG_IMX1_UART
#define IMX_DEBUG_SOC MX1
#elif defined CONFIG_DEBUG_IMX21_UART
@@ -61,5 +63,5 @@ static inline void PUTC_LL(int c)
writel(c, base + URTX0);
}
-
+#endif /* CONFIG_DEBUG_LL */
#endif /* __MACH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 16d11805e2..b2eec30b9a 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -90,6 +90,14 @@ config OMAP_BUILD_SPI
Say Y here if you want to build an barebox.spi image as used
on the AM35xx chips when booting from SPI NOR flash.
+config BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO
+ prompt "barebox update SPI NOR MLO handler"
+ bool
+ depends on BAREBOX_UPDATE
+ help
+ Say Y for barebox update SPI NOR MLO handler.
+ AM35xx, AM33xx chips use big endian MLO for SPI NOR flash.
+
config ARCH_TEXT_BASE
hex
default 0x80e80000 if MACH_OMAP343xSDP
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 2163c3fd31..cf2d5ee7dd 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_MFD_TWL6030) += omap4_twl6030_mmc.o
obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
obj-$(CONFIG_CMD_BOOT_ORDER) += boot_order.o
obj-y += gpio.o
+obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO) += am33xx_bbu_spi_mlo.o
diff --git a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c
new file mode 100644
index 0000000000..ff9f8a69ac
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c
@@ -0,0 +1,88 @@
+/*
+ * am33xx_bbu_spi_mlo.c - am35xx and am33xx specific MLO
+ * update handler for SPI NOR flash
+ *
+ * Copyright (c) 2013 Sharavn kumar <shravan.k@phytec.in>, Phytec
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <bbu.h>
+#include <fs.h>
+#include <fcntl.h>
+
+/*
+ * AM35xx, AM33xx chips use big endian MLO for SPI NOR flash
+ * This handler converting MLO to big endian and write to SPI NOR
+ */
+static int spi_nor_mlo_handler(struct bbu_handler *handler,
+ struct bbu_data *data)
+{
+ int dstfd = 0;
+ int ret = 0;
+ uint32_t readbuf;
+ int size = data->len;
+ void *image = data->image;
+
+ dstfd = open(data->devicefile, O_WRONLY);
+ if (dstfd < 0) {
+ printf("could not open %s: %s", data->devicefile, errno_str());
+ ret = dstfd;
+ goto out;
+ }
+
+ ret = erase(dstfd, ~0, 0);
+ if (ret < 0) {
+ printf("could not erase %s: %s", data->devicefile, errno_str());
+ goto out1;
+ }
+
+ for (; size >= 0; size -= 4) {
+ memcpy((char *)&readbuf, image, 4);
+
+ readbuf = cpu_to_be32(readbuf);
+ ret = write(dstfd, &readbuf, 4);
+ if (ret < 0) {
+ perror("write");
+ goto out1;
+ }
+
+ image = image + 4;
+ }
+
+ ret = 0;
+out1:
+ close(dstfd);
+out:
+ return ret;
+}
+
+/*
+ * Register a am33xx MLO update handler for SPI NOR
+ */
+int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile)
+{
+ struct bbu_handler *handler;
+ int ret;
+
+ handler = xzalloc(sizeof(*handler));
+ handler->devicefile = devicefile;
+ handler->name = name;
+ handler->handler = spi_nor_mlo_handler;
+
+ ret = bbu_register_handler(handler);
+
+ if (ret)
+ free(handler);
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
index 9928e9fbb4..692b0ec97b 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -156,7 +156,7 @@ static void per_clocks_enable(void)
while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
}
-static void mpu_pll_config(int mpupll_M)
+static void mpu_pll_config(int mpupll_M, int osc)
{
u32 clkmode, clksel, div_m2;
@@ -170,7 +170,7 @@ static void mpu_pll_config(int mpupll_M)
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x00000100);
clksel = clksel & (~0x7ffff);
- clksel = clksel | ((mpupll_M << 0x8) | MPUPLL_N);
+ clksel = clksel | ((mpupll_M << 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
div_m2 = div_m2 & ~0x1f;
@@ -183,7 +183,7 @@ static void mpu_pll_config(int mpupll_M)
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
}
-static void core_pll_config(void)
+static void core_pll_config(int osc)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -199,7 +199,7 @@ static void core_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x00000100);
clksel = clksel & (~0x7ffff);
- clksel = clksel | ((COREPLL_M << 0x8) | COREPLL_N);
+ clksel = clksel | ((COREPLL_M << 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
div_m4 = div_m4 & ~0x1f;
@@ -221,7 +221,7 @@ static void core_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
}
-static void per_pll_config(void)
+static void per_pll_config(int osc)
{
u32 clkmode, clksel, div_m2;
@@ -235,7 +235,7 @@ static void per_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x00000100);
clksel = clksel & (~0x7ffff);
- clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
+ clksel = clksel | ((PERPLL_M << 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_PER);
div_m2 = div_m2 & ~0x7f;
@@ -248,7 +248,7 @@ static void per_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
}
-static void ddr_pll_config(void)
+static void ddr_pll_config(int osc, int ddrpll_M)
{
u32 clkmode, clksel, div_m2;
@@ -263,7 +263,7 @@ static void ddr_pll_config(void)
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
clksel = clksel & (~0x7ffff);
- clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
+ clksel = clksel | ((ddrpll_M << 0x8) | (osc - 1));
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 & 0xFFFFFFE0;
@@ -288,18 +288,18 @@ void enable_ddr_clocks(void)
PRCM_L3_GCLK_ACTIVITY));
/* Poll if module is functional */
while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
-
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
-void pll_init(int mpupll_M)
+void pll_init(int mpupll_M, int osc, int ddrpll_M)
{
- mpu_pll_config(mpupll_M);
- core_pll_config();
- per_pll_config();
- ddr_pll_config();
+ mpu_pll_config(mpupll_M, osc);
+ core_pll_config(osc);
+ per_pll_config(osc);
+ ddr_pll_config(osc, ddrpll_M);
+
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index a653ef79fd..3690ce1438 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
- * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de>
+ * (C) Copyright 2012-2013 Jan Luebbe <j.luebbe@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -38,6 +38,38 @@ void __noreturn reset_cpu(unsigned long addr)
}
/**
+ * @brief Extract the AM33xx ES revision
+ *
+ * The significance of the CPU revision depends upon the cpu type.
+ * Latest known revision is considered default.
+ *
+ * @return silicon version
+ */
+u32 am33xx_get_cpu_rev(void)
+{
+ u32 version, retval;
+
+ version = (readl(AM33XX_IDCODE_REG) >> 28) & 0xF;
+
+ switch (version) {
+ case 0:
+ retval = AM335X_ES1_0;
+ break;
+ case 1:
+ retval = AM335X_ES2_0;
+ break;
+ case 2:
+ /*
+ * Fall through the default case.
+ */
+ default:
+ retval = AM335X_ES2_1;
+ }
+
+ return retval;
+}
+
+/**
* @brief Get the upper address of current execution
*
* we can use this to figure out if we are running in SRAM /
@@ -100,6 +132,7 @@ u32 running_in_sdram(void)
static int am33xx_bootsource(void)
{
enum bootsource src;
+ int instance = 0;
switch (omap_bootinfo[2] & 0xFF) {
case 0x05:
@@ -107,6 +140,11 @@ static int am33xx_bootsource(void)
break;
case 0x08:
src = BOOTSOURCE_MMC;
+ instance = 0;
+ break;
+ case 0x09:
+ src = BOOTSOURCE_MMC;
+ instance = 1;
break;
case 0x0b:
src = BOOTSOURCE_SPI;
@@ -115,7 +153,7 @@ static int am33xx_bootsource(void)
src = BOOTSOURCE_UNKNOWN;
}
bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_instance(instance);
return 0;
}
postcore_initcall(am33xx_bootsource);
@@ -171,3 +209,160 @@ static int am33xx_gpio_init(void)
return 0;
}
coredevice_initcall(am33xx_gpio_init);
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET 0x54
+#define UART_SYSSTS_OFFSET 0x58
+
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_RESET (0x1 << 1)
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+void am33xx_uart0_soft_reset(void)
+{
+ int reg;
+
+ reg = readl(AM33XX_UART0_BASE + UART_SYSCFG_OFFSET);
+ reg |= UART_RESET;
+ writel(reg, (AM33XX_UART0_BASE + UART_SYSCFG_OFFSET));
+
+ while ((readl(AM33XX_UART0_BASE + UART_SYSSTS_OFFSET) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ reg = readl((AM33XX_UART0_BASE + UART_SYSCFG_OFFSET));
+ reg |= UART_SMART_IDLE_EN;
+ writel(reg, (AM33XX_UART0_BASE + UART_SYSCFG_OFFSET));
+}
+
+
+#define VTP_CTRL_READY (0x1 << 5)
+#define VTP_CTRL_ENABLE (0x1 << 6)
+#define VTP_CTRL_START_EN (0x1)
+
+void am33xx_config_vtp(void)
+{
+ uint32_t val;
+
+ val = readl(AM33XX_VTP0_CTRL_REG);
+ val |= VTP_CTRL_ENABLE;
+ writel(val, AM33XX_VTP0_CTRL_REG);
+
+ val = readl(AM33XX_VTP0_CTRL_REG);
+ val &= ~VTP_CTRL_START_EN;
+ writel(val, AM33XX_VTP0_CTRL_REG);
+
+ val = readl(AM33XX_VTP0_CTRL_REG);
+ val |= VTP_CTRL_START_EN;
+ writel(val, AM33XX_VTP0_CTRL_REG);
+
+ /* Poll for READY */
+ while ((readl(AM33XX_VTP0_CTRL_REG) &
+ VTP_CTRL_READY) != VTP_CTRL_READY)
+ ;
+}
+
+void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl)
+{
+ writel(cmd_ctrl->slave_ratio0, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
+ writel(cmd_ctrl->dll_lock_diff0, AM33XX_CMD0_DLL_LOCK_DIFF_0);
+ writel(cmd_ctrl->invert_clkout0, AM33XX_CMD0_INVERT_CLKOUT_0);
+
+ writel(cmd_ctrl->slave_ratio1, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
+ writel(cmd_ctrl->dll_lock_diff1, AM33XX_CMD1_DLL_LOCK_DIFF_0);
+ writel(cmd_ctrl->invert_clkout1, AM33XX_CMD1_INVERT_CLKOUT_0);
+
+ writel(cmd_ctrl->slave_ratio2, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
+ writel(cmd_ctrl->dll_lock_diff2, AM33XX_CMD2_DLL_LOCK_DIFF_0);
+ writel(cmd_ctrl->invert_clkout2, AM33XX_CMD2_INVERT_CLKOUT_0);
+}
+
+#define CM_EMIF_SDRAM_CONFIG (AM33XX_CTRL_BASE + 0x110)
+
+void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
+{
+ writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
+ writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
+ writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
+ writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
+ writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
+ writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
+ writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
+ writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
+ writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+
+ if (regs->zq_config) {
+ /*
+ * A value of 0x2800 for the REF CTRL will give us
+ * about 570us for a delay, which will be long enough
+ * to configure things.
+ */
+ writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
+ writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
+ writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+ writel(regs->sdram_ref_ctrl,
+ AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ writel(regs->sdram_ref_ctrl,
+ AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+ }
+
+ writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+ writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
+}
+
+void am33xx_config_io_ctrl(int ioctrl)
+{
+ writel(ioctrl, AM33XX_DDR_CMD0_IOCTRL);
+ writel(ioctrl, AM33XX_DDR_CMD1_IOCTRL);
+ writel(ioctrl, AM33XX_DDR_CMD2_IOCTRL);
+ writel(ioctrl, AM33XX_DDR_DATA0_IOCTRL);
+ writel(ioctrl, AM33XX_DDR_DATA1_IOCTRL);
+}
+
+void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr)
+{
+ u32 base = 0x0;
+
+ if (macronr)
+ base = 0xA4;
+
+ writel(data->rd_slave_ratio0, AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + base);
+ writel(data->wr_dqs_slave_ratio0, AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + base);
+ writel(data->wrlvl_init_ratio0, AM33XX_DATA0_WRLVL_INIT_RATIO_0 + base);
+ writel(data->gatelvl_init_ratio0, AM33XX_DATA0_GATELVL_INIT_RATIO_0 + base);
+ writel(data->fifo_we_slave_ratio0, AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + base);
+ writel(data->wr_slave_ratio0, AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + base);
+ writel(data->use_rank0_delay, AM33XX_DATA0_RANK0_DELAYS_0 + base);
+ writel(data->dll_lock_diff0, AM33XX_DATA0_DLL_LOCK_DIFF_0 + base);
+}
+
+void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
+ const struct am33xx_emif_regs *emif_regs,
+ const struct am33xx_ddr_data *ddr_data)
+{
+ uint32_t val;
+
+ enable_ddr_clocks();
+
+ am33xx_config_vtp();
+
+ am33xx_ddr_phydata_cmd_macro(cmd_ctrl);
+ am33xx_config_ddr_data(ddr_data, 0);
+ am33xx_config_ddr_data(ddr_data, 1);
+
+ am33xx_config_io_ctrl(ioctrl);
+
+ val = readl(AM33XX_DDR_IO_CTRL);
+ val &= 0xefffffff;
+ writel(val, AM33XX_DDR_IO_CTRL);
+
+ val = readl(AM33XX_DDR_CKE_CTRL);
+ val |= 0x00000001;
+ writel(val, AM33XX_DDR_CKE_CTRL);
+
+ am33xx_config_sdram(emif_regs);
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 968509ec5e..ecd90b2229 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -23,20 +23,16 @@
/* Put the pll config values over here */
-#define OSC 24
-
/* MAIN PLL Fdll = 1 GHZ, */
#define MPUPLL_M_500 500 /* 125 * n */
#define MPUPLL_M_550 550 /* 125 * n */
#define MPUPLL_M_600 600 /* 125 * n */
#define MPUPLL_M_720 720 /* 125 * n */
-#define MPUPLL_N (OSC - 1)
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000 /* 125 * n */
-#define COREPLL_N (OSC - 1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
@@ -48,12 +44,13 @@
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
-#define PERPLL_N (OSC - 1)
#define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M 266
+#define DDRPLL_M_266 266
+#define DDRPLL_M_303 303
+#define DDRPLL_M_400 400
#define DDRPLL_N (OSC - 1)
#define DDRPLL_M2 1
@@ -187,7 +184,7 @@
#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
-extern void pll_init(int mpupll_M);
+extern void pll_init(int mpupll_M, int osc, int ddrpll_M);
extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h
index 6a4d901028..669198023c 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-devices.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h
@@ -31,6 +31,12 @@ static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data *
AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
+static inline struct device_d *am33xx_add_mmc1(struct omap_hsmmc_platform_data *pdata)
+{
+ return add_generic_device("omap4-hsmmc", 1, NULL,
+ AM33XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
+}
+
static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_data)
{
return add_generic_device("cpsw", 0, NULL,
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index ba69caf313..ec22ad201a 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -1,6 +1,25 @@
#ifndef __MACH_AM33XX_GENERIC_H
#define __MACH_AM33XX_GENERIC_H
+#include <mach/generic.h>
+#include <mach/am33xx-silicon.h>
+
int am33xx_register_ethaddr(int eth_id, int mac_id);
+u32 am33xx_get_cpu_rev(void);
+
+static inline void am33xx_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < AM33XX_SRAM0_START)
+ return;
+ if (i > AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
#endif /* __MACH_AM33XX_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index bd55da4403..30b605a695 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -17,6 +17,8 @@
#ifndef __ASM_ARCH_AM33XX_H
#define __ASM_ARCH_AM33XX_H
+#include <sizes.h>
+
/** AM335x Internal Bus Base addresses */
#define AM33XX_L4_WKUP_BASE 0x44C00000
#define AM33XX_L4_PER_BASE 0x48000000
@@ -69,6 +71,7 @@
/* CTRL */
#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
+#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600)
/* Watchdog Timer */
#define AM33XX_WDT_BASE 0x44E35000
@@ -115,11 +118,10 @@
#define AM33XX_VTP1_CTRL_REG 0x48140E10
/* OCMC */
-#define AM33XX_SRAM0_SIZE (0x1B400) /* 109 KB */
+#define AM33XX_SRAM0_START 0x402f0400
+#define AM33XX_SRAM0_SIZE (SZ_128K - SZ_1K)
#define AM33XX_SRAM_GPMC_STACK_SIZE (0x40)
-#define AM33XX_LOW_LEVEL_SRAM_STACK (AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE - 4)
-
/* DDR offsets */
#define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000
#define AM33XX_DDR_IO_CTRL 0x44E10E04
@@ -191,4 +193,48 @@
#define AM33XX_MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c)
#define AM33XX_MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650)
+struct am33xx_cmd_control {
+ u32 slave_ratio0;
+ u32 dll_lock_diff0;
+ u32 invert_clkout0;
+ u32 slave_ratio1;
+ u32 dll_lock_diff1;
+ u32 invert_clkout1;
+ u32 slave_ratio2;
+ u32 dll_lock_diff2;
+ u32 invert_clkout2;
+};
+
+struct am33xx_emif_regs {
+ u32 emif_read_latency;
+ u32 emif_tim1;
+ u32 emif_tim2;
+ u32 emif_tim3;
+ u32 sdram_config;
+ u32 sdram_config2;
+ u32 zq_config;
+ u32 sdram_ref_ctrl;
+};
+
+struct am33xx_ddr_data {
+ u32 rd_slave_ratio0;
+ u32 wr_dqs_slave_ratio0;
+ u32 wrlvl_init_ratio0;
+ u32 gatelvl_init_ratio0;
+ u32 fifo_we_slave_ratio0;
+ u32 wr_slave_ratio0;
+ u32 use_rank0_delay;
+ u32 dll_lock_diff0;
+};
+
+void am33xx_uart0_soft_reset(void);
+void am33xx_config_vtp(void);
+void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl);
+void am33xx_config_io_ctrl(int ioctrl);
+void am33xx_config_sdram(const struct am33xx_emif_regs *regs);
+void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr);
+void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
+ const struct am33xx_emif_regs *emif_regs,
+ const struct am33xx_ddr_data *ddr_data);
+
#endif
diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h
new file mode 100644
index 0000000000..6d4b70f803
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/bbu.h
@@ -0,0 +1,15 @@
+#ifndef __MACH_BBU_H
+#define __MACH_BBU_H
+
+#include <bbu.h>
+
+#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO
+int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile);
+#else
+int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile)
+{
+ return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h b/arch/arm/mach-omap/include/mach/debug_ll.h
index 38ca56203c..2917558732 100644
--- a/arch/arm/mach-omap/include/mach/debug_ll.h
+++ b/arch/arm/mach-omap/include/mach/debug_ll.h
@@ -17,7 +17,7 @@
#ifndef __MACH_DEBUG_LL_H__
#define __MACH_DEBUG_LL_H__
-#include <asm/io.h>
+#include <io.h>
#ifdef CONFIG_ARCH_OMAP3
#include <mach/omap3-silicon.h>
@@ -56,7 +56,7 @@
#define MCR (4 << 2)
#define MDR (8 << 2)
-static inline void INIT_LL(void)
+static inline void omap_uart_lowlevel_init(void)
{
writeb(0x00, UART_BASE + LCR);
writeb(0x00, UART_BASE + IER);
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
index 3314fafcc1..ece8c2baea 100644
--- a/arch/arm/mach-omap/include/mach/generic.h
+++ b/arch/arm/mach-omap/include/mach/generic.h
@@ -42,14 +42,22 @@ struct omap_barebox_part {
#ifdef CONFIG_SHELL_NONE
int omap_set_barebox_part(struct omap_barebox_part *part);
+int omap_set_mmc_dev(const char *mmcdev);
#else
static inline int omap_set_barebox_part(struct omap_barebox_part *part)
{
return 0;
}
+static inline int omap_set_mmc_dev(const char *mmcdev)
+{
+ return 0;
+}
#endif
extern uint32_t omap_bootinfo[3];
-void omap_save_bootinfo(void);
+void omap_save_bootinfo(void *data);
+
+void omap_set_bootmmc_devname(const char *devname);
+const char *omap_get_bootmmc_devname(void);
#endif
diff --git a/arch/arm/mach-omap/include/mach/omap3-generic.h b/arch/arm/mach-omap/include/mach/omap3-generic.h
new file mode 100644
index 0000000000..7f0da4e331
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap3-generic.h
@@ -0,0 +1,21 @@
+#ifndef __MACH_OMAP3_GENERIC_H
+#define __MACH_OMAP3_GENERIC_H
+
+#include <mach/generic.h>
+#include <mach/omap3-silicon.h>
+
+static inline void omap3_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < OMAP3_SRAM_BASE)
+ return;
+ if (i > OMAP3_SRAM_BASE + SZ_64K)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
+#endif /* __MACH_OMAP3_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h
new file mode 100644
index 0000000000..44f5a12788
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-generic.h
@@ -0,0 +1,21 @@
+#ifndef __MACH_OMAP4_GENERIC_H
+#define __MACH_OMAP4_GENERIC_H
+
+#include <mach/generic.h>
+#include <mach/omap4-silicon.h>
+
+static inline void omap4_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < OMAP44XX_SRAM_BASE)
+ return;
+ if (i > OMAP44XX_SRAM_BASE + SZ_64K)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
+#endif /* __MACH_OMAP4_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap_hsmmc.h b/arch/arm/mach-omap/include/mach/omap_hsmmc.h
index 2055cccbd5..19942df587 100644
--- a/arch/arm/mach-omap/include/mach/omap_hsmmc.h
+++ b/arch/arm/mach-omap/include/mach/omap_hsmmc.h
@@ -21,5 +21,6 @@
/** omapmmc platform data structure */
struct omap_hsmmc_platform_data {
unsigned f_max; /* host interface upper limit */
+ char *devname; /* The mci device name, optional */
};
#endif /* __ASM_OMAP_HSMMC_H */
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index 4d9b138fd8..fce5895554 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -40,6 +40,7 @@
#define CPU_1710 0x1710
#define CPU_2420 0x2420
#define CPU_2430 0x2430
+#define CPU_3350 0x3350
#define CPU_3430 0x3430
#define CPU_3630 0x3630
@@ -54,6 +55,10 @@
#define OMAP34XX_ES3 cpu_revision(CPU_3430, 3)
#define OMAP34XX_ES3_1 cpu_revision(CPU_3430, 4)
+#define AM335X_ES1_0 cpu_revision(CPU_3350, 0)
+#define AM335X_ES2_0 cpu_revision(CPU_3350, 1)
+#define AM335X_ES2_1 cpu_revision(CPU_3350, 2)
+
#define OMAP36XX_ES1 cpu_revision(CPU_3630, 0)
#define OMAP36XX_ES1_1 cpu_revision(CPU_3630, 1)
#define OMAP36XX_ES1_2 cpu_revision(CPU_3630, 2)
@@ -76,8 +81,9 @@
/**
* Hawkeye definitions to identify silicon families
*/
-#define OMAP_HAWKEYE_34XX 0xB7AE
-#define OMAP_HAWKEYE_36XX 0xB891
+#define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */
+#define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */
+#define OMAP_HAWKEYE_335X 0xB944 /* AM335x */
/** These are implemented by the System specific code in omapX-generic.c */
u32 get_cpu_type(void);
diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c
index cfd3dec453..e7ca821212 100644
--- a/arch/arm/mach-omap/omap_generic.c
+++ b/arch/arm/mach-omap/omap_generic.c
@@ -18,19 +18,44 @@
#include <init.h>
#include <io.h>
#include <fs.h>
+#include <malloc.h>
#include <linux/stat.h>
-#if defined(CONFIG_DEFAULT_ENVIRONMENT) && defined(CONFIG_MCI_STARTUP)
+static char *omap_bootmmc_dev;
+
+void omap_set_bootmmc_devname(char *devname)
+{
+ omap_bootmmc_dev = devname;
+}
+
+const char *omap_get_bootmmc_devname(void)
+{
+ return omap_bootmmc_dev;
+}
+
+#if defined(CONFIG_DEFAULT_ENVIRONMENT)
static int omap_env_init(void)
{
struct stat s;
- char *diskdev = "/dev/disk0.0";
+ char *diskdev, *partname;
int ret;
if (bootsource_get() != BOOTSOURCE_MMC)
return 0;
- ret = stat(diskdev, &s);
+ if (omap_bootmmc_dev)
+ diskdev = omap_bootmmc_dev;
+ else
+ diskdev = "disk0";
+
+ device_detect_by_name(diskdev);
+
+ partname = asprintf("/dev/%s.0", diskdev);
+
+ ret = stat(partname, &s);
+
+ free(partname);
+
if (ret) {
printf("no %s. using default env\n", diskdev);
return 0;
diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
index 76746e27bd..b4d1b55e57 100644
--- a/arch/arm/mach-omap/xload.c
+++ b/arch/arm/mach-omap/xload.c
@@ -8,6 +8,7 @@
#include <fs.h>
#include <fcntl.h>
#include <sizes.h>
+#include <malloc.h>
#include <filetype.h>
#include <mach/generic.h>
@@ -98,11 +99,23 @@ static void *omap_xload_boot_mmc(void)
int ret;
void *buf;
int len;
- const char *diskdev = "disk0.0";
+ const char *diskdev;
+ char *partname;
+
+ diskdev = omap_get_bootmmc_devname();
+ if (!diskdev)
+ diskdev = "disk0";
+
+ device_detect_by_name(diskdev);
+
+ partname = asprintf("%s.0", diskdev);
+
+ ret = mount(partname, "fat", "/");
+
+ free(partname);
- ret = mount(diskdev, "fat", "/");
if (ret) {
- printf("Unable to mount %s (%d)\n", diskdev, ret);
+ printf("Unable to mount %s (%d)\n", partname, ret);
return NULL;
}
diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
index 820e1d5d1b..3a244a0c50 100644
--- a/arch/mips/boot/main_entry-pbl.c
+++ b/arch/mips/boot/main_entry-pbl.c
@@ -51,7 +51,7 @@ void __section(.text_entry) pbl_main_entry(void)
u32 pg_start, pg_end, pg_len;
void (*barebox)(void);
- PUTS_LL("pbl_main_entry()\n");
+ puts_ll("pbl_main_entry()\n");
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);
diff --git a/common/console.c b/common/console.c
index 1518ed885f..6ca94e2a02 100644
--- a/common/console.c
+++ b/common/console.c
@@ -93,9 +93,9 @@ static int console_std_set(struct device_d *dev, struct param_d *param,
if (initialized < CONSOLE_INIT_FULL) {
char ch;
initialized = CONSOLE_INIT_FULL;
- PUTS_LL("Switch to console [");
- PUTS_LL(dev_name(dev));
- PUTS_LL("]\n");
+ puts_ll("Switch to console [");
+ puts_ll(dev_name(dev));
+ puts_ll("]\n");
barebox_banner();
while (kfifo_getc(console_output_fifo, &ch) == 0)
console_putc(CONSOLE_STDOUT, ch);
@@ -286,7 +286,7 @@ void console_putc(unsigned int ch, char c)
case CONSOLE_INITIALIZED_BUFFER:
kfifo_putc(console_output_fifo, c);
- PUTC_LL(c);
+ putc_ll(c);
return;
case CONSOLE_INIT_FULL:
diff --git a/common/console_simple.c b/common/console_simple.c
index 1fe569ef9d..101064b69a 100644
--- a/common/console_simple.c
+++ b/common/console_simple.c
@@ -28,7 +28,7 @@ EXPORT_SYMBOL(console_puts);
void console_putc(unsigned int ch, char c)
{
if (!console) {
- PUTC_LL(c);
+ putc_ll(c);
return;
}
diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c
index 62c79e1159..a2cd3fec59 100644
--- a/drivers/mci/omap_hsmmc.c
+++ b/drivers/mci/omap_hsmmc.c
@@ -574,6 +574,13 @@ static void mmc_set_ios(struct mci_host *mci, struct mci_ios *ios)
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}
+static int omap_mmc_detect(struct device_d *dev)
+{
+ struct omap_hsmmc *hsmmc = dev->priv;
+
+ return mci_detect_card(&hsmmc->mci);
+}
+
static int omap_mmc_probe(struct device_d *dev)
{
struct omap_hsmmc *hsmmc;
@@ -593,7 +600,7 @@ static int omap_mmc_probe(struct device_d *dev)
hsmmc->mci.set_ios = mmc_set_ios;
hsmmc->mci.init = mmc_init_setup;
hsmmc->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_MMC_HIGHSPEED;
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_8_BIT_DATA;
hsmmc->mci.hw_dev = dev;
hsmmc->iobase = dev_request_mem_region(dev, 0);
@@ -604,10 +611,19 @@ static int omap_mmc_probe(struct device_d *dev)
hsmmc->mci.f_min = 400000;
pdata = (struct omap_hsmmc_platform_data *)dev->platform_data;
- if (pdata && pdata->f_max)
- hsmmc->mci.f_max = pdata->f_max;
- else
- hsmmc->mci.f_max = 52000000;
+ if (pdata) {
+ if (pdata->f_max)
+ hsmmc->mci.f_max = pdata->f_max;
+ else
+ hsmmc->mci.f_max = 52000000;
+
+ if (pdata->devname)
+ hsmmc->mci.devname = pdata->devname;
+ }
+
+
+ dev->priv = hsmmc;
+ dev->detect = omap_mmc_detect,
mci_register(&hsmmc->mci);
diff --git a/include/debug_ll.h b/include/debug_ll.h
index f0034ba06a..288aa256e5 100644
--- a/include/debug_ll.h
+++ b/include/debug_ll.h
@@ -20,8 +20,7 @@
#ifndef __INCLUDE_DEBUG_LL_H__
#define __INCLUDE_DEBUG_LL_H__
-#if defined (CONFIG_DEBUG_LL)
-
+#ifdef CONFIG_HAS_DEBUG_LL
/*
* mach/debug_ll.h should implement PUTC_LL. This can be a macro or a static
* inline function. Note that several SoCs expect the UART to be initialized
@@ -29,35 +28,61 @@
* this initialization. Depending on the PUTC_LL implementation the board might
* also hang in PUTC_LL without proper initialization.
*/
-# include <mach/debug_ll.h>
+#include <mach/debug_ll.h>
+#endif
-# define PUTHEX_LL(value) ({ unsigned long v = (unsigned long) (value); \
- int i; unsigned char ch; \
- for (i = 8; i--; ) {\
- ch = ((v >> (i*4)) & 0xf);\
- ch += (ch >= 10) ? 'a' - 10 : '0';\
- PUTC_LL (ch); }})
+#if defined (CONFIG_DEBUG_LL)
+
+static inline void putc_ll(unsigned char value)
+{
+ PUTC_LL(value);
+}
+
+static inline void puthex_ll(unsigned long value)
+{
+ int i; unsigned char ch;
+
+ for (i = 8; i--; ) {
+ ch = ((value >> (i * 4)) & 0xf);
+ ch += (ch >= 10) ? 'a' - 10 : '0';
+ putc_ll(ch);
+ }
+}
/*
- * Be careful with PUTS_LL, it only works if the binary is running at the
+ * Be careful with puts_ll, it only works if the binary is running at the
* link address which often is not the case during early startup. If in doubt
* don't use it.
*/
-static __inline__ void PUTS_LL(const char * str)
+static inline void puts_ll(const char * str)
{
while (*str) {
- if (*str == '\n') {
- PUTC_LL('\r');
- }
- PUTC_LL(*str);
+ if (*str == '\n')
+ putc_ll('\r');
+
+ putc_ll(*str);
str++;
}
}
#else
-# define PUTC_LL(c) do {} while (0)
-# define PUTHEX_LL(v) do {} while (0)
-# define PUTS_LL(c) do {} while (0)
+
+static inline void putc_ll(unsigned char value)
+{
+}
+
+static inline void puthex_ll(unsigned long value)
+{
+}
+
+/*
+ * Be careful with puts_ll, it only works if the binary is running at the
+ * link address which often is not the case during early startup. If in doubt
+ * don't use it.
+ */
+static inline void puts_ll(const char * str)
+{
+}
#endif