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authorAndrey Smirnov <andrew.smirnov@gmail.com>2018-06-12 11:47:55 -0700
committerSascha Hauer <s.hauer@pengutronix.de>2018-06-13 09:56:21 +0200
commit96aac9a3a6a64450b82a2295c1ec147b92215487 (patch)
tree44321cd454db15a10953da73555c5561562c1b79
parent239bf555a1b4eab2ebdd9e90aa93f2021759a7de (diff)
downloadbarebox-96aac9a3a6a64450b82a2295c1ec147b92215487.tar.gz
barebox-96aac9a3a6a64450b82a2295c1ec147b92215487.tar.xz
VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCD
Although upstream U-Boot does not initialize this register in vf610-twr code (it does so in code for Phytec's PCM052) multiple revisions of VFxxx Controller Reference Manual state: 5.2.6.1 DUMMY PADS (DDR/QuadSPI) There are two dummy pads that are useful for timing calibration of DDR. These pads are internal only, but there corresponding IOMUX register need to be programmed for correct operation of DDR. These registers are: * IOMUXC_DUMMY_DDRBYTE1 (0x400482DC) * IOMUXC_DUMMY_DDRBYTE2 (0x400482E0) DDR: Dummy pads for DDR must be configured before any DDR I/O transactions are done. These pads simulate the input delay of the I/O buffers from the DRAM devices and DDR configures the delays accordingly. Although current DCD works as is, add writes for those registers for the sake of completness. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg3
-rw-r--r--arch/arm/mach-imx/include/mach/vf610-iomux-regs.h5
2 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
index e2ad818c64..64f97aacd9 100644
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
+++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
@@ -58,3 +58,6 @@ wm 32 VF610_PAD_DDR_WE__DDR_WE_B VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1 VF610_DDR_PAD_CTRL
wm 32 VF610_PAD_DDR_RESETB VF610_DDR_PAD_CTRL
+
+wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL \ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
index 38b3bc7da8..c85f0b74b9 100644
--- a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
+++ b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
@@ -52,4 +52,7 @@
#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x400482cc
#define VF610_PAD_DDR_WE__DDR_WE_B 0x400482d0
#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x400482d4
-#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x400482d8 \ No newline at end of file
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x400482d8
+
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x400482dc
+#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 0x400482e0