diff options
| author | Sascha Hauer <sha@octopus.labnet.pengutronix.de> | 2007-09-11 10:15:32 +0200 |
|---|---|---|
| committer | Sascha Hauer <sha@octopus.labnet.pengutronix.de> | 2007-09-11 10:15:32 +0200 |
| commit | 97c0278dc1cdef940d837be932a284c2bd7f4d35 (patch) | |
| tree | bd0de4b1543c47e6368cd3feaa4b20b2b4c20ed8 | |
| parent | 6402a7d5b747008c5b13d8e62d97493b9f852700 (diff) | |
| download | barebox-97c0278dc1cdef940d837be932a284c2bd7f4d35.tar.gz barebox-97c0278dc1cdef940d837be932a284c2bd7f4d35.tar.xz | |
initial blackfin support
38 files changed, 5830 insertions, 593 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig new file mode 100644 index 0000000000..8268d0c6ed --- /dev/null +++ b/arch/blackfin/Kconfig @@ -0,0 +1,29 @@ + +config BLACKFIN + bool + default y + +config BF561 + bool + +config BOARDINFO + default "PII IPE337" if MACH_IPE337 + +choice + prompt "Select your board" + +config MACH_IPE337 + bool "PII ipe337" + select BF561 + help + Say Y here if you are using the PII IPE337 board + +endchoice + +source common/Kconfig +source commands/Kconfig +source net/Kconfig +source drivers/Kconfig +source fs/Kconfig +source lib/Kconfig + diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile new file mode 100644 index 0000000000..ec9af9d94c --- /dev/null +++ b/arch/blackfin/Makefile @@ -0,0 +1,56 @@ + +CPPFLAGS += -fno-builtin -ffreestanding -nostdinc -Wall \ + -isystem $(gccincdir) -pipe \ + -fno-strict-aliasing + + +board-$(CONFIG_MACH_IPE337) := ipe337 +cpu-$(CONFIG_BF561) := bf561 + +TEXT_BASE = $(CONFIG_TEXT_BASE) + +CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -P +CFLAGS := -fno-common -Os +LDFLAGS_uboot :=-L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -Ttext $(TEXT_BASE) + +ifeq ($(incdir-y),) +incdir-y := $(machine-y) +endif +INCDIR := arch-$(incdir-y) + +# Update machine arch and proc symlinks if something which affects +# them changed. We use .arch to indicate when they were updated +# last, otherwise make uses the target directory mtime. + +include/asm-blackfin/.arch: $(wildcard include/config/arch/*.h) include/config/auto.conf + @echo ' SYMLINK include/asm-blackfin/arch -> include/asm-blackfin/$(INCDIR)' +ifneq ($(KBUILD_SRC),) + $(Q)mkdir -p include/asm-blackfin + $(Q)ln -fsn $(srctree)/include/asm-blackfin/$(INCDIR) include/asm-blackfin/arch +else + $(Q)ln -fsn $(INCDIR) include/asm-blackfin/arch +endif + @touch $@ + +archprepare: maketools + +PHONY += maketools +maketools: include/asm-blackfin/.arch + + +ifneq ($(board-y),) +BOARD := board/$(board-y)/ +else +BOARD := +endif + +ifneq ($(cpu-y),) +CPU := arch/blackfin/cpu-$(cpu-y)/ +else +CPU := +endif + +common-y += $(BOARD) +common-y += arch/blackfin/lib/ $(CPU) + +MRPROPER_FILES += include/asm-arm/arch include/asm-arm/proc diff --git a/arch/blackfin/cpu-bf561/Makefile b/arch/blackfin/cpu-bf561/Makefile new file mode 100644 index 0000000000..1348febb45 --- /dev/null +++ b/arch/blackfin/cpu-bf561/Makefile @@ -0,0 +1,2 @@ +obj-y += start.o +obj-y += init_sdram.o diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S new file mode 100644 index 0000000000..f16bb28bad --- /dev/null +++ b/arch/blackfin/cpu-bf561/init_sdram.S @@ -0,0 +1,167 @@ +#define ASSEMBLY + +#include <config.h> +#include <asm/blackfin.h> +#include <asm/mem_init.h> +.global init_sdram; + +init_sdram: + [--SP] = ASTAT; + [--SP] = RETS; + [--SP] = (R7:0); + [--SP] = (P5:0); + +#ifndef BF537_UART_BOOT + +#ifdef CONFIG_BF537 + /* Enable PHY CLK buffer output */ + p0.h = hi(VR_CTL); + p0.l = lo(VR_CTL); + r0.l = w[p0]; + bitset(r0, 14); + w[p0] = r0.l; + ssync; +#endif + /* + * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable + */ + p0.h = hi(PLL_LOCKCNT); + p0.l = lo(PLL_LOCKCNT); + r0 = 0x300(Z); + w[p0] = r0.l; + ssync; + + /* + * Put SDRAM in self-refresh, incase anything is running + */ + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITSET (R0, 24); + [P2] = R0; + SSYNC; + + /* + * Set PLL_CTL with the value that we calculate in R0 + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over, */ + r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ + r0 = r1 | r0; + r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + cli r2; /* Disable interrupts */ + ssync; + w[p0] = r0.l; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ + +check_again: + p0.h = hi(PLL_STAT); + p0.l = lo(PLL_STAT); + R0 = W[P0](Z); + CC = BITTST(R0,5); + if ! CC jump check_again; + + /* Configure SCLK & CCLK Dividers */ + r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); + p0.h = hi(PLL_DIV); + p0.l = lo(PLL_DIV); + w[p0] = r0.l; + ssync; +#endif + + /* + * We now are running at speed, time to set the Async mem bank wait states + * This will speed up execution, since we are normally running from FLASH. + */ + + p2.h = (EBIU_AMBCTL1 >> 16); + p2.l = (EBIU_AMBCTL1 & 0xFFFF); + r0.h = (AMBCTL1VAL >> 16); + r0.l = (AMBCTL1VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMBCTL0 >> 16); + p2.l = (EBIU_AMBCTL0 & 0xFFFF); + r0.h = (AMBCTL0VAL >> 16); + r0.l = (AMBCTL0VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMGCTL >> 16); + p2.l = (EBIU_AMGCTL & 0xffff); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; + + /* + * Now, Initialize the SDRAM, + * start with the SDRAM Refresh Rate Control Register + */ + p0.l = lo(EBIU_SDRRC); + p0.h = hi(EBIU_SDRRC); + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; + + /* + * SDRAM Memory Bank Control Register - bank specific parameters + */ + p0.l = (EBIU_SDBCTL & 0xFFFF); + p0.h = (EBIU_SDBCTL >> 16); + r0 = mem_SDBCTL; + w[p0] = r0.l; + ssync; + + /* + * SDRAM Global Control Register - global programmable parameters + * Disable self-refresh + */ + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITCLR (R0, 24); + + /* + * Check if SDRAM is already powered up, if it is, enable self-refresh + */ + p0.h = hi(EBIU_SDSTAT); + p0.l = lo(EBIU_SDSTAT); + r2.l = w[p0]; + cc = bittst(r2,3); + if !cc jump skip; + NOP; + BITSET (R0, 23); +skip: + [P2] = R0; + SSYNC; + + /* Write in the new value in the register */ + R0.L = lo(mem_SDGCTL); + R0.H = hi(mem_SDGCTL); + [P2] = R0; + SSYNC; + nop; + + (P5:0) = [SP++]; + (R7:0) = [SP++]; + RETS = [SP++]; + ASTAT = [SP++]; + RTS; + diff --git a/arch/blackfin/cpu-bf561/start.S b/arch/blackfin/cpu-bf561/start.S new file mode 100644 index 0000000000..99b106d98a --- /dev/null +++ b/arch/blackfin/cpu-bf561/start.S @@ -0,0 +1,356 @@ +/* + * U-boot - start.S Startup file of u-boot for BF533/BF561 + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on head.S + * Copyright (c) 2003 Metrowerks/Motorola + * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, + * Kenneth Albanowski <kjahds@kjahds.com>, + * The Silver Hammer Group, Ltd. + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/blackfin.h> +#include <asm/cpu/defBF561_extn.h> +#include <asm/cpu/defBF561.h> + +.section ".text_entry","ax" + +.macro checker + p0.h = FIO0_DIR >> 16; + p0.l = FIO0_DIR & 0xFFFF; + r0 = (1 << 9); + w[p0] = r0; + p0.h = FIO0_FLAG_S >> 16; + p0.l = FIO0_FLAG_S & 0xFFFF; + r0 = (1 << 9); + w[p0] = r0; +1: + jump 1b +.endm + +_start: +start: +_stext: + + R0 = 0x32; + SYSCFG = R0; + SSYNC; + + /* As per HW reference manual DAG registers, + * DATA and Address resgister shall be zero'd + * in initialization, after a reset state + */ + r1 = 0; /* Data registers zero'd */ + r2 = 0; + r3 = 0; + r4 = 0; + r5 = 0; + r6 = 0; + r7 = 0; + + p0 = 0; /* Address registers zero'd */ + p1 = 0; + p2 = 0; + p3 = 0; + p4 = 0; + p5 = 0; + + i0 = 0; /* DAG Registers zero'd */ + i1 = 0; + i2 = 0; + i3 = 0; + m0 = 0; + m1 = 0; + m3 = 0; + m3 = 0; + l0 = 0; + l1 = 0; + l2 = 0; + l3 = 0; + b0 = 0; + b1 = 0; + b2 = 0; + b3 = 0; + + /* Set loop counters to zero, to make sure that + * hw loops are disabled. + */ + r0 = 0; + lc0 = r0; + lc1 = r0; + + SSYNC; + + /* Check soft reset status */ + p0.h = SWRST >> 16; + p0.l = SWRST & 0xFFFF; + r0.l = w[p0]; + + cc = bittst(r0, 15); + if !cc jump no_soft_reset; + + /* Clear Soft reset */ + r0 = 0x0000; + w[p0] = r0; + ssync; + +no_soft_reset: + nop; + + /* Clear EVT registers */ + p0.h = hi(EVT_EMULATION_ADDR) + p0.l = lo(EVT_EMULATION_ADDR); + p0 += 8; + p1 = 14; + r1 = 0; + LSETUP(4,4) lc0 = p1; + [ p0 ++ ] = r1; + + p0.h = hi(SIC_IWR); + p0.l = lo(SIC_IWR); + r0.l = 0x1; + w[p0] = r0.l; + SSYNC; + + sp.l = lo(0xffb01000); + sp.h = hi(0xffb01000); + + /* Check if the code is in SDRAM */ + /* If the code is in SDRAM, skip SDRAM initializaiton */ + call get_pc; + r3.l = 0x0; + r3.h = 0x2000; + cc = r0 < r3 (iu); + if cc jump sdram_initialized; + call init_sdram; + /* relocate into to RAM */ +sdram_initialized: + call get_pc; +offset: + r2.l = offset; + r2.h = offset; + r3.l = start; + r3.h = start; + r1 = r2 - r3; + + r0 = r0 - r1; + p1 = r0; + + p2.l = lo(TEXT_BASE); + p2.h = hi(TEXT_BASE); + + p3 = 0x04; + p4.l = __bss_start; + p4.h = __bss_start; +loop1: + r1 = [p1 ++ p3]; + [p2 ++ p3] = r1; + cc=p2==p4; + if !cc jump loop1; + + /* + * configure STACK + */ + r0.h = hi(CONFIG_STACKBASE); + r0.l = lo(CONFIG_STACKBASE); + sp = r0; + fp = sp; + + /* + * This next section keeps the processor in supervisor mode + * during kernel boot. Switches to user mode at end of boot. + * See page 3-9 of Hardware Reference manual for documentation. + */ + + /* To keep ourselves in the supervisor mode */ + p0.l = lo(EVT_IVG15_ADDR); + p0.h = hi(EVT_IVG15_ADDR); + + p1.l = _real_start; + p1.h = _real_start; + [p0] = p1; + + p0.l = lo(IMASK); + p0.h = hi(IMASK); + r0.l = lo(IVG15_POS); + r0.h = hi(IVG15_POS); + [p0] = r0; + raise 15; + p0.l = WAIT_HERE; + p0.h = WAIT_HERE; + reti = p0; + rti; + +WAIT_HERE: + jump WAIT_HERE; + +.global _real_start; +_real_start: + [ -- sp ] = reti; + +#if defined(CONFIG_EZKIT533) || defined(CONFIG_EZKIT561) + p0.l = lo(WDOG_CTL); + p0.h = hi(WDOG_CTL); + r0 = WATCHDOG_DISABLE(z); + w[p0] = r0; +#endif + + +#ifdef CONFIG_BF537 +/* Initialise General-Purpose I/O Modules on BF537 + * Rev 0.0 Anomaly 05000212 - PORTx_FER, + * PORT_MUX Registers Do Not accept "writes" correctly + */ + p0.h = hi(PORTF_FER); + p0.l = lo(PORTF_FER); + R0.L = W[P0]; /* Read */ + nop; + nop; + nop; + ssync; + R0 = 0x000F(Z); + W[P0] = R0.L; /* Write */ + nop; + nop; + nop; + ssync; + W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */ + nop; + nop; + nop; + ssync; + + p0.h = hi(PORTH_FER); + p0.l = lo(PORTH_FER); + R0.L = W[P0]; /* Read */ + nop; + nop; + nop; + ssync; + R0 = 0xFFFF(Z); + W[P0] = R0.L; /* Write */ + nop; + nop; + nop; + ssync; + W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */ + nop; + nop; + nop; + ssync; + +#endif + + /* DMA reset code to Hi of L1 SRAM */ +copy: + P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ + P1.L = lo(SYSMMR_BASE); + + R0.H = reset_start; /* Source Address (high) */ + R0.L = reset_start; /* Source Address (low) */ + R1.H = reset_end; + R1.L = reset_end; + R2 = R1 - R0; /* Count */ + R1.H = hi(L1_ISRAM); /* Destination Address (high) */ + R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ + R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ + +DMA: + R6 = 0x1 (Z); + W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + + [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + /* Set Source DMAConfig = DMA Enable, + Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ + W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + + [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + /* Set Destination DMAConfig = DMA Enable, + Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ + W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + +WAIT_DMA_DONE: + p0.h = hi(MDMA_D0_IRQ_STATUS); + p0.l = lo(MDMA_D0_IRQ_STATUS); + R0 = W[P0](Z); + CC = BITTST(R0, 0); + if ! CC jump WAIT_DMA_DONE + + R0 = 0x1; + W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + + /* Initialize BSS Section with 0 s */ + p1.l = __bss_start; + p1.h = __bss_start; + p2.l = _end; + p2.h = _end; + r1 = p1; + r2 = p2; + r3 = r2 - r1; + r3 = r3 >> 2; + p3 = r3; + lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; + CC = p2<=p1; + if CC jump _clear_bss_skip; + r0 = 0; +_clear_bss: +_clear_bss_end: + [p1++] = r0; +_clear_bss_skip: + +#if defined(CONFIG_BF537)&&defined(CONFIG_POST) + p0.l = post_flag; + p0.h = post_flag; + r0 = r7; + [p0] = r0; +#endif + + p0.l = _start_uboot; + p0.h = _start_uboot; + jump (p0); + +reset_start: + p0.h = hi(WDOG_CNT); + p0.l = lo(WDOG_CNT); + r0 = 0x0010; + w[p0] = r0; + p0.h = hi(WDOG_CTL); + p0.l = lo(WDOG_CTL); + r0 = 0x0000; + w[p0] = r0; +reset_wait: + jump reset_wait; + +reset_end: nop; + +_exit: + jump.s _exit; +get_pc: + r0 = rets; + rts; diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile new file mode 100644 index 0000000000..a510263a05 --- /dev/null +++ b/arch/blackfin/lib/Makefile @@ -0,0 +1,12 @@ + +obj-y += board.o +obj-y += clock.o +obj-y += muldi3.o +obj-y += udivsi3.o +obj-y += umulsi3_highpart.o +obj-y += smulsi3_highpart.o +obj-y += umodsi3.o +obj-y += lshrdi3.o +obj-y += ashldi3.o +obj-y += divsi3.o +obj-y += modsi3.o diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c new file mode 100644 index 0000000000..c0c4df8cc9 --- /dev/null +++ b/arch/blackfin/lib/ashldi3.c @@ -0,0 +1,60 @@ +/* + * File: arch/blackfin/lib/ashldi3.c + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: $Id: ashldi3.c 2775 2007-02-21 13:58:44Z hennerich $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "gcclib.h" + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text)); +#endif + +DItype __ashldi3(DItype u, word_type b) +{ + DIunion w; + word_type bm; + DIunion uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof(SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) { + w.s.low = 0; + w.s.high = (USItype) uu.s.low << -bm; + } else { + USItype carries = (USItype) uu.s.low >> bm; + w.s.low = (USItype) uu.s.low << b; + w.s.high = ((USItype) uu.s.high << b) | carries; + } + + return w.ll; +} diff --git a/lib_blackfin/bf533_linux.c b/arch/blackfin/lib/bf533_linux.c index 88b4da29df..dba01b4f70 100644 --- a/lib_blackfin/bf533_linux.c +++ b/arch/blackfin/lib/bf533_linux.c @@ -52,7 +52,6 @@ static char *make_command_line(void); extern image_header_t header; -extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], ulong addr, ulong * len_ptr, int verify) { diff --git a/lib_blackfin/bf533_string.c b/arch/blackfin/lib/bf533_string.c index c8b1a3a983..c8b1a3a983 100644 --- a/lib_blackfin/bf533_string.c +++ b/arch/blackfin/lib/bf533_string.c diff --git a/lib_blackfin/blackfin_board.h b/arch/blackfin/lib/blackfin_board.h index 31c16a20fe..5c6eb88949 100644 --- a/lib_blackfin/blackfin_board.h +++ b/arch/blackfin/lib/blackfin_board.h @@ -42,12 +42,7 @@ ulong monitor_flash_len; #define VERSION_STRING_FORMAT "%s (%s - %s)\n" #define VERSION_STRING U_BOOT_VERSION, __DATE__, __TIME__ -char version_string[VERSION_STRING_SIZE]; - int *g_addr; -static ulong mem_malloc_start; -static ulong mem_malloc_end; -static ulong mem_malloc_brk; extern char _sram_in_sdram_start[]; extern char _sram_inst_size[]; #ifdef DEBUG diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c new file mode 100644 index 0000000000..9a9a83dfbd --- /dev/null +++ b/arch/blackfin/lib/board.c @@ -0,0 +1,50 @@ +/* + * U-boot - board.c First C file to be called contains init routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mem_malloc.h> +#include "blackfin_board.h" + +int blackfin_mem_malloc_init(void) +{ + mem_malloc_init((void *)(CONFIG_MALLOC_BASE - CONFIG_MALLOC_LEN), + (void *)CONFIG_MALLOC_BASE); + return 0; +} + +core_initcall(blackfin_mem_malloc_init); + +void reset_cpu(ulong ignored) +{ + printf("do not ave a reset function\n"); + while (1); +} diff --git a/lib_blackfin/cache.c b/arch/blackfin/lib/cache.c index 847278d226..847278d226 100644 --- a/lib_blackfin/cache.c +++ b/arch/blackfin/lib/cache.c diff --git a/arch/blackfin/lib/clock.c b/arch/blackfin/lib/clock.c new file mode 100644 index 0000000000..71fccfeb4a --- /dev/null +++ b/arch/blackfin/lib/clock.c @@ -0,0 +1,79 @@ + +#include <common.h> +#include <clock.h> +#include <init.h> +#include <asm/blackfin.h> +#include <asm/cpu/cdef_LPBlackfin.h> + +static ulong get_vco(void) +{ + ulong msel; + ulong vco; + + msel = (*pPLL_CTL >> 9) & 0x3F; + if (0 == msel) + msel = 64; + + vco = CONFIG_CLKIN_HZ; + vco >>= (1 & *pPLL_CTL); /* DF bit */ + vco = msel * vco; + return vco; +} + +/* Get the Core clock */ +ulong get_cclk(void) +{ + ulong csel, ssel; + if (*pPLL_STAT & 0x1) + return CONFIG_CLKIN_HZ; + + ssel = *pPLL_DIV; + csel = ((ssel >> 4) & 0x03); + ssel &= 0xf; + if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ + return get_vco() / ssel; + return get_vco() >> csel; +} + +/* Get the System clock */ +ulong get_sclk(void) +{ + ulong ssel; + + if (*pPLL_STAT & 0x1) + return CONFIG_CLKIN_HZ; + + ssel = (*pPLL_DIV & 0xf); + + return get_vco() / ssel; +} + +uint64_t blackfin_clocksource_read(void) +{ + return ~(*pTCOUNT); +} + +static struct clocksource cs = { + .read = blackfin_clocksource_read, + .mask = 0xffffffff, + .shift = 10, +}; + +static int clocksource_init (void) +{ + *pTCNTL = 0x1; + *pTSCALE = 0x0; + *pTCOUNT = ~0; + *pTPERIOD = ~0; + *pTCNTL = 0x7; + asm("CSYNC;"); + + cs.mult = clocksource_hz2mult(get_cclk(), cs.shift); + + init_clock(&cs); + + return 0; +} + +core_initcall(clocksource_init); + diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S new file mode 100644 index 0000000000..8a6a6c913c --- /dev/null +++ b/arch/blackfin/lib/divsi3.S @@ -0,0 +1,217 @@ +/* + * File: arch/blackfin/lib/divsi3.S + * Based on: + * Author: + * + * Created: + * Description: 16 / 32 bit signed division. + * Special cases : + * 1) If(numerator == 0) + * return 0 + * 2) If(denominator ==0) + * return positive max = 0x7fffffff + * 3) If(numerator == denominator) + * return 1 + * 4) If(denominator ==1) + * return numerator + * 5) If(denominator == -1) + * return -numerator + * + * Operand : R0 - Numerator (i) + * R1 - Denominator (i) + * R0 - Quotient (o) + * Registers Used : R2-R7,P0-P2 + * Rev: $Id: divsi3.S 2794 2007-03-05 05:27:47Z cooloney $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +.global ___divsi3; + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + +.align 2; +___divsi3 : + + + R3 = R0 ^ R1; + R0 = ABS R0; + + CC = V; + + r3 = rot r3 by -1; + r1 = abs r1; /* now both positive, r3.30 means "negate result", + ** r3.31 means overflow, add one to result + */ + cc = r0 < r1; + if cc jump .Lret_zero; + r2 = r1 >> 15; + cc = r2; + if cc jump .Lidents; + r2 = r1 << 16; + cc = r2 <= r0; + if cc jump .Lidents; + + DIVS(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + DIVQ(R0, R1); + + R0 = R0.L (Z); + r1 = r3 >> 31; /* add overflow issue back in */ + r0 = r0 + r1; + r1 = -r0; + cc = bittst(r3, 30); + if cc r0 = r1; + RTS; + +/* Can't use the primitives. Test common identities. +** If the identity is true, return the value in R2. +*/ + +.Lidents: + CC = R1 == 0; /* check for divide by zero */ + IF CC JUMP .Lident_return; + + CC = R0 == 0; /* check for division of zero */ + IF CC JUMP .Lzero_return; + + CC = R0 == R1; /* check for identical operands */ + IF CC JUMP .Lident_return; + + CC = R1 == 1; /* check for divide by 1 */ + IF CC JUMP .Lident_return; + + R2.L = ONES R1; + R2 = R2.L (Z); + CC = R2 == 1; + IF CC JUMP .Lpower_of_two; + + /* Identities haven't helped either. + ** Perform the full division process. + */ + + P1 = 31; /* Set loop counter */ + + [--SP] = (R7:5); /* Push registers R5-R7 */ + R2 = -R1; + [--SP] = R2; + R2 = R0 << 1; /* R2 lsw of dividend */ + R6 = R0 ^ R1; /* Get sign */ + R5 = R6 >> 31; /* Shift sign to LSB */ + + R0 = 0 ; /* Clear msw partial remainder */ + R2 = R2 | R5; /* Shift quotient bit */ + R6 = R0 ^ R1; /* Get new quotient bit */ + + LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */ +.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */ + R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ + R0 = R0 << 1 || R5 = [SP]; + R0 = R0 | R7; /* and add carry */ + CC = R6 < 0; /* Check quotient(AQ) */ + /* we might be subtracting divisor (AQ==0) */ + IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/ + R0 = R0 + R5; /* do add or subtract, as indicated by AQ */ + R6 = R0 ^ R1; /* Generate next quotient bit */ + R5 = R6 >> 31; + /* Assume AQ==1, shift in zero */ + BITTGL(R5,0); /* tweak AQ to be what we want to shift in */ +.Llend: R2 = R2 + R5; /* and then set shifted-in value to + ** tweaked AQ. + */ + r1 = r3 >> 31; + r2 = r2 + r1; + cc = bittst(r3,30); + r0 = -r2; + if !cc r0 = r2; + SP += 4; + (R7:5)= [SP++]; /* Pop registers R6-R7 */ + RTS; + +.Lident_return: + CC = R1 == 0; /* check for divide by zero => 0x7fffffff */ + R2 = -1 (X); + R2 >>= 1; + IF CC JUMP .Ltrue_ident_return; + + CC = R0 == R1; /* check for identical operands => 1 */ + R2 = 1 (Z); + IF CC JUMP .Ltrue_ident_return; + + R2 = R0; /* assume divide by 1 => numerator */ + /*FALLTHRU*/ + +.Ltrue_ident_return: + R0 = R2; /* Return an identity value */ + R2 = -R2; + CC = bittst(R3,30); + IF CC R0 = R2; +.Lzero_return: + RTS; /* ...including zero */ + +.Lpower_of_two: + /* Y has a single bit set, which means it's a power of two. + ** That means we can perform the division just by shifting + ** X to the right the appropriate number of bits + */ + + /* signbits returns the number of sign bits, minus one. + ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need + ** to shift right n-signbits spaces. It also means 0x80000000 + ** is a special case, because that *also* gives a signbits of 0 + */ + + R2 = R0 >> 31; + CC = R1 < 0; + IF CC JUMP .Ltrue_ident_return; + + R1.l = SIGNBITS R1; + R1 = R1.L (Z); + R1 += -30; + R0 = LSHIFT R0 by R1.L; + r1 = r3 >> 31; + r0 = r0 + r1; + R2 = -R0; // negate result if necessary + CC = bittst(R3,30); + IF CC R0 = R2; + RTS; + +.Lret_zero: + R0 = 0; + RTS; diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h new file mode 100644 index 0000000000..8bf01f4190 --- /dev/null +++ b/arch/blackfin/lib/gcclib.h @@ -0,0 +1,49 @@ +/* + * File: arch/blackfin/lib/gcclib.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: $Id: gcclib.h 1942 2006-08-03 17:37:22Z vapier $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define BITS_PER_UNIT 8 +#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT) + +typedef unsigned int UQItype __attribute__ ((mode(QI))); +typedef int SItype __attribute__ ((mode(SI))); +typedef unsigned int USItype __attribute__ ((mode(SI))); +typedef int DItype __attribute__ ((mode(DI))); +typedef int word_type __attribute__ ((mode(__word__))); +typedef unsigned int UDItype __attribute__ ((mode(DI))); + +struct DIstruct { + SItype low, high; +}; + +typedef union { + struct DIstruct s; + DItype ll; +} DIunion; diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c new file mode 100644 index 0000000000..75f366575a --- /dev/null +++ b/arch/blackfin/lib/lshrdi3.c @@ -0,0 +1,74 @@ +/* + * File: arch/blackfin/lib/lshrdi3.c + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: $Id: lshrdi3.c 2775 2007-02-21 13:58:44Z hennerich $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define BITS_PER_UNIT 8 + +typedef int SItype __attribute__ ((mode(SI))); +typedef unsigned int USItype __attribute__ ((mode(SI))); +typedef int DItype __attribute__ ((mode(DI))); +typedef int word_type __attribute__ ((mode(__word__))); + +struct DIstruct { + SItype high, low; +}; + +typedef union { + struct DIstruct s; + DItype ll; +} DIunion; + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text)); +#endif + +DItype __lshrdi3(DItype u, word_type b) +{ + DIunion w; + word_type bm; + DIunion uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof(SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) { + w.s.high = 0; + w.s.low = (USItype) uu.s.high >> -bm; + } else { + USItype carries = (USItype) uu.s.high << bm; + w.s.high = (USItype) uu.s.high >> b; + w.s.low = ((USItype) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S new file mode 100644 index 0000000000..4f9f5cb812 --- /dev/null +++ b/arch/blackfin/lib/modsi3.S @@ -0,0 +1,81 @@ +/* + * File: arch/blackfin/lib/modsi3.S + * Based on: + * Author: + * + * Created: + * Description: This program computes 32 bit signed remainder. It calls div32 function + * for quotient estimation. + * + * Registers used : + * Numerator/ Denominator in R0, R1 + * R0 - returns remainder. + * R2-R7 + * + * Rev: $Id: modsi3.S 2775 2007-02-21 13:58:44Z hennerich $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +.global ___modsi3; +.type ___modsi3, STT_FUNC; +.extern ___divsi3; +.type ___divsi3, STT_FUNC; + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + +___modsi3: + + CC=R0==0; + IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */ + CC=R1==0; + IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */ + CC=R0==R1; + IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */ + CC = R1 == 1; + IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */ + CC = R1 == -1; + IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */ + + /* Valid input. Use __divsi3() to compute the quotient, and then + * derive the remainder from that. */ + + [--SP] = (R7:6); /* Push R7 and R6 */ + [--SP] = RETS; /* and return address */ + R7 = R0; /* Copy of R0 */ + R6 = R1; /* Save for later */ + SP += -12; /* Should always provide this space */ + CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/ + SP += 12; + R0 *= R6; /* Quotient * divisor */ + R0 = R7 - R0; /* Dividend - (quotient * divisor) */ + RETS = [SP++]; /* Get back return address */ + (R7:6) = [SP++]; /* Pop registers R7 and R4 */ + RTS; /* Store remainder */ + +.LRETURN_ZERO: + R0 = 0; +.LRETURN_R0: + RTS; diff --git a/lib_blackfin/muldi3.c b/arch/blackfin/lib/muldi3.c index 1fc34e3d93..3924fd9d23 100644 --- a/lib_blackfin/muldi3.c +++ b/arch/blackfin/lib/muldi3.c @@ -22,10 +22,9 @@ * MA 02111-1307 USA */ +#include "gcclib.h" + /* Generic function got from GNU gcc package, libgcc2.c */ -#ifndef SI_TYPE_SIZE -#define SI_TYPE_SIZE 32 -#endif #define __ll_B (1L << (SI_TYPE_SIZE / 2)) #define __ll_lowpart(t) ((USItype) (t) % __ll_B) #define __ll_highpart(t) ((USItype) (t) / __ll_B) @@ -64,18 +63,6 @@ do { \ __w.ll; }) #endif -typedef unsigned int USItype __attribute__ ((mode (SI))); -typedef int SItype __attribute__ ((mode (SI))); -typedef int DItype __attribute__ ((mode (DI))); -typedef int word_type __attribute__ ((mode (__word__))); - -struct DIstruct {SItype low, high;}; -typedef union -{ - struct DIstruct s; - DItype ll; -} DIunion; - DItype __muldi3 (DItype u, DItype v) { DIunion w; diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S new file mode 100644 index 0000000000..10b8f8da57 --- /dev/null +++ b/arch/blackfin/lib/smulsi3_highpart.S @@ -0,0 +1,30 @@ +.align 2 +.global ___smulsi3_highpart; +.type ___smulsi3_highpart, STT_FUNC; + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + +___smulsi3_highpart: + R2 = R1.L * R0.L (FU); + R3 = R1.H * R0.L (IS,M); + R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); + + R1.L = R2.H + R1.L; + cc = ac0; + R2 = cc; + + R1.L = R1.L + R3.L; + cc = ac0; + R1 >>>= 16; + R3 >>>= 16; + R1 = R1 + R3; + R1 = R1 + R2; + R2 = cc; + R1 = R1 + R2; + + R0 = R0 + R1; + RTS; diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S new file mode 100644 index 0000000000..63cbcf35a7 --- /dev/null +++ b/arch/blackfin/lib/udivsi3.S @@ -0,0 +1,299 @@ +/* + * File: arch/blackfin/lib/udivsi3.S + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: $Id: udivsi3.S 2795 2007-03-05 06:25:33Z cooloney $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CARRY AC0 + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + + +.globl ___udivsi3; + +___udivsi3: + CC = R0 < R1 (IU); /* If X < Y, always return 0 */ + IF CC JUMP .Lreturn_ident; + + R2 = R1 << 16; + CC = R2 <= R0 (IU); + IF CC JUMP .Lidents; + + R2 = R0 >> 31; /* if X is a 31-bit number */ + R3 = R1 >> 15; /* and Y is a 15-bit number */ + R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/ + CC = R2; + IF CC JUMP .Ly_16bit; + +/* METHOD 1: FAST DIVQ + We know we have a 31-bit dividend, and 15-bit divisor so we can use the + simple divq approach (first setting AQ to 0 - implying unsigned division, + then 16 DIVQ's). +*/ + + AQ = CC; /* Clear AQ (CC==0) */ + +/* ISR States: When dividing two integers (32.0/16.0) using divide primitives, + we need to shift the dividend one bit to the left. + We have already checked that we have a 31-bit number so we are safe to do + that. +*/ + R0 <<= 1; + DIVQ(R0, R1); // 1 + DIVQ(R0, R1); // 2 + DIVQ(R0, R1); // 3 + DIVQ(R0, R1); // 4 + DIVQ(R0, R1); // 5 + DIVQ(R0, R1); // 6 + DIVQ(R0, R1); // 7 + DIVQ(R0, R1); // 8 + DIVQ(R0, R1); // 9 + DIVQ(R0, R1); // 10 + DIVQ(R0, R1); // 11 + DIVQ(R0, R1); // 12 + DIVQ(R0, R1); // 13 + DIVQ(R0, R1); // 14 + DIVQ(R0, R1); // 15 + DIVQ(R0, R1); // 16 + R0 = R0.L (Z); + RTS; + +.Ly_16bit: + /* We know that the upper 17 bits of Y might have bits set, + ** or that the sign bit of X might have a bit. If Y is a + ** 16-bit number, but not bigger, then we can use the builtins + ** with a post-divide correction. + ** R3 currently holds Y>>15, which means R3's LSB is the + ** bit we're interested in. + */ + + /* According to the ISR, to use the Divide primitives for + ** unsigned integer divide, the useable range is 31 bits + */ + CC = ! BITTST(R0, 31); + + /* IF condition is true we can scale our inputs and use the divide primitives, + ** with some post-adjustment + */ + R3 += -1; /* if so, Y is 0x00008nnn */ + CC &= AZ; + + /* If condition is true we can scale our inputs and use the divide primitives, + ** with some post-adjustment + */ + R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */ + R2 = R0 >> 16; + + R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */ + CC &= CARRY; + IF CC JUMP .Lshift_and_correct; + + /* Fall through to the identities */ + +/* METHOD 2: identities and manual calculation + We are not able to use the divide primites, but may still catch some special + cases. +*/ +.Lidents: + /* Test for common identities. Value to be returned is placed in R2. */ + CC = R0 == 0; /* 0/Y => 0 */ + IF CC JUMP .Lreturn_r0; + CC = R0 == R1; /* X==Y => 1 */ + IF CC JUMP .Lreturn_ident; + CC = R1 == 1; /* X/1 => X */ + IF CC JUMP .Lreturn_ident; + + R2.L = ONES R1; + R2 = R2.L (Z); + CC = R2 == 1; + IF CC JUMP .Lpower_of_two; + + [--SP] = (R7:5); /* Push registers R5-R7 */ + + /* Idents don't match. Go for the full operation. */ + + + R6 = 2; /* assume we'll shift two */ + R3 = 1; + + P2 = R1; + /* If either R0 or R1 have sign set, */ + /* divide them by two, and note it's */ + /* been done. */ + CC = R1 < 0; + R2 = R1 >> 1; + IF CC R1 = R2; /* Possibly-shifted R1 */ + IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */ + + P0 = 0; + R3 = -R1; + [--SP] = R3; + R2 = R0 >> 1; + R2 = R0 >> 1; + CC = R0 < 0; + IF CC P0 = R6; /* Number of values divided */ + IF !CC R2 = R0; /* Shifted R0 */ + + /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */ + + /* r2 holds Copy dividend */ + R3 = 0; /* Clear partial remainder */ + R7 = 0; /* Initialise quotient bit */ + + P1 = 32; /* Set loop counter */ + LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */ +.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */ + R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ + R3 = R3 << 1 || R5 = [SP]; + R3 = R3 | R6; /* Include any carry */ + CC = R7 < 0; /* Check quotient(AQ) */ + /* If AQ==0, we'll sub divisor */ + IF CC R5 = R1; /* and if AQ==1, we'll add it. */ + R3 = R3 + R5; /* Add/sub divsor to partial remainder */ + R7 = R3 ^ R1; /* Generate next quotient bit */ + + R5 = R7 >> 31; /* Get AQ */ + BITTGL(R5, 0); /* Invert it, to get what we'll shift */ +.Lulend: R2 = R2 + R5; /* and "shift" it in. */ + + CC = P0 == 0; /* Check how many inputs we shifted */ + IF CC JUMP .Lno_mult; /* if none... */ + R6 = R2 << 1; + CC = P0 == 1; + IF CC R2 = R6; /* if 1, Q = Q*2 */ + IF !CC R1 = P2; /* if 2, restore stored divisor */ + + R3 = R2; /* Copy of R2 */ + R3 *= R1; /* Q * divisor */ + R5 = R0 - R3; /* Z = (dividend - Q * divisor) */ + CC = R1 <= R5 (IU); /* Check if divisor <= Z? */ + R6 = CC; /* if yes, R6 = 1 */ + R2 = R2 + R6; /* if yes, add one to quotient(Q) */ +.Lno_mult: + SP += 4; + (R7:5) = [SP++]; /* Pop registers R5-R7 */ + R0 = R2; /* Store quotient */ + RTS; + +.Lreturn_ident: + CC = R0 < R1 (IU); /* If X < Y, always return 0 */ + R2 = 0; + IF CC JUMP .Ltrue_return_ident; + R2 = -1 (X); /* X/0 => 0xFFFFFFFF */ + CC = R1 == 0; + IF CC JUMP .Ltrue_return_ident; + R2 = -R2; /* R2 now 1 */ + CC = R0 == R1; /* X==Y => 1 */ + IF CC JUMP .Ltrue_return_ident; + R2 = R0; /* X/1 => X */ + /*FALLTHRU*/ + +.Ltrue_return_ident: + R0 = R2; +.Lreturn_r0: + RTS; + +.Lpower_of_two: + /* Y has a single bit set, which means it's a power of two. + ** That means we can perform the division just by shifting + ** X to the right the appropriate number of bits + */ + + /* signbits returns the number of sign bits, minus one. + ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need + ** to shift right n-signbits spaces. It also means 0x80000000 + ** is a special case, because that *also* gives a signbits of 0 + */ + + R2 = R0 >> 31; + CC = R1 < 0; + IF CC JUMP .Ltrue_return_ident; + + R1.l = SIGNBITS R1; + R1 = R1.L (Z); + R1 += -30; + R0 = LSHIFT R0 by R1.L; + RTS; + +/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION + Two scaling operations are required to use the divide primitives with a + divisor > 0x7FFFF. + Firstly (as in method 1) we need to shift the dividend 1 to the left for + integer division. + Secondly we need to shift both the divisor and dividend 1 to the right so + both are in range for the primitives. + The left/right shift of the dividend does nothing so we can skip it. +*/ +.Lshift_and_correct: + R2 = R0; + // R3 is already R1 >> 1 + CC=!CC; + AQ = CC; /* Clear AQ, got here with CC = 0 */ + DIVQ(R2, R3); // 1 + DIVQ(R2, R3); // 2 + DIVQ(R2, R3); // 3 + DIVQ(R2, R3); // 4 + DIVQ(R2, R3); // 5 + DIVQ(R2, R3); // 6 + DIVQ(R2, R3); // 7 + DIVQ(R2, R3); // 8 + DIVQ(R2, R3); // 9 + DIVQ(R2, R3); // 10 + DIVQ(R2, R3); // 11 + DIVQ(R2, R3); // 12 + DIVQ(R2, R3); // 13 + DIVQ(R2, R3); // 14 + DIVQ(R2, R3); // 15 + DIVQ(R2, R3); // 16 + + /* According to the Instruction Set Reference: + To divide by a divisor > 0x7FFF, + 1. prescale and perform divide to obtain quotient (Q) (done above), + 2. multiply quotient by unscaled divisor (result M) + 3. subtract the product from the divident to get an error (E = X - M) + 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q) + */ + R3 = R2.L (Z); /* Q = X' / Y' */ + R2 = R3; /* Preserve Q */ + R2 *= R1; /* M = Q * Y */ + R2 = R0 - R2; /* E = X - M */ + R0 = R3; /* Copy Q into result reg */ + +/* Correction: If result of the multiply is negative, we overflowed + and need to correct the result by subtracting 1 from the result.*/ + R3 = 0xFFFF (Z); + R2 = R2 >> 16; /* E >> 16 */ + CC = R2 == R3; + R3 = 1 ; + R1 = R0 - R3; + IF CC R0 = R1; + RTS; diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S new file mode 100644 index 0000000000..363ccdf65e --- /dev/null +++ b/arch/blackfin/lib/umodsi3.S @@ -0,0 +1,68 @@ +/* + * File: arch/blackfin/lib/umodsi3.S + * Based on: + * Author: + * + * Created: + * Description: libgcc1 routines for Blackfin 5xx + * + * Rev: $Id: umodsi3.S 2769 2007-02-19 16:45:53Z hennerich $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + +.extern ___udivsi3; +.globl ___umodsi3 +___umodsi3: + + CC=R0==0; + IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */ + CC= R1==0; + IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */ + CC=R0==R1; + IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */ + CC = R1 == 1; + IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */ + CC = R0<R1 (IU); + IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */ + + [--SP] = (R7:6); /* Push registers and */ + [--SP] = RETS; /* Return address */ + R7 = R0; /* Copy of R0 */ + R6 = R1; + SP += -12; /* Should always provide this space */ + CALL ___udivsi3; /* Compute unsigned quotient using ___udiv32()*/ + SP += 12; + R0 *= R6; /* Quotient * divisor */ + R0 = R7 - R0; /* Dividend - (quotient * divisor) */ + RETS = [SP++]; /* Pop return address */ + ( R7:6) = [SP++]; /* And registers */ + RTS; /* Return remainder */ +.LRETURN_ZERO_VAL: + R0 = 0; +.LRETURN_R0: + RTS; diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S new file mode 100644 index 0000000000..aac8218fb2 --- /dev/null +++ b/arch/blackfin/lib/umulsi3_highpart.S @@ -0,0 +1,23 @@ +.align 2 +.global ___umulsi3_highpart; +.type ___umulsi3_highpart, STT_FUNC; + +#ifdef CONFIG_ARITHMETIC_OPS_L1 +.section .l1.text +#else +.text +#endif + +___umulsi3_highpart: + R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU); + R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU); + R0 >>= 16; + /* Unsigned multiplication has the nice property that we can + ignore carry on this first addition. */ + R0 = R0 + R3; + R0 = R0 + R1; + cc = ac0; + R1 = cc; + R1 = PACK(R1.l,R0.h); + R0 = R1 + R2; + RTS; diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index fbdbf30fa1..f6a10eda32 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -25,22 +25,52 @@ #ifndef _BLACKFIN_H_ #define _BLACKFIN_H_ -#include <asm/cpu/defBF533.h> -#include <asm/cpu/bf533_serial.h> +#define lo(con32) ((con32) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) +#ifdef CONFIG_BF561 + +#include <asm/cpu/defBF561.h> #ifndef __ASSEMBLY__ -#ifndef ASSEMBLY +#include <asm/cpu/cdefBF561.h> +#endif + +#endif -#ifdef SHARED_RESOURCES - #include <asm/shared_resources.h> +#ifndef __ASSEMBLY__ +/* Get the System clock */ +ulong get_sclk(void); #endif -#include <asm/cpu/cdefBF53x.h> +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif -#include <asm/cpu/defBF533.h> -#include <asm/cpu/defBF533_extn.h> -#include <asm/cpu/bf533_serial.h> +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif #endif + diff --git a/include/asm-blackfin/common.h b/include/asm-blackfin/common.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/include/asm-blackfin/common.h diff --git a/include/asm-blackfin/cpu/cdefBF561.h b/include/asm-blackfin/cpu/cdefBF561.h new file mode 100644 index 0000000000..60fdf1eb79 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF561.h @@ -0,0 +1,1001 @@ +/************************************************************************ + * + * cdefBF561.h + * + * (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ + +#ifndef _CDEF_BF561_H +#define _CDEF_BF561_H + +/* + * #if !defined(__ADSPBF561__) + * #warning cdefBF561.h should only be included for BF561 chip. + * #endif + */ + +// include all Core registers and bit definitions +#include <asm/cpu/defBF561.h> +//#include <asm/arch-common/cdef_LPBlackfin.h> + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define pPLL_CTL (volatile unsigned short *)PLL_CTL +#define pPLL_DIV (volatile unsigned short *)PLL_DIV +#define pVR_CTL (volatile unsigned short *)VR_CTL +#define pPLL_STAT (volatile unsigned short *)PLL_STAT +#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT + +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST +#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR +#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT +#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK +#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0 +#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1 +#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0 +#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1 +#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2 +#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3 +#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4 +#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5 +#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6 +#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7 +#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0 +#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1 +#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0 +#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1 + +/* + * System Reset and Interrupt Controller registers for + * Core B (0xFFC0 1100-0xFFC0 11FF) + */ +#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST +#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR +#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT +#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0 +#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1 +#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0 +#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1 +#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2 +#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3 +#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4 +#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5 +#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6 +#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7 +#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0 +#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1 +#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0 +#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1 + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL +#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT +#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT + +/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ +#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL +#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT +#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define pUART_THR (volatile unsigned short *)UART_THR +#define pUART_RBR (volatile unsigned short *)UART_RBR +#define pUART_DLL (volatile unsigned short *)UART_DLL +#define pUART_IER (volatile unsigned short *)UART_IER +#define pUART_DLH (volatile unsigned short *)UART_DLH +#define pUART_IIR (volatile unsigned short *)UART_IIR +#define pUART_LCR (volatile unsigned short *)UART_LCR +#define pUART_MCR (volatile unsigned short *)UART_MCR +#define pUART_LSR (volatile unsigned short *)UART_LSR +#define pUART_MSR (volatile unsigned short *)UART_MSR +#define pUART_SCR (volatile unsigned short *)UART_SCR +#define pUART_GCTL (volatile unsigned short *)UART_GCTL + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define pSPI_CTL (volatile unsigned short *)SPI_CTL +#define pSPI_FLG (volatile unsigned short *)SPI_FLG +#define pSPI_STAT (volatile unsigned short *)SPI_STAT +#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR +#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR +#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD +#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW + +/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ +#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG +#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER +#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD +#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH +#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG +#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER +#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD +#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH +#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG +#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER +#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD +#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH +#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG +#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER +#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD +#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH +#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG +#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER +#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD +#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH +#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG +#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER +#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD +#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH +#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG +#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER +#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD +#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH +#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG +#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER +#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD +#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH + +/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ +#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE +#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE +#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS +#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG +#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER +#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD +#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH +#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG +#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER +#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD +#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH +#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG +#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER +#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD +#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH +#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG +#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER +#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD +#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH +#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE +#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE +#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D +#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C +#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S +#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T +#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D +#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C +#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S +#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T +#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D +#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C +#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S +#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T +#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR +#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR +#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE +#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH +#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN + +/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ +#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D +#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C +#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S +#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T +#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D +#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C +#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S +#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T +#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D +#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C +#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S +#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T +#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR +#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR +#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE +#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH +#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN + +/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ +#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D +#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C +#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S +#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T +#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D +#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C +#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S +#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T +#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D +#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C +#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S +#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T +#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR +#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR +#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE +#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH +#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1 +#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2 +#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV +#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV +#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX +#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1 +#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2 +#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV +#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV +#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT +#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL +#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1 +#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2 +#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0 +#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1 +#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2 +#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3 +#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0 +#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1 +#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2 +#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3 + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1 +#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2 +#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV +#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV +#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX +#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1 +#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2 +#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV +#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV +#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT +#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL +#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1 +#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2 +#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0 +#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1 +#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2 +#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3 +#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0 +#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1 +#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2 +#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3 + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL +#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0 +#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1 + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL +#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL +#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC +#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ +#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL +#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS +#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT +#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY +#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME + +/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/ +#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL +#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS +#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT +#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY +#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME + +/*DMA Traffic controls*/ +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER) +#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT) + +/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ +#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG +#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR +#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR +#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT +#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT +#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY +#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY +#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR +#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR +#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT +#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT +#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS +#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP +#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG +#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR +#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR +#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT +#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT +#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY +#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY +#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR +#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR +#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT +#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT +#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS +#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP +#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG +#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR +#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR +#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT +#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT +#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY +#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY +#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR +#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR +#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT +#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT +#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS +#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP +#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG +#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR +#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR +#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT +#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT +#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY +#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY +#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR +#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR +#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT +#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT +#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS +#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP +#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG +#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR +#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR +#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT +#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT +#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY +#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY +#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR +#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR +#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT +#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT +#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS +#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP +#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG +#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR +#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR +#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT +#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT +#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY +#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY +#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR +#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR +#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT +#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT +#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS +#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP +#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG +#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR +#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR +#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT +#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT +#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY +#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY +#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR +#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR +#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT +#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT +#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS +#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP +#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG +#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR +#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR +#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT +#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT +#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY +#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY +#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR +#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR +#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT +#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT +#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS +#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP +#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG +#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR +#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR +#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT +#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT +#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY +#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY +#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR +#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR +#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT +#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT +#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS +#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP +#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG +#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR +#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR +#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT +#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT +#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY +#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY +#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR +#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR +#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT +#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT +#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS +#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP +#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG +#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR +#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR +#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT +#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT +#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY +#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY +#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR +#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR +#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT +#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT +#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS +#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP +#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG +#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR +#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR +#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT +#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT +#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY +#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY +#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR +#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR +#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT +#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT +#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS +#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/ +#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG +#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR +#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR +#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT +#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT +#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY +#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY +#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR +#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR +#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT +#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT +#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS +#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP +#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG +#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR +#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR +#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT +#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT +#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY +#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY +#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR +#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR +#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT +#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT +#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS +#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP +#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG +#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR +#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR +#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT +#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT +#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY +#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY +#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR +#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR +#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT +#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT +#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS +#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP +#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG +#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR +#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR +#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT +#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT +#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY +#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY +#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR +#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR +#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT +#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT +#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS +#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP + +/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ +#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG +#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR +#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR +#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT +#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT +#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY +#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY +#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR +#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR +#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT +#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT +#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS +#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP +#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG +#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR +#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR +#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT +#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT +#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY +#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY +#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR +#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR +#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT +#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT +#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS +#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP +#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG +#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR +#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR +#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT +#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT +#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY +#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY +#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR +#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR +#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT +#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT +#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS +#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP +#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG +#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR +#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR +#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT +#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT +#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY +#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY +#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR +#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR +#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT +#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT +#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS +#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP +#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG +#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR +#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR +#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT +#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT +#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY +#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY +#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR +#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR +#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT +#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT +#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS +#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP +#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG +#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR +#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR +#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT +#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT +#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY +#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY +#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR +#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR +#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT +#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT +#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS +#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP +#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG +#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR +#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR +#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT +#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT +#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY +#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY +#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR +#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR +#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT +#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT +#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS +#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP +#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG +#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR +#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR +#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT +#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT +#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY +#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY +#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR +#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR +#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT +#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT +#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS +#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP +#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG +#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR +#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR +#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT +#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT +#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY +#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY +#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR +#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR +#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT +#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT +#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS +#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP +#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG +#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR +#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR +#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT +#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT +#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY +#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY +#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR +#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR +#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT +#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT +#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS +#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP +#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG +#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR +#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR +#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT +#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT +#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY +#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY +#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR +#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR +#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT +#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT +#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS +#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP +#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG +#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR +#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR +#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT +#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT +#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY +#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY +#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR +#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR +#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT +#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT +#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS +#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP + +/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ +#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG +#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR +#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR +#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT +#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT +#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY +#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY +#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR +#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR +#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT +#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT +#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS +#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP +#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG +#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR +#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR +#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT +#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT +#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY +#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY +#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR +#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR +#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT +#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT +#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS +#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP +#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG +#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR +#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR +#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT +#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT +#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY +#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY +#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR +#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR +#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT +#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT +#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS +#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP +#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG +#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR +#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR +#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT +#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT +#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY +#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY +#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR +#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR +#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT +#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT +#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS +#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP + +/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ +#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG +#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR +#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR +#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT +#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT +#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY +#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY +#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR +#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR +#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT +#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT +#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS +#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG +#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR +#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR +#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT +#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT +#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY +#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY +#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR +#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR +#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT +#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT +#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS +#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG +#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR +#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR +#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT +#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT +#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY +#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY +#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR +#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR +#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT +#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT +#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS +#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG +#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR +#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR +#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT +#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT +#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY +#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY +#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR +#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR +#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT +#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT +#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS + +#if 1 /* comment by mhfan */ +/* + * System Reset and Interrupt Controller registers for + * core A (0xFFC0 0100-0xFFC0 01FF) + */ +#define pSWRST (volatile unsigned short *)SICA_SWRST +#define pSYSCR (volatile unsigned short *)SICA_SYSCR +#define pRVECT (volatile unsigned short *)SICA_RVECT +#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST +#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR +#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT +#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK +#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0) +#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1 +#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2 +#define pSIC_ISR (volatile unsigned long *)SICA_ISR0 +#define pSIC_IWR (volatile unsigned long *)SICA_IWR0 + +/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ +#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL +#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT +#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT +#endif /* comment by mhfan */ + +/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ +#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D +#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C +#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S +#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T +#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D +#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C +#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S +#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T +#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D +#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C +#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S +#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T +#define pFIO_DIR (volatile unsigned short *)FIO0_DIR +#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR +#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE +#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH +#define pFIO_INEN (volatile unsigned short *)FIO0_INEN + +/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ +#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL +#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS +#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT +#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY +#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME + +/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ +#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG +#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR +#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR +#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT +#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT +#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY +#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY +#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR +#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR +#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT +#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT +#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS +#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP + +/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ +#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG +#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR +#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR +#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT +#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT +#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY +#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY +#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR +#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR +#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT +#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT +#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS +#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP +#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG +#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR +#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR +#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT +#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT +#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY +#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY +#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR +#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR +#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT +#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT +#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS +#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP +#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG +#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR +#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR +#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT +#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT +#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY +#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY +#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR +#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR +#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT +#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT +#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS +#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP +#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG +#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR +#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR +#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT +#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT +#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY +#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY +#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR +#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR +#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT +#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT +#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS +#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP + +/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ +#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG +#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR +#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR +#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT +#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT +#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY +#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY +#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR +#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR +#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT +#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT +#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS +#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP +#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG +#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR +#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR +#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT +#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT +#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY +#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY +#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR +#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR +#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT +#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT +#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS +#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP +#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG +#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR +#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR +#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT +#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT +#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY +#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY +#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR +#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR +#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT +#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT +#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS +#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP +#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG +#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR +#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR +#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT +#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT +#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY +#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY +#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR +#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR +#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT +#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT +#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS +#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP +#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG +#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR +#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR +#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT +#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT +#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY +#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY +#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR +#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR +#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT +#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT +#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS +#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP +#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG +#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR +#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR +#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT +#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT +#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY +#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY +#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR +#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR +#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT +#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT +#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS +#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP +#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG +#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR +#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR +#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT +#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT +#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY +#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY +#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR +#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR +#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT +#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT +#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS +#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP + +#endif /* _CDEF_BF561_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h index 26a5fe6442..65853ed434 100644 --- a/include/asm-blackfin/cpu/defBF532.h +++ b/include/asm-blackfin/cpu/defBF532.h @@ -30,17 +30,6 @@ /* include all Core registers and bit definitions */ #include <asm/cpu/def_LPBlackfin.h> -/* Helper macros - * usage: - * P0.H = HI(UART_THR); - * P0.L = LO(UART_THR); - */ - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - /* * System MMR Register Map */ diff --git a/include/asm-blackfin/cpu/defBF561.h b/include/asm-blackfin/cpu/defBF561.h new file mode 100644 index 0000000000..11de2beb62 --- /dev/null +++ b/include/asm-blackfin/cpu/defBF561.h @@ -0,0 +1,3057 @@ +/************************************************************************ + * + * defBF561.h + * + * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ + +#ifndef _DEF_BF561_H +#define _DEF_BF561_H + +/* + * #if !defined(__ADSPBF561__) + * #warning defBF561.h should only be included for BF561 chip. + * #endif + */ + +// include all Core registers and bit definitions +#include <asm/cpu/def_LPBlackfin.h> + +//***************************************************************************** +// System MMR Register Map +//***************************************************************************** + +//// Clock and System Control (0xFFC00000 - 0xFFC000FF) +#define PLL_CTL 0xFFC00000 // PLL Control register (16-bit) +#define PLL_DIV 0xFFC00004 // PLL Divide Register (16-bit) +#define VR_CTL 0xFFC00008 // Voltage Regulator + // Control Register (16-bit) +#define PLL_STAT 0xFFC0000C // PLL Status register (16-bit) +#define PLL_LOCKCNT 0xFFC00010 // PLL Lock Count register + // (16-bit) + +// System Reset and Interrupt Controller registers for +// core A (0xFFC0 0100-0xFFC0 01FF) +#define SICA_SWRST 0xFFC00100 // Software Reset register +#define SICA_SYSCR 0xFFC00104 // System Reset Configuration + // register +#define SICA_RVECT 0xFFC00108 // SIC Reset Vector Address + // Register +#define SICA_IMASK 0xFFC0010C // SIC Interrupt Mask + // register 0 - hack to fix + // old tests +#define SICA_IMASK0 0xFFC0010C // SIC Interrupt Mask + // register 0 +#define SICA_IMASK1 0xFFC00110 // SIC Interrupt Mask + // register 1 +#define SICA_IAR0 0xFFC00124 // SIC Interrupt Assignment + // Register 0 +#define SICA_IAR1 0xFFC00128 // SIC Interrupt Assignment + // Register 1 +#define SICA_IAR2 0xFFC0012C // SIC Interrupt Assignment + // Register 2 +#define SICA_IAR3 0xFFC00130 // SIC Interrupt Assignment + // Register 3 +#define SICA_IAR4 0xFFC00134 // SIC Interrupt Assignment + // Register 4 +#define SICA_IAR5 0xFFC00138 // SIC Interrupt Assignment + // Register 5 +#define SICA_IAR6 0xFFC0013C // SIC Interrupt Assignment + // Register 6 +#define SICA_IAR7 0xFFC00140 // SIC Interrupt Assignment + // Register 7 +#define SICA_ISR0 0xFFC00114 // SIC Interrupt Status + // register 0 +#define SICA_ISR1 0xFFC00118 // SIC Interrupt Status + // register 1 +#define SICA_IWR0 0xFFC0011C // SIC Interrupt + // Wakeup-Enable register 0 +#define SICA_IWR1 0xFFC00120 // SIC Interrupt + // Wakeup-Enable register 1 + +// System Reset and Interrupt Controller registers for +// Core B (0xFFC0 1100-0xFFC0 11FF) +#define SICB_SWRST 0xFFC01100 // reserved +#define SICB_SYSCR 0xFFC01104 // reserved +#define SICB_RVECT 0xFFC01108 // SIC Reset Vector Address + // Register +#define SICB_IMASK0 0xFFC0110C // SIC Interrupt Mask + // register 0 +#define SICB_IMASK1 0xFFC01110 // SIC Interrupt Mask + // register 1 +#define SICB_IAR0 0xFFC01124 // SIC Interrupt Assignment + // Register 0 +#define SICB_IAR1 0xFFC01128 // SIC Interrupt Assignment + // Register 1 +#define SICB_IAR2 0xFFC0112C // SIC Interrupt Assignment + // Register 2 +#define SICB_IAR3 0xFFC01130 // SIC Interrupt Assignment + // Register 3 +#define SICB_IAR4 0xFFC01134 // SIC Interrupt Assignment + // Register 4 +#define SICB_IAR5 0xFFC01138 // SIC Interrupt Assignment + // Register 5 +#define SICB_IAR6 0xFFC0113C // SIC Interrupt Assignment + // Register 6 +#define SICB_IAR7 0xFFC01140 // SIC Interrupt Assignment + // Register 7 +#define SICB_ISR0 0xFFC01114 // SIC Interrupt Status + // register 0 +#define SICB_ISR1 0xFFC01118 // SIC Interrupt Status + // register 1 +#define SICB_IWR0 0xFFC0111C // SIC Interrupt + // Wakeup-Enable register 0 +#define SICB_IWR1 0xFFC01120 // SIC Interrupt + // Wakeup-Enable register 1 + +// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) +#define WDOGA_CTL 0xFFC00200 // Watchdog Control register +#define WDOGA_CNT 0xFFC00204 // Watchdog Count register +#define WDOGA_STAT 0xFFC00208 // Watchdog Status register + +// Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) +#define WDOGB_CTL 0xFFC01200 // Watchdog Control register +#define WDOGB_CNT 0xFFC01204 // Watchdog Count register +#define WDOGB_STAT 0xFFC01208 // Watchdog Status register + +// UART Controller (0xFFC00400 - 0xFFC004FF) +#define UART_THR 0xFFC00400 // Transmit Holding register +#define UART_RBR 0xFFC00400 // Receive Buffer register +#define UART_DLL 0xFFC00400 // Divisor Latch (Low-Byte) +#define UART_IER 0xFFC00404 // Interrupt Enable Register +#define UART_DLH 0xFFC00404 // Divisor Latch (High-Byte) +#define UART_IIR 0xFFC00408 // Interrupt Identification + // Register +#define UART_LCR 0xFFC0040C // Line Control Register +#define UART_MCR 0xFFC00410 // Modem Control Register +#define UART_LSR 0xFFC00414 // Line Status Register +#define UART_MSR 0xFFC00418 // Modem Status Register +#define UART_SCR 0xFFC0041C // SCR Scratch Register +#define UART_GCTL 0xFFC00424 // Global Control Register + +// SPI Controller (0xFFC00500 - 0xFFC005FF) +#define SPI_CTL 0xFFC00500 // SPI Control Register +#define SPI_FLG 0xFFC00504 // SPI Flag register +#define SPI_STAT 0xFFC00508 // SPI Status register +#define SPI_TDBR 0xFFC0050C // SPI Transmit Data + // Buffer Register +#define SPI_RDBR 0xFFC00510 // SPI Receive Data + // Buffer Register +#define SPI_BAUD 0xFFC00514 // SPI Baud rate + // Register +#define SPI_SHADOW 0xFFC00518 // SPI_RDBR Shadow + // Register + +// Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) +#define TIMER0_CONFIG 0xFFC00600 // Timer0 Configuration + // register +#define TIMER0_COUNTER 0xFFC00604 // Timer0 Counter register +#define TIMER0_PERIOD 0xFFC00608 // Timer0 Period register +#define TIMER0_WIDTH 0xFFC0060C // Timer0 Width register +#define TIMER1_CONFIG 0xFFC00610 // Timer1 Configuration + // register +#define TIMER1_COUNTER 0xFFC00614 // Timer1 Counter register +#define TIMER1_PERIOD 0xFFC00618 // Timer1 Period register +#define TIMER1_WIDTH 0xFFC0061C // Timer1 Width register +#define TIMER2_CONFIG 0xFFC00620 // Timer2 Configuration + // register +#define TIMER2_COUNTER 0xFFC00624 // Timer2 Counter register +#define TIMER2_PERIOD 0xFFC00628 // Timer2 Period register +#define TIMER2_WIDTH 0xFFC0062C // Timer2 Width register +#define TIMER3_CONFIG 0xFFC00630 // Timer3 Configuration + // register +#define TIMER3_COUNTER 0xFFC00634 // Timer3 Counter register +#define TIMER3_PERIOD 0xFFC00638 // Timer3 Period register +#define TIMER3_WIDTH 0xFFC0063C // Timer3 Width register +#define TIMER4_CONFIG 0xFFC00640 // Timer4 Configuration + // register +#define TIMER4_COUNTER 0xFFC00644 // Timer4 Counter register +#define TIMER4_PERIOD 0xFFC00648 // Timer4 Period register +#define TIMER4_WIDTH 0xFFC0064C // Timer4 Width register +#define TIMER5_CONFIG 0xFFC00650 // Timer5 Configuration + // register +#define TIMER5_COUNTER 0xFFC00654 // Timer5 Counter register +#define TIMER5_PERIOD 0xFFC00658 // Timer5 Period register +#define TIMER5_WIDTH 0xFFC0065C // Timer5 Width register +#define TIMER6_CONFIG 0xFFC00660 // Timer6 Configuration + // register +#define TIMER6_COUNTER 0xFFC00664 // Timer6 Counter register +#define TIMER6_PERIOD 0xFFC00668 // Timer6 Period register +#define TIMER6_WIDTH 0xFFC0066C // Timer6 Width register +#define TIMER7_CONFIG 0xFFC00670 // Timer7 Configuration + // register +#define TIMER7_COUNTER 0xFFC00674 // Timer7 Counter register +#define TIMER7_PERIOD 0xFFC00678 // Timer7 Period register +#define TIMER7_WIDTH 0xFFC0067C // Timer7 Width register + +#define TMRS8_ENABLE 0xFFC00680 // Timer Enable Register +#define TMRS8_DISABLE 0xFFC00684 // Timer Disable register +#define TMRS8_STATUS 0xFFC00688 // Timer Status register + +// Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) +#define TIMER8_CONFIG 0xFFC01600 // Timer8 Configuration + // register +#define TIMER8_COUNTER 0xFFC01604 // Timer8 Counter register +#define TIMER8_PERIOD 0xFFC01608 // Timer8 Period register +#define TIMER8_WIDTH 0xFFC0160C // Timer8 Width register +#define TIMER9_CONFIG 0xFFC01610 // Timer9 Configuration + // register +#define TIMER9_COUNTER 0xFFC01614 // Timer9 Counter register +#define TIMER9_PERIOD 0xFFC01618 // Timer9 Period register +#define TIMER9_WIDTH 0xFFC0161C // Timer9 Width register +#define TIMER10_CONFIG 0xFFC01620 // Timer10 Configuration + // register +#define TIMER10_COUNTER 0xFFC01624 // Timer10 Counter register +#define TIMER10_PERIOD 0xFFC01628 // Timer10 Period register +#define TIMER10_WIDTH 0xFFC0162C // Timer10 Width register +#define TIMER11_CONFIG 0xFFC01630 // Timer11 Configuration + // register +#define TIMER11_COUNTER 0xFFC01634 // Timer11 Counter register +#define TIMER11_PERIOD 0xFFC01638 // Timer11 Period register +#define TIMER11_WIDTH 0xFFC0163C // Timer11 Width register + +#define TMRS4_ENABLE 0xFFC01640 // Timer Enable Register +#define TMRS4_DISABLE 0xFFC01644 // Timer Disable register +#define TMRS4_STATUS 0xFFC01648 // Timer Status register + +// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) +#define FIO0_FLAG_D 0xFFC00700 // Flag Data register +#define FIO0_FLAG_C 0xFFC00704 // Flag Clear register +#define FIO0_FLAG_S 0xFFC00708 // Flag Set register +#define FIO0_FLAG_T 0xFFC0070C // Flag Toggle register +#define FIO0_MASKA_D 0xFFC00710 // Flag Mask Interrupt A Data + // register +#define FIO0_MASKA_C 0xFFC00714 // Flag Mask Interrupt A Clear + // register +#define FIO0_MASKA_S 0xFFC00718 // Flag Mask Interrupt A Set + // register +#define FIO0_MASKA_T 0xFFC0071C // Flag Mask Interrupt A Toggle + // register +#define FIO0_MASKB_D 0xFFC00720 // Flag Mask Interrupt B Data + // register +#define FIO0_MASKB_C 0xFFC00724 // Flag Mask Interrupt B Clear + // register +#define FIO0_MASKB_S 0xFFC00728 // Flag Mask Interrupt B Set + // register +#define FIO0_MASKB_T 0xFFC0072C // Flag Mask Interrupt B Toggle + // register +#define FIO0_DIR 0xFFC00730 // Flag Direction register +#define FIO0_POLAR 0xFFC00734 // Flag Polarity register +#define FIO0_EDGE 0xFFC00738 // Flag Interrupt Sensitivity + // register +#define FIO0_BOTH 0xFFC0073C // Flag Set on Both Edges + // register +#define FIO0_INEN 0xFFC00740 // Flag Input Enable register + +// Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) +#define FIO1_FLAG_D 0xFFC01500 // Flag Data register +#define FIO1_FLAG_C 0xFFC01504 // Flag Clear register +#define FIO1_FLAG_S 0xFFC01508 // Flag Set register +#define FIO1_FLAG_T 0xFFC0150C // Flag Toggle register +#define FIO1_MASKA_D 0xFFC01510 // Flag Mask Interrupt A Data + // register +#define FIO1_MASKA_C 0xFFC01514 // Flag Mask Interrupt A Clear + // register +#define FIO1_MASKA_S 0xFFC01518 // Flag Mask Interrupt A Set + // register +#define FIO1_MASKA_T 0xFFC0151C // Flag Mask Interrupt A Toggle + // register +#define FIO1_MASKB_D 0xFFC01520 // Flag Mask Interrupt B Data + // register +#define FIO1_MASKB_C 0xFFC01524 // Flag Mask Interrupt B Clear + // register +#define FIO1_MASKB_S 0xFFC01528 // Flag Mask Interrupt B Set + // register +#define FIO1_MASKB_T 0xFFC0152C // Flag Mask Interrupt B Toggle + // register +#define FIO1_DIR 0xFFC01530 // Flag Direction register +#define FIO1_POLAR 0xFFC01534 // Flag Polarity register +#define FIO1_EDGE 0xFFC01538 // Flag Interrupt Sensitivity + // register +#define FIO1_BOTH 0xFFC0153C // Flag Set on Both Edges + // register +#define FIO1_INEN 0xFFC01540 // Flag Input Enable register + +// Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) +#define FIO2_FLAG_D 0xFFC01700 // Flag Data register +#define FIO2_FLAG_C 0xFFC01704 // Flag Clear register +#define FIO2_FLAG_S 0xFFC01708 // Flag Set register +#define FIO2_FLAG_T 0xFFC0170C // Flag Toggle register +#define FIO2_MASKA_D 0xFFC01710 // Flag Mask Interrupt A Data + // register +#define FIO2_MASKA_C 0xFFC01714 // Flag Mask Interrupt A Clear + // register +#define FIO2_MASKA_S 0xFFC01718 // Flag Mask Interrupt A Set + // register +#define FIO2_MASKA_T 0xFFC0171C // Flag Mask Interrupt A Toggle + // register +#define FIO2_MASKB_D 0xFFC01720 // Flag Mask Interrupt B Data + // register +#define FIO2_MASKB_C 0xFFC01724 // Flag Mask Interrupt B Clear + // register +#define FIO2_MASKB_S 0xFFC01728 // Flag Mask Interrupt B Set + // register +#define FIO2_MASKB_T 0xFFC0172C // Flag Mask Interrupt B Toggle + // register +#define FIO2_DIR 0xFFC01730 // Flag Direction register +#define FIO2_POLAR 0xFFC01734 // Flag Polarity register +#define FIO2_EDGE 0xFFC01738 // Flag Interrupt Sensitivity + // register +#define FIO2_BOTH 0xFFC0173C // Flag Set on Both Edges + // register +#define FIO2_INEN 0xFFC01740 // Flag Input Enable register + +//// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) +#define SPORT0_TCR1 0xFFC00800 // SPORT0 Transmit + // Configuration 1 Register +#define SPORT0_TCR2 0xFFC00804 // SPORT0 Transmit + // Configuration 2 Register +#define SPORT0_TCLKDIV 0xFFC00808 // SPORT0 Transmit Clock Divider +#define SPORT0_TFSDIV 0xFFC0080C // SPORT0 Transmit + // Frame Sync Divider +#define SPORT0_TX 0xFFC00810 // SPORT0 TX Data Register +#define SPORT0_RX 0xFFC00818 // SPORT0 RX Data Register +#define SPORT0_RCR1 0xFFC00820 // SPORT0 Transmit + // Configuration 1 Register +#define SPORT0_RCR2 0xFFC00824 // SPORT0 Transmit + // Configuration 2 Register +#define SPORT0_RCLKDIV 0xFFC00828 // SPORT0 Receive Clock Divider +#define SPORT0_RFSDIV 0xFFC0082C // SPORT0 Receive + // Frame Sync Divider +#define SPORT0_STAT 0xFFC00830 // SPORT0 Status Register +#define SPORT0_CHNL 0xFFC00834 // SPORT0 Current + // Channel Register +#define SPORT0_MCMC1 0xFFC00838 // SPORT0 Multi-Channel + // Configuration Register 1 +#define SPORT0_MCMC2 0xFFC0083C // SPORT0 Multi-Channel + // Configuration Register 2 +#define SPORT0_MTCS0 0xFFC00840 // SPORT0 Multi-Channel + // Transmit Select Register 0 +#define SPORT0_MTCS1 0xFFC00844 // SPORT0 Multi-Channel + // Transmit Select Register 1 +#define SPORT0_MTCS2 0xFFC00848 // SPORT0 Multi-Channel + // Transmit Select Register 2 +#define SPORT0_MTCS3 0xFFC0084C // SPORT0 Multi-Channel + // Transmit Select Register 3 +#define SPORT0_MRCS0 0xFFC00850 // SPORT0 Multi-Channel + // Receive Select Register 0 +#define SPORT0_MRCS1 0xFFC00854 // SPORT0 Multi-Channel + // Receive Select Register 1 +#define SPORT0_MRCS2 0xFFC00858 // SPORT0 Multi-Channel + // Receive Select Register 2 +#define SPORT0_MRCS3 0xFFC0085C // SPORT0 Multi-Channel + // Receive Select Register 3 + +//// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) +#define SPORT1_TCR1 0xFFC00900 // SPORT1 Transmit + // Configuration 1 Register +#define SPORT1_TCR2 0xFFC00904 // SPORT1 Transmit + // Configuration 2 Register +#define SPORT1_TCLKDIV 0xFFC00908 // SPORT1 Transmit Clock Divider +#define SPORT1_TFSDIV 0xFFC0090C // SPORT1 Transmit + // Frame Sync Divider +#define SPORT1_TX 0xFFC00910 // SPORT1 TX Data Register +#define SPORT1_RX 0xFFC00918 // SPORT1 RX Data Register +#define SPORT1_RCR1 0xFFC00920 // SPORT1 Transmit + // Configuration 1 Register +#define SPORT1_RCR2 0xFFC00924 // SPORT1 Transmit + // Configuration 2 Register +#define SPORT1_RCLKDIV 0xFFC00928 // SPORT1 Receive Clock Divider +#define SPORT1_RFSDIV 0xFFC0092C // SPORT1 Receive + // Frame Sync Divider +#define SPORT1_STAT 0xFFC00930 // SPORT1 Status Register +#define SPORT1_CHNL 0xFFC00934 // SPORT1 Current + // Channel Register +#define SPORT1_MCMC1 0xFFC00938 // SPORT1 Multi-Channel + // Configuration Register 1 +#define SPORT1_MCMC2 0xFFC0093C // SPORT1 Multi-Channel + // Configuration Register 2 +#define SPORT1_MTCS0 0xFFC00940 // SPORT1 Multi-Channel + // Transmit Select Register 0 +#define SPORT1_MTCS1 0xFFC00944 // SPORT1 Multi-Channel + // Transmit Select Register 1 +#define SPORT1_MTCS2 0xFFC00948 // SPORT1 Multi-Channel + // Transmit Select Register 2 +#define SPORT1_MTCS3 0xFFC0094C // SPORT1 Multi-Channel + // Transmit Select Register 3 +#define SPORT1_MRCS0 0xFFC00950 // SPORT1 Multi-Channel + // Receive Select Register 0 +#define SPORT1_MRCS1 0xFFC00954 // SPORT1 Multi-Channel + // Receive Select Register 1 +#define SPORT1_MRCS2 0xFFC00958 // SPORT1 Multi-Channel + // Receive Select Register 2 +#define SPORT1_MRCS3 0xFFC0095C // SPORT1 Multi-Channel + // Receive Select Register 3 + +// Asynchronous Memory Controller - External Bus Interface Unit +#define EBIU_AMGCTL 0xFFC00A00 // Asynchronous Memory + // Global Control Register +#define EBIU_AMBCTL0 0xFFC00A04 // Asynchronous Memory + // Bank Control Register 0 +#define EBIU_AMBCTL1 0xFFC00A08 // Asynchronous Memory + // Bank Control Register 1 + +// SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) +#define EBIU_SDGCTL 0xFFC00A10 // SDRAM Global Control + // Register +#define EBIU_SDBCTL 0xFFC00A14 // SDRAM Bank Control Register +#define EBIU_SDRRC 0xFFC00A18 // SDRAM Refresh Rate Control + // Register +#define EBIU_SDSTAT 0xFFC00A1C // SDRAM Status Register + +// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) +#define PPI0_CONTROL 0xFFC01000 // PPI0 Control register +#define PPI0_STATUS 0xFFC01004 // PPI0 Status register +#define PPI0_COUNT 0xFFC01008 // PPI0 Transfer Count register +#define PPI0_DELAY 0xFFC0100C // PPI0 Delay Count register +#define PPI0_FRAME 0xFFC01010 // PPI0 Frame Length register + +//Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) +#define PPI1_CONTROL 0xFFC01300 // PPI1 Control register +#define PPI1_STATUS 0xFFC01304 // PPI1 Status register +#define PPI1_COUNT 0xFFC01308 // PPI1 Transfer Count register +#define PPI1_DELAY 0xFFC0130C // PPI1 Delay Count register +#define PPI1_FRAME 0xFFC01310 // PPI1 Frame Length register + +// DMA Traffic controls +#define DMA_TCPER 0xFFC00B0C // Traffic Control Periods + // Register +#define DMA_TCCNT 0xFFC00B10 // Traffic Control Current + // Counts Register +#define DMA_TC_PER 0xFFC00B0C // Traffic Control Periods + // Register +#define DMA_TC_CNT 0xFFC00B10 // Traffic Control Current + // Counts Register + +// DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) +#define DMA1_0_CONFIG 0xFFC01C08 // DMA1 Channel 0 Configuration + // register +#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 // DMA1 Channel 0 Next + // Descripter Ptr Reg +#define DMA1_0_START_ADDR 0xFFC01C04 // DMA1 Channel 0 Start Address +#define DMA1_0_X_COUNT 0xFFC01C10 // DMA1 Channel 0 Inner Loop + // Count +#define DMA1_0_Y_COUNT 0xFFC01C18 // DMA1 Channel 0 Outer Loop + // Count +#define DMA1_0_X_MODIFY 0xFFC01C14 // DMA1 Channel 0 Inner Loop + // Addr Increment +#define DMA1_0_Y_MODIFY 0xFFC01C1C // DMA1 Channel 0 Outer Loop + // Addr Increment +#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 // DMA1 Channel 0 Current + // Descriptor Pointer +#define DMA1_0_CURR_ADDR 0xFFC01C24 // DMA1 Channel 0 Current + // Address Pointer +#define DMA1_0_CURR_X_COUNT 0xFFC01C30 // DMA1 Channel 0 Current Inner + // Loop Count +#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 // DMA1 Channel 0 Current Outer + // Loop Count +#define DMA1_0_IRQ_STATUS 0xFFC01C28 // DMA1 Channel 0 Interrupt + // Status Register +#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C // DMA1 Channel 0 Peripheral + // Map Register + +#define DMA1_1_CONFIG 0xFFC01C48 // DMA1 Channel 1 Configuration + // register +#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 // DMA1 Channel 1 Next + // Descripter Ptr Reg +#define DMA1_1_START_ADDR 0xFFC01C44 // DMA1 Channel 1 Start Address +#define DMA1_1_X_COUNT 0xFFC01C50 // DMA1 Channel 1 Inner Loop + // Count +#define DMA1_1_Y_COUNT 0xFFC01C58 // DMA1 Channel 1 Outer Loop + // Count +#define DMA1_1_X_MODIFY 0xFFC01C54 // DMA1 Channel 1 Inner Loop + // Addr Increment +#define DMA1_1_Y_MODIFY 0xFFC01C5C // DMA1 Channel 1 Outer Loop + // Addr Increment +#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 // DMA1 Channel 1 Current + // Descriptor Pointer +#define DMA1_1_CURR_ADDR 0xFFC01C64 // DMA1 Channel 1 Current + // Address Pointer +#define DMA1_1_CURR_X_COUNT 0xFFC01C70 // DMA1 Channel 1 Current Inner + // Loop Count +#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 // DMA1 Channel 1 Current Outer + // Loop Count +#define DMA1_1_IRQ_STATUS 0xFFC01C68 // DMA1 Channel 1 Interrupt + // Status Register +#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C // DMA1 Channel 1 Peripheral + // Map Register + +#define DMA1_2_CONFIG 0xFFC01C88 // DMA1 Channel 2 Configuration + // register +#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 // DMA1 Channel 2 Next + // Descripter Ptr Reg +#define DMA1_2_START_ADDR 0xFFC01C84 // DMA1 Channel 2 Start Address +#define DMA1_2_X_COUNT 0xFFC01C90 // DMA1 Channel 2 Inner Loop + // Count +#define DMA1_2_Y_COUNT 0xFFC01C98 // DMA1 Channel 2 Outer Loop + // Count +#define DMA1_2_X_MODIFY 0xFFC01C94 // DMA1 Channel 2 Inner Loop + // Addr Increment +#define DMA1_2_Y_MODIFY 0xFFC01C9C // DMA1 Channel 2 Outer Loop + // Addr Increment +#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 // DMA1 Channel 2 Current + // Descriptor Pointer +#define DMA1_2_CURR_ADDR 0xFFC01CA4 // DMA1 Channel 2 Current + // Address Pointer +#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 // DMA1 Channel 2 Current Inner + // Loop Count +#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 // DMA1 Channel 2 Current Outer + // Loop Count +#define DMA1_2_IRQ_STATUS 0xFFC01CA8 // DMA1 Channel 2 Interrupt + // Status Register +#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC // DMA1 Channel 2 Peripheral + // Map Register + +#define DMA1_3_CONFIG 0xFFC01CC8 // DMA1 Channel 3 Configuration + // register +#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 // DMA1 Channel 3 Next + // Descripter Ptr Reg +#define DMA1_3_START_ADDR 0xFFC01CC4 // DMA1 Channel 3 Start Address +#define DMA1_3_X_COUNT 0xFFC01CD0 // DMA1 Channel 3 Inner Loop + // Count +#define DMA1_3_Y_COUNT 0xFFC01CD8 // DMA1 Channel 3 Outer Loop + // Count +#define DMA1_3_X_MODIFY 0xFFC01CD4 // DMA1 Channel 3 Inner Loop + // Addr Increment +#define DMA1_3_Y_MODIFY 0xFFC01CDC // DMA1 Channel 3 Outer Loop + // Addr Increment +#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 // DMA1 Channel 3 Current + // Descriptor Pointer +#define DMA1_3_CURR_ADDR 0xFFC01CE4 // DMA1 Channel 3 Current + // Address Pointer +#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 // DMA1 Channel 3 Current Inner + // Loop Count +#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 // DMA1 Channel 3 Current Outer + // Loop Count +#define DMA1_3_IRQ_STATUS 0xFFC01CE8 // DMA1 Channel 3 Interrupt + // Status Register +#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC // DMA1 Channel 3 Peripheral + // Map Register + +#define DMA1_4_CONFIG 0xFFC01D08 // DMA1 Channel 4 Configuration + // register +#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 // DMA1 Channel 4 Next + // Descripter Ptr Reg +#define DMA1_4_START_ADDR 0xFFC01D04 // DMA1 Channel 4 Start Address +#define DMA1_4_X_COUNT 0xFFC01D10 // DMA1 Channel 4 Inner Loop + // Count +#define DMA1_4_Y_COUNT 0xFFC01D18 // DMA1 Channel 4 Outer Loop + // Count +#define DMA1_4_X_MODIFY 0xFFC01D14 // DMA1 Channel 4 Inner Loop + // Addr Increment +#define DMA1_4_Y_MODIFY 0xFFC01D1C // DMA1 Channel 4 Outer Loop + // Addr Increment +#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 // DMA1 Channel 4 Current + // Descriptor Pointer +#define DMA1_4_CURR_ADDR 0xFFC01D24 // DMA1 Channel 4 Current + // Address Pointer +#define DMA1_4_CURR_X_COUNT 0xFFC01D30 // DMA1 Channel 4 Current Inner + // Loop Count +#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 // DMA1 Channel 4 Current Outer + // Loop Count +#define DMA1_4_IRQ_STATUS 0xFFC01D28 // DMA1 Channel 4 Interrupt + // Status Register +#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C // DMA1 Channel 4 Peripheral + // Map Register + +#define DMA1_5_CONFIG 0xFFC01D48 // DMA1 Channel 5 Configuration + // register +#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 // DMA1 Channel 5 Next + // Descripter Ptr Reg +#define DMA1_5_START_ADDR 0xFFC01D44 // DMA1 Channel 5 Start Address +#define DMA1_5_X_COUNT 0xFFC01D50 // DMA1 Channel 5 Inner Loop + // Count +#define DMA1_5_Y_COUNT 0xFFC01D58 // DMA1 Channel 5 Outer Loop + // Count +#define DMA1_5_X_MODIFY 0xFFC01D54 // DMA1 Channel 5 Inner Loop + // Addr Increment +#define DMA1_5_Y_MODIFY 0xFFC01D5C // DMA1 Channel 5 Outer Loop + // Addr Increment +#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 // DMA1 Channel 5 Current + // Descriptor Pointer +#define DMA1_5_CURR_ADDR 0xFFC01D64 // DMA1 Channel 5 Current + // Address Pointer +#define DMA1_5_CURR_X_COUNT 0xFFC01D70 // DMA1 Channel 5 Current Inner + // Loop Count +#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 // DMA1 Channel 5 Current Outer + // Loop Count +#define DMA1_5_IRQ_STATUS 0xFFC01D68 // DMA1 Channel 5 Interrupt + // Status Register +#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C // DMA1 Channel 5 Peripheral + // Map Register + +#define DMA1_6_CONFIG 0xFFC01D88 // DMA1 Channel 6 Configuration + // register +#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 // DMA1 Channel 6 Next + // Descripter Ptr Reg +#define DMA1_6_START_ADDR 0xFFC01D84 // DMA1 Channel 6 Start Address +#define DMA1_6_X_COUNT 0xFFC01D90 // DMA1 Channel 6 Inner Loop + // Count +#define DMA1_6_Y_COUNT 0xFFC01D98 // DMA1 Channel 6 Outer Loop + // Count +#define DMA1_6_X_MODIFY 0xFFC01D94 // DMA1 Channel 6 Inner Loop + // Addr Increment +#define DMA1_6_Y_MODIFY 0xFFC01D9C // DMA1 Channel 6 Outer Loop + // Addr Increment +#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 // DMA1 Channel 6 Current + // Descriptor Pointer +#define DMA1_6_CURR_ADDR 0xFFC01DA4 // DMA1 Channel 6 Current + // Address Pointer +#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 // DMA1 Channel 6 Current Inner + // Loop Count +#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 // DMA1 Channel 6 Current Outer + // Loop Count +#define DMA1_6_IRQ_STATUS 0xFFC01DA8 // DMA1 Channel 6 Interrupt + // /Status Register +#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC // DMA1 Channel 6 Peripheral + // Map Register + +#define DMA1_7_CONFIG 0xFFC01DC8 // DMA1 Channel 7 Configuration + // register +#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 // DMA1 Channel 7 Next + // Descripter Ptr Reg +#define DMA1_7_START_ADDR 0xFFC01DC4 // DMA1 Channel 7 Start Address +#define DMA1_7_X_COUNT 0xFFC01DD0 // DMA1 Channel 7 Inner Loop + // Count +#define DMA1_7_Y_COUNT 0xFFC01DD8 // DMA1 Channel 7 Outer Loop + // Count +#define DMA1_7_X_MODIFY 0xFFC01DD4 // DMA1 Channel 7 Inner Loop + // Addr Increment +#define DMA1_7_Y_MODIFY 0xFFC01DDC // DMA1 Channel 7 Outer Loop + // Addr Increment +#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 // DMA1 Channel 7 Current + // Descriptor Pointer +#define DMA1_7_CURR_ADDR 0xFFC01DE4 // DMA1 Channel 7 Current + // Address Pointer +#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 // DMA1 Channel 7 Current Inner + // Loop Count +#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 // DMA1 Channel 7 Current Outer + // Loop Count +#define DMA1_7_IRQ_STATUS 0xFFC01DE8 // DMA1 Channel 7 Interrupt + // /Status Register +#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC // DMA1 Channel 7 Peripheral + // Map Register + +#define DMA1_8_CONFIG 0xFFC01E08 // DMA1 Channel 8 Configuration + // register +#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 // DMA1 Channel 8 Next + // Descripter Ptr Reg +#define DMA1_8_START_ADDR 0xFFC01E04 // DMA1 Channel 8 Start Address +#define DMA1_8_X_COUNT 0xFFC01E10 // DMA1 Channel 8 Inner Loop + // Count +#define DMA1_8_Y_COUNT 0xFFC01E18 // DMA1 Channel 8 Outer Loop + // Count +#define DMA1_8_X_MODIFY 0xFFC01E14 // DMA1 Channel 8 Inner Loop + // Addr Increment +#define DMA1_8_Y_MODIFY 0xFFC01E1C // DMA1 Channel 8 Outer Loop + // Addr Increment +#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 // DMA1 Channel 8 Current + // Descriptor Pointer +#define DMA1_8_CURR_ADDR 0xFFC01E24 // DMA1 Channel 8 Current + // Address Pointer +#define DMA1_8_CURR_X_COUNT 0xFFC01E30 // DMA1 Channel 8 Current Inner + // Loop Count +#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 // DMA1 Channel 8 Current Outer + // Loop Count +#define DMA1_8_IRQ_STATUS 0xFFC01E28 // DMA1 Channel 8 Interrupt + // /Status Register +#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C // DMA1 Channel 8 Peripheral + // Map Register + +#define DMA1_9_CONFIG 0xFFC01E48 // DMA1 Channel 9 Configuration + // register +#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 // DMA1 Channel 9 Next + // Descripter Ptr Reg +#define DMA1_9_START_ADDR 0xFFC01E44 // DMA1 Channel 9 Start Address +#define DMA1_9_X_COUNT 0xFFC01E50 // DMA1 Channel 9 Inner Loop + // Count +#define DMA1_9_Y_COUNT 0xFFC01E58 // DMA1 Channel 9 Outer Loop + // Count +#define DMA1_9_X_MODIFY 0xFFC01E54 // DMA1 Channel 9 Inner Loop + // Addr Increment +#define DMA1_9_Y_MODIFY 0xFFC01E5C // DMA1 Channel 9 Outer Loop + // Addr Increment +#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 // DMA1 Channel 9 Current + // Descriptor Pointer +#define DMA1_9_CURR_ADDR 0xFFC01E64 // DMA1 Channel 9 Current + // Address Pointer +#define DMA1_9_CURR_X_COUNT 0xFFC01E70 // DMA1 Channel 9 Current Inner + // Loop Count +#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 // DMA1 Channel 9 Current Outer + // Loop Count +#define DMA1_9_IRQ_STATUS 0xFFC01E68 // DMA1 Channel 9 Interrupt + // /Status Register +#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C // DMA1 Channel 9 Peripheral + // Map Register + +#define DMA1_10_CONFIG 0xFFC01E88 // DMA1 Channel 10 Configuration + // register +#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 // DMA1 Channel 10 Next + // Descripter Ptr Reg +#define DMA1_10_START_ADDR 0xFFC01E84 // DMA1 Channel 10 Start Address +#define DMA1_10_X_COUNT 0xFFC01E90 // DMA1 Channel 10 Inner Loop + // Count +#define DMA1_10_Y_COUNT 0xFFC01E98 // DMA1 Channel 10 Outer Loop + // Count +#define DMA1_10_X_MODIFY 0xFFC01E94 // DMA1 Channel 10 Inner Loop + // Addr Increment +#define DMA1_10_Y_MODIFY 0xFFC01E9C // DMA1 Channel 10 Outer Loop + // Addr Increment +#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 // DMA1 Channel 10 Current + // Descriptor Pointer +#define DMA1_10_CURR_ADDR 0xFFC01EA4 // DMA1 Channel 10 Current + // Address Pointer +#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 // DMA1 Channel 10 Current Inner + // Loop Count +#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 // DMA1 Channel 10 Current Outer + // Loop Count +#define DMA1_10_IRQ_STATUS 0xFFC01EA8 // DMA1 Channel 10 Interrupt + // /Status Register +#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC // DMA1 Channel 10 Peripheral + // Map Register + +#define DMA1_11_CONFIG 0xFFC01EC8 // DMA1 Channel 11 Configuration + // register +#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 // DMA1 Channel 11 Next + // Descripter Ptr Reg +#define DMA1_11_START_ADDR 0xFFC01EC4 // DMA1 Channel 11 Start Address +#define DMA1_11_X_COUNT 0xFFC01ED0 // DMA1 Channel 11 Inner Loop + // Count +#define DMA1_11_Y_COUNT 0xFFC01ED8 // DMA1 Channel 11 Outer Loop + // Count +#define DMA1_11_X_MODIFY 0xFFC01ED4 // DMA1 Channel 11 Inner Loop + // Addr Increment +#define DMA1_11_Y_MODIFY 0xFFC01EDC // DMA1 Channel 11 Outer Loop + // Addr Increment +#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 // DMA1 Channel 11 Current + // Descriptor Pointer +#define DMA1_11_CURR_ADDR 0xFFC01EE4 // DMA1 Channel 11 Current + // Address Pointer +#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 // DMA1 Channel 11 Current Inner + // Loop Count +#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 // DMA1 Channel 11 Current Outer + // Loop Count +#define DMA1_11_IRQ_STATUS 0xFFC01EE8 // DMA1 Channel 11 Interrupt + // /Status Register +#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC // DMA1 Channel 11 Peripheral + // Map Register + +// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) +#define MDMA1_D0_CONFIG 0xFFC01F08 // MemDMA1 Stream 0 Destination + // Configuration +#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 // MemDMA1 Stream 0 + // Destination Next + // Descriptor Ptr Reg +#define MDMA1_D0_START_ADDR 0xFFC01F04 // MemDMA1 Stream 0 Destination + // Start Address +#define MDMA1_D0_X_COUNT 0xFFC01F10 // MemDMA1 Stream 0 Destination + // Inner-Loop Count +#define MDMA1_D0_Y_COUNT 0xFFC01F18 // MemDMA1 Stream 0 Destination + // Outer-Loop Count +#define MDMA1_D0_X_MODIFY 0xFFC01F14 // MemDMA1 Stream 0 Dest + // Inner-Loop Address-Increment +#define MDMA1_D0_Y_MODIFY 0xFFC01F1C // MemDMA1 Stream 0 Dest + // Outer-Loop Address-Increment +#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 // MemDMA1 Stream 0 Dest + // Current Descriptor Ptr reg +#define MDMA1_D0_CURR_ADDR 0xFFC01F24 // MemDMA1 Stream 0 Destination + // Current Address +#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 // MemDMA1 Stream 0 Dest + // Current Inner-Loop Count +#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 // MemDMA1 Stream 0 Dest + // Current Outer-Loop Count +#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 // MemDMA1 Stream 0 Destination + // Interrupt/Status +#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C // MemDMA1 Stream 0 + // Destination Peripheral Map + +#define MDMA1_S0_CONFIG 0xFFC01F48 // MemDMA1 Stream 0 Source + // Configuration +#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 // MemDMA1 Stream 0 Source + // Next Descriptor Ptr Reg +#define MDMA1_S0_START_ADDR 0xFFC01F44 // MemDMA1 Stream 0 Source + // Start Address +#define MDMA1_S0_X_COUNT 0xFFC01F50 // MemDMA1 Stream 0 Source + // Inner-Loop Count +#define MDMA1_S0_Y_COUNT 0xFFC01F58 // MemDMA1 Stream 0 Source + // Outer-Loop Count +#define MDMA1_S0_X_MODIFY 0xFFC01F54 // MemDMA1 Stream 0 Source + // Inner-Loop Address-Increment +#define MDMA1_S0_Y_MODIFY 0xFFC01F5C // MemDMA1 Stream 0 Source + // Outer-Loop Address-Increment +#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 // MemDMA1 Stream 0 Source + // Current Descriptor Ptr reg +#define MDMA1_S0_CURR_ADDR 0xFFC01F64 // MemDMA1 Stream 0 Source + // Current Address +#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 // MemDMA1 Stream 0 Source + // Current Inner-Loop Count +#define MDMA1_S0_CURR_Y_COUNT ` 0xFFC01F78 // MemDMA1 Stream 0 Source + // Current Outer-Loop Count +#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 // MemDMA1 Stream 0 Source + // Interrupt/Status +#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C // MemDMA1 Stream 0 Source + // Peripheral Map + +#define MDMA1_D1_CONFIG 0xFFC01F88 // MemDMA1 Stream 1 Destination + // Configuration +#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 // MemDMA1 Stream 1 + // Destination Next + // Descriptor Ptr Reg +#define MDMA1_D1_START_ADDR 0xFFC01F84 // MemDMA1 Stream 1 Destination + // Start Address +#define MDMA1_D1_X_COUNT 0xFFC01F90 // MemDMA1 Stream 1 Destination + // Inner-Loop Count +#define MDMA1_D1_Y_COUNT 0xFFC01F98 // MemDMA1 Stream 1 Destination + // Outer-Loop Count +#define MDMA1_D1_X_MODIFY 0xFFC01F94 // MemDMA1 Stream 1 Dest + // Inner-Loop Address-Increment +#define MDMA1_D1_Y_MODIFY 0xFFC01F9C // MemDMA1 Stream 1 Dest + // Outer-Loop Address-Increment +#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 // MemDMA1 Stream 1 Dest + // Current Descriptor Ptr reg +#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 // MemDMA1 Stream 1 Dest + // Current Address +#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 // MemDMA1 Stream 1 Dest + // Current Inner-Loop Count +#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 // MemDMA1 Stream 1 Dest + // Current Outer-Loop Count +#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 // MemDMA1 Stream 1 Dest + // Interrupt/Status +#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC // MemDMA1 Stream 1 Dest + // Peripheral Map + +#define MDMA1_S1_CONFIG 0xFFC01FC8 // MemDMA1 Stream 1 Source + // Configuration +#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 // MemDMA1 Stream 1 Source + // Next Descriptor Ptr Reg +#define MDMA1_S1_START_ADDR 0xFFC01FC4 // MemDMA1 Stream 1 Source + // Start Address +#define MDMA1_S1_X_COUNT 0xFFC01FD0 // MemDMA1 Stream 1 Source + // Inner-Loop Count +#define MDMA1_S1_Y_COUNT 0xFFC01FD8 // MemDMA1 Stream 1 Source + // Outer-Loop Count +#define MDMA1_S1_X_MODIFY 0xFFC01FD4 // MemDMA1 Stream 1 Source + // Inner-Loop Address-Increment +#define MDMA1_S1_Y_MODIFY 0xFFC01FDC // MemDMA1 Stream 1 Source + // Outer-Loop Address-Increment +#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 // MemDMA1 Stream 1 Source + // Current Descriptor Ptr reg +#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 // MemDMA1 Stream 1 Source + // Current Address +#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 // MemDMA1 Stream 1 Source + // Current Inner-Loop Count +#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 // MemDMA1 Stream 1 Source + // Current Outer-Loop Count +#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 // MemDMA1 Stream 1 Source + // Interrupt/Status +#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC // MemDMA1 Stream 1 Source + // Peripheral Map + +// DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) +#define DMA2_0_CONFIG 0xFFC00C08 // DMA2 Channel 0 Configuration + // register +#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 // DMA2 Channel 0 Next + // Descripter Ptr Reg +#define DMA2_0_START_ADDR 0xFFC00C04 // DMA2 Channel 0 Start Address +#define DMA2_0_X_COUNT 0xFFC00C10 // DMA2 Channel 0 Inner Loop + // Count +#define DMA2_0_Y_COUNT 0xFFC00C18 // DMA2 Channel 0 Outer Loop + // Count +#define DMA2_0_X_MODIFY 0xFFC00C14 // DMA2 Channel 0 Inner Loop + // Addr Increment +#define DMA2_0_Y_MODIFY 0xFFC00C1C // DMA2 Channel 0 Outer Loop + // Addr Increment +#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 // DMA2 Channel 0 Current + // Descriptor Pointer +#define DMA2_0_CURR_ADDR 0xFFC00C24 // DMA2 Channel 0 Current + // Address Pointer +#define DMA2_0_CURR_X_COUNT 0xFFC00C30 // DMA2 Channel 0 Current Inner + // Loop Count +#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 // DMA2 Channel 0 Current Outer + // Loop Count +#define DMA2_0_IRQ_STATUS 0xFFC00C28 // DMA2 Channel 0 Interrupt + // /Status Register +#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C // DMA2 Channel 0 Peripheral + // Map Register + +#define DMA2_1_CONFIG 0xFFC00C48 // DMA2 Channel 1 Configuration + // register +#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 // DMA2 Channel 1 Next + // Descripter Ptr Reg +#define DMA2_1_START_ADDR 0xFFC00C44 // DMA2 Channel 1 Start Address +#define DMA2_1_X_COUNT 0xFFC00C50 // DMA2 Channel 1 Inner Loop + // Count +#define DMA2_1_Y_COUNT 0xFFC00C58 // DMA2 Channel 1 Outer Loop + // Count +#define DMA2_1_X_MODIFY 0xFFC00C54 // DMA2 Channel 1 Inner Loop + // Addr Increment +#define DMA2_1_Y_MODIFY 0xFFC00C5C // DMA2 Channel 1 Outer Loop + // Addr Increment +#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 // DMA2 Channel 1 Current + // Descriptor Pointer +#define DMA2_1_CURR_ADDR 0xFFC00C64 // DMA2 Channel 1 Current + // Address Pointer +#define DMA2_1_CURR_X_COUNT 0xFFC00C70 // DMA2 Channel 1 Current + // Inner Loop Count +#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 // DMA2 Channel 1 Current + // Outer Loop Count +#define DMA2_1_IRQ_STATUS 0xFFC00C68 // DMA2 Channel 1 Interrupt + // /Status Register +#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C // DMA2 Channel 1 Peripheral + // Map Register + +#define DMA2_2_CONFIG 0xFFC00C88 // DMA2 Channel 2 Configuration + // register +#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 // DMA2 Channel 2 Next + // Descripter Ptr Reg +#define DMA2_2_START_ADDR 0xFFC00C84 // DMA2 Channel 2 Start Address +#define DMA2_2_X_COUNT 0xFFC00C90 // DMA2 Channel 2 Inner Loop + // Count +#define DMA2_2_Y_COUNT 0xFFC00C98 // DMA2 Channel 2 Outer Loop + // Count +#define DMA2_2_X_MODIFY 0xFFC00C94 // DMA2 Channel 2 Inner Loop + // Addr Increment +#define DMA2_2_Y_MODIFY 0xFFC00C9C // DMA2 Channel 2 Outer Loop + // Addr Increment +#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 // DMA2 Channel 2 Current + // Descriptor Pointer +#define DMA2_2_CURR_ADDR 0xFFC00CA4 // DMA2 Channel 2 Current + // Address Pointer +#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 // DMA2 Channel 2 Current Inner + // Loop Count +#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 // DMA2 Channel 2 Current Outer + // Loop Count +#define DMA2_2_IRQ_STATUS 0xFFC00CA8 // DMA2 Channel 2 Interrupt + // /Status Register +#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC // DMA2 Channel 2 Peripheral + // Map Register + +#define DMA2_3_CONFIG 0xFFC00CC8 // DMA2 Channel 3 Configuration + // register +#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 // DMA2 Channel 3 Next + // Descripter Ptr Reg +#define DMA2_3_START_ADDR 0xFFC00CC4 // DMA2 Channel 3 Start Address +#define DMA2_3_X_COUNT 0xFFC00CD0 // DMA2 Channel 3 Inner Loop + // Count +#define DMA2_3_Y_COUNT 0xFFC00CD8 // DMA2 Channel 3 Outer Loop + // Count +#define DMA2_3_X_MODIFY 0xFFC00CD4 // DMA2 Channel 3 Inner Loop + // Addr Increment +#define DMA2_3_Y_MODIFY 0xFFC00CDC // DMA2 Channel 3 Outer Loop + // Addr Increment +#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 // DMA2 Channel 3 Current + // Descriptor Pointer +#define DMA2_3_CURR_ADDR 0xFFC00CE4 // DMA2 Channel 3 Current + // Address Pointer +#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 // DMA2 Channel 3 Current Inner + // Loop Count +#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 // DMA2 Channel 3 Current Outer + // Loop Count +#define DMA2_3_IRQ_STATUS 0xFFC00CE8 // DMA2 Channel 3 Interrupt + // /Status Register +#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC // DMA2 Channel 3 Peripheral + // Map Register + +#define DMA2_4_CONFIG 0xFFC00D08 // DMA2 Channel 4 Configuration + // register +#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 // DMA2 Channel 4 Next + // Descripter Ptr Reg +#define DMA2_4_START_ADDR 0xFFC00D04 // DMA2 Channel 4 Start Address +#define DMA2_4_X_COUNT 0xFFC00D10 // DMA2 Channel 4 Inner Loop + // Count +#define DMA2_4_Y_COUNT 0xFFC00D18 // DMA2 Channel 4 Outer Loop + // Count +#define DMA2_4_X_MODIFY 0xFFC00D14 // DMA2 Channel 4 Inner Loop + // Addr Increment +#define DMA2_4_Y_MODIFY 0xFFC00D1C // DMA2 Channel 4 Outer Loop + // Addr Increment +#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 // DMA2 Channel 4 Current + // Descriptor Pointer +#define DMA2_4_CURR_ADDR 0xFFC00D24 // DMA2 Channel 4 Current + // Address Pointer +#define DMA2_4_CURR_X_COUNT 0xFFC00D30 // DMA2 Channel 4 Current Inner + // Loop Count +#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 // DMA2 Channel 4 Current Outer + // Loop Count +#define DMA2_4_IRQ_STATUS 0xFFC00D28 // DMA2 Channel 4 Interrupt + // /Status Register +#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C // DMA2 Channel 4 Peripheral + // Map Register + +#define DMA2_5_CONFIG 0xFFC00D48 // DMA2 Channel 5 Configuration + // register +#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 // DMA2 Channel 5 Next + // Descripter Ptr Reg +#define DMA2_5_START_ADDR 0xFFC00D44 // DMA2 Channel 5 Start Address +#define DMA2_5_X_COUNT 0xFFC00D50 // DMA2 Channel 5 Inner Loop + // Count +#define DMA2_5_Y_COUNT 0xFFC00D58 // DMA2 Channel 5 Outer Loop + // Count +#define DMA2_5_X_MODIFY 0xFFC00D54 // DMA2 Channel 5 Inner Loop + // Addr Increment +#define DMA2_5_Y_MODIFY 0xFFC00D5C // DMA2 Channel 5 Outer Loop + // Addr Increment +#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 // DMA2 Channel 5 Current + // Descriptor Pointer +#define DMA2_5_CURR_ADDR 0xFFC00D64 // DMA2 Channel 5 Current + // Address Pointer +#define DMA2_5_CURR_X_COUNT 0xFFC00D70 // DMA2 Channel 5 Current Inner + // Loop Count +#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 // DMA2 Channel 5 Current Outer + // Loop Count +#define DMA2_5_IRQ_STATUS 0xFFC00D68 // DMA2 Channel 5 Interrupt + // /Status Register +#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C // DMA2 Channel 5 Peripheral + // Map Register + +#define DMA2_6_CONFIG 0xFFC00D88 // DMA2 Channel 6 Configuration + // register +#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 // DMA2 Channel 6 Next + // Descripter Ptr Reg +#define DMA2_6_START_ADDR 0xFFC00D84 // DMA2 Channel 6 Start Address +#define DMA2_6_X_COUNT 0xFFC00D90 // DMA2 Channel 6 Inner Loop + // Count +#define DMA2_6_Y_COUNT 0xFFC00D98 // DMA2 Channel 6 Outer Loop + // Count +#define DMA2_6_X_MODIFY 0xFFC00D94 // DMA2 Channel 6 Inner Loop + // Addr Increment +#define DMA2_6_Y_MODIFY 0xFFC00D9C // DMA2 Channel 6 Outer Loop + // Addr Increment +#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 // DMA2 Channel 6 Current + // Descriptor Pointer +#define DMA2_6_CURR_ADDR 0xFFC00DA4 // DMA2 Channel 6 Current + // Address Pointer +#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 // DMA2 Channel 6 Current Inner + // Loop Count +#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 // DMA2 Channel 6 Current Outer + // Loop Count +#define DMA2_6_IRQ_STATUS 0xFFC00DA8 // DMA2 Channel 6 Interrupt + // /Status Register +#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC // DMA2 Channel 6 Peripheral + // Map Register + +#define DMA2_7_CONFIG 0xFFC00DC8 // DMA2 Channel 7 Configuration + // register +#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 // DMA2 Channel 7 Next + // Descripter Ptr Reg +#define DMA2_7_START_ADDR 0xFFC00DC4 // DMA2 Channel 7 Start Address +#define DMA2_7_X_COUNT 0xFFC00DD0 // DMA2 Channel 7 Inner Loop + // Count +#define DMA2_7_Y_COUNT 0xFFC00DD8 // DMA2 Channel 7 Outer Loop + // Count +#define DMA2_7_X_MODIFY 0xFFC00DD4 // DMA2 Channel 7 Inner Loop + // Addr Increment +#define DMA2_7_Y_MODIFY 0xFFC00DDC // DMA2 Channel 7 Outer Loop + // Addr Increment +#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 // DMA2 Channel 7 Current + // Descriptor Pointer +#define DMA2_7_CURR_ADDR 0xFFC00DE4 // DMA2 Channel 7 Current + // Address Pointer +#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 // DMA2 Channel 7 Current Inner + // Loop Count +#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 // DMA2 Channel 7 Current Outer + // Loop Count +#define DMA2_7_IRQ_STATUS 0xFFC00DE8 // DMA2 Channel 7 Interrupt + // /Status Register +#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC // DMA2 Channel 7 Peripheral + // Map Register + +#define DMA2_8_CONFIG 0xFFC00E08 // DMA2 Channel 8 Configuration + // register +#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 // DMA2 Channel 8 Next + // Descripter Ptr Reg +#define DMA2_8_START_ADDR 0xFFC00E04 // DMA2 Channel 8 Start Address +#define DMA2_8_X_COUNT 0xFFC00E10 // DMA2 Channel 8 Inner Loop + // Count +#define DMA2_8_Y_COUNT 0xFFC00E18 // DMA2 Channel 8 Outer Loop + // Count +#define DMA2_8_X_MODIFY 0xFFC00E14 // DMA2 Channel 8 Inner Loop + // Addr Increment +#define DMA2_8_Y_MODIFY 0xFFC00E1C // DMA2 Channel 8 Outer Loop + // Addr Increment +#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 // DMA2 Channel 8 Current + // Descriptor Pointer +#define DMA2_8_CURR_ADDR 0xFFC00E24 // DMA2 Channel 8 Current + // Address Pointer +#define DMA2_8_CURR_X_COUNT 0xFFC00E30 // DMA2 Channel 8 Current Inner + // Loop Count +#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 // DMA2 Channel 8 Current Outer + // Loop Count +#define DMA2_8_IRQ_STATUS 0xFFC00E28 // DMA2 Channel 8 Interrupt + // /Status Register +#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C // DMA2 Channel 8 Peripheral + // Map Register + +#define DMA2_9_CONFIG 0xFFC00E48 // DMA2 Channel 9 Configuration + // register +#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 // DMA2 Channel 9 Next + // Descripter Ptr Reg +#define DMA2_9_START_ADDR 0xFFC00E44 // DMA2 Channel 9 Start Address +#define DMA2_9_X_COUNT 0xFFC00E50 // DMA2 Channel 9 Inner Loop + // Count +#define DMA2_9_Y_COUNT 0xFFC00E58 // DMA2 Channel 9 Outer Loop + // Count +#define DMA2_9_X_MODIFY 0xFFC00E54 // DMA2 Channel 9 Inner Loop + // Addr Increment +#define DMA2_9_Y_MODIFY 0xFFC00E5C // DMA2 Channel 9 Outer Loop + // Addr Increment +#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 // DMA2 Channel 9 Current + // Descriptor Pointer +#define DMA2_9_CURR_ADDR 0xFFC00E64 // DMA2 Channel 9 Current + // Address Pointer +#define DMA2_9_CURR_X_COUNT 0xFFC00E70 // DMA2 Channel 9 Current Inner + // Loop Count +#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 // DMA2 Channel 9 Current Outer + // Loop Count +#define DMA2_9_IRQ_STATUS 0xFFC00E68 // DMA2 Channel 9 Interrupt + // /Status Register +#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C // DMA2 Channel 9 Peripheral + // Map Register + +#define DMA2_10_CONFIG 0xFFC00E88 // DMA2 Channel 10 Configuration + // register +#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 // DMA2 Channel 10 Next + // Descripter Ptr Reg +#define DMA2_10_START_ADDR 0xFFC00E84 // DMA2 Channel 10 Start Address +#define DMA2_10_X_COUNT 0xFFC00E90 // DMA2 Channel 10 Inner Loop + // Count +#define DMA2_10_Y_COUNT 0xFFC00E98 // DMA2 Channel 10 Outer Loop + // Count +#define DMA2_10_X_MODIFY 0xFFC00E94 // DMA2 Channel 10 Inner Loop + // Addr Increment +#define DMA2_10_Y_MODIFY 0xFFC00E9C // DMA2 Channel 10 Outer Loop + // Addr Increment +#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 // DMA2 Channel 10 Current + // Descriptor Pointer +#define DMA2_10_CURR_ADDR 0xFFC00EA4 // DMA2 Channel 10 Current + // Address Pointer +#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 // DMA2 Channel 10 Current Inner + // Loop Count +#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 // DMA2 Channel 10 Current Outer + // Loop Count +#define DMA2_10_IRQ_STATUS 0xFFC00EA8 // DMA2 Channel 10 Interrupt + // /Status Register +#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC // DMA2 Channel 10 Peripheral + // Map Register + +#define DMA2_11_CONFIG 0xFFC00EC8 // DMA2 Channel 11 Configuration + // register +#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 // DMA2 Channel 11 Next + // Descripter Ptr Reg +#define DMA2_11_START_ADDR 0xFFC00EC4 // DMA2 Channel 11 Start Address +#define DMA2_11_X_COUNT 0xFFC00ED0 // DMA2 Channel 11 Inner Loop + // Count +#define DMA2_11_Y_COUNT 0xFFC00ED8 // DMA2 Channel 11 Outer Loop + // Count +#define DMA2_11_X_MODIFY 0xFFC00ED4 // DMA2 Channel 11 Inner Loop + // Addr Increment +#define DMA2_11_Y_MODIFY 0xFFC00EDC // DMA2 Channel 11 Outer Loop + // Addr Increment +#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 // DMA2 Channel 11 Current + // Descriptor Pointer +#define DMA2_11_CURR_ADDR 0xFFC00EE4 // DMA2 Channel 11 Current + // Address Pointer +#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 // DMA2 Channel 11 Current Inner + // Loop Count +#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 // DMA2 Channel 11 Current Outer + // Loop Count +#define DMA2_11_IRQ_STATUS 0xFFC00EE8 // DMA2 Channel 11 Interrupt + // /Status Register +#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC // DMA2 Channel 11 Peripheral + // Map Register + +// Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) +#define MDMA2_D0_CONFIG 0xFFC00F08 // MemDMA2 Stream 0 Destination + // Configuration register +#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 // MemDMA2 Stream 0 + // Destination Next + // Descriptor Ptr Reg +#define MDMA2_D0_START_ADDR 0xFFC00F04 // MemDMA2 Stream 0 Destination + // Start Address +#define MDMA2_D0_X_COUNT 0xFFC00F10 // MemDMA2 Stream 0 Dest + // Inner-Loop Count register +#define MDMA2_D0_Y_COUNT 0xFFC00F18 // MemDMA2 Stream 0 Dest + // Outer-Loop Count register +#define MDMA2_D0_X_MODIFY 0xFFC00F14 // MemDMA2 Stream 0 Dest + // Inner-Loop Address-Increment +#define MDMA2_D0_Y_MODIFY 0xFFC00F1C // MemDMA2 Stream 0 Dest + // Outer-Loop Address-Increment +#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 // MemDMA2 Stream 0 Dest + // Current Descriptor Ptr reg +#define MDMA2_D0_CURR_ADDR 0xFFC00F24 // MemDMA2 Stream 0 Destination + // Current Address +#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 // MemDMA2 Stream 0 Dest + // Current Inner-Loop Count reg +#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 // MemDMA2 Stream 0 Dest + // Current Outer-Loop Count reg +#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 // MemDMA2 Stream 0 Dest + // Interrupt/Status Register +#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C // MemDMA2 Stream 0 + // Destination Peripheral Map + // register + +#define MDMA2_S0_CONFIG 0xFFC00F48 // MemDMA2 Stream 0 Source + // Configuration register +#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 // MemDMA2 Stream 0 Source + // Next Descriptor Ptr Reg +#define MDMA2_S0_START_ADDR 0xFFC00F44 // MemDMA2 Stream 0 Source + // Start Address +#define MDMA2_S0_X_COUNT 0xFFC00F50 // MemDMA2 Stream 0 Source + // Inner-Loop Count register +#define MDMA2_S0_Y_COUNT 0xFFC00F58 // MemDMA2 Stream 0 Source + // Outer-Loop Count register +#define MDMA2_S0_X_MODIFY 0xFFC00F54 // MemDMA2 Stream 0 Src + // Inner-Loop Addr-Increment reg +#define MDMA2_S0_Y_MODIFY 0xFFC00F5C // MemDMA2 Stream 0 Src + // Outer-Loop Addr-Increment reg +#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 // MemDMA2 Stream 0 Source + // Current Descriptor Ptr reg +#define MDMA2_S0_CURR_ADDR 0xFFC00F64 // MemDMA2 Stream 0 Source + // Current Address +#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 // MemDMA2 Stream 0 Src + // Current Inner-Loop Count reg +#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 // MemDMA2 Stream 0 Src + // Current Outer-Loop Count reg +#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 // MemDMA2 Stream 0 Source + // Interrupt/Status Register +#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C // MemDMA2 Stream 0 Source + // Peripheral Map register + +#define MDMA2_D1_CONFIG 0xFFC00F88 // MemDMA2 Stream 1 Destination + // Configuration register +#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 // MemDMA2 Stream 1 + // Destination Next + // Descriptor Ptr Reg +#define MDMA2_D1_START_ADDR 0xFFC00F84 // MemDMA2 Stream 1 Destination + // Start Address +#define MDMA2_D1_X_COUNT 0xFFC00F90 // MemDMA2 Stream 1 Dest + // Inner-Loop Count register +#define MDMA2_D1_Y_COUNT 0xFFC00F98 // MemDMA2 Stream 1 Dest + // Outer-Loop Count register +#define MDMA2_D1_X_MODIFY 0xFFC00F94 // MemDMA2 Stream 1 Dest + // Inner-Loop Address-Increment +#define MDMA2_D1_Y_MODIFY 0xFFC00F9C // MemDMA2 Stream 1 Dest + // Outer-Loop Address-Increment +#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 // MemDMA2 Stream 1 + // Destination Current + // Descriptor Ptr +#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 // MemDMA2 Stream 1 Destination + // Current Address reg +#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 // MemDMA2 Stream 1 Dest + // Current Inner-Loop Count reg +#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 // MemDMA2 Stream 1 Dest + // Current Outer-Loop Count reg +#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 // MemDMA2 Stream 1 Destination + // Interrupt/Status Reg +#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC // MemDMA2 Stream 1 + // Destination Peripheral Map + // register + +#define MDMA2_S1_CONFIG 0xFFC00FC8 // MemDMA2 Stream 1 Source + // Configuration register +#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 // MemDMA2 Stream 1 Source + // Next Descriptor Ptr Reg +#define MDMA2_S1_START_ADDR 0xFFC00FC4 // MemDMA2 Stream 1 Source + // Start Address +#define MDMA2_S1_X_COUNT 0xFFC00FD0 // MemDMA2 Stream 1 Source + // Inner-Loop Count register +#define MDMA2_S1_Y_COUNT 0xFFC00FD8 // MemDMA2 Stream 1 Source + // Outer-Loop Count register +#define MDMA2_S1_X_MODIFY 0xFFC00FD4 // MemDMA2 Stream 1 Src + // Inner-Loop Address-Increment +#define MDMA2_S1_Y_MODIFY 0xFFC00FDC // MemDMA2 Stream 1 Source + // Outer-Loop Address-Increment +#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 // MemDMA2 Stream 1 Source + // Current Descriptor Ptr reg +#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 // MemDMA2 Stream 1 Source + // Current Address +#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 // MemDMA2 Stream 1 Source + // Current Inner-Loop Count +#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 // MemDMA2 Stream 1 Source + // Current Outer-Loop Count +#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 // MemDMA2 Stream 1 Source + // Interrupt/Status Register +#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC // MemDMA2 Stream 1 Source + // Peripheral Map register + +// Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) +#define IMDMA_D0_CONFIG 0xFFC01808 // IMDMA Stream 0 Destination + // Configuration +#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 // IMDMA Stream 0 Destination + // Next Descriptor Ptr Reg +#define IMDMA_D0_START_ADDR 0xFFC01804 // IMDMA Stream 0 Destination + // Start Address +#define IMDMA_D0_X_COUNT 0xFFC01810 // IMDMA Stream 0 Destination + // Inner-Loop Count +#define IMDMA_D0_Y_COUNT 0xFFC01818 // IMDMA Stream 0 Destination + // Outer-Loop Count +#define IMDMA_D0_X_MODIFY 0xFFC01814 // IMDMA Stream 0 Dest + // Inner-Loop Address-Increment +#define IMDMA_D0_Y_MODIFY 0xFFC0181C // IMDMA Stream 0 Dest + // Outer-Loop Address-Increment +#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 // IMDMA Stream 0 Destination + // Current Descriptor Ptr +#define IMDMA_D0_CURR_ADDR 0xFFC01824 // IMDMA Stream 0 Destination + // Current Address +#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 // IMDMA Stream 0 Destination + // Current Inner-Loop Count +#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 // IMDMA Stream 0 Destination + // Current Outer-Loop Count +#define IMDMA_D0_IRQ_STATUS 0xFFC01828 // IMDMA Stream 0 Destination + // Interrupt/Status + +#define IMDMA_S0_CONFIG 0xFFC01848 // IMDMA Stream 0 Source + // Configuration +#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 // IMDMA Stream 0 Source Next + // Descriptor Ptr Reg +#define IMDMA_S0_START_ADDR 0xFFC01844 // IMDMA Stream 0 Source Start + // Address +#define IMDMA_S0_X_COUNT 0xFFC01850 // IMDMA Stream 0 Source + // Inner-Loop Count +#define IMDMA_S0_Y_COUNT 0xFFC01858 // IMDMA Stream 0 Source + // Outer-Loop Count +#define IMDMA_S0_X_MODIFY 0xFFC01854 // IMDMA Stream 0 Source + // Inner-Loop Address-Increment +#define IMDMA_S0_Y_MODIFY 0xFFC0185C // IMDMA Stream 0 Source + // Outer-Loop Address-Increment +#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 // IMDMA Stream 0 Source + // Current Descriptor Ptr reg +#define IMDMA_S0_CURR_ADDR 0xFFC01864 // IMDMA Stream 0 Source Current + // Address +#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 // IMDMA Stream 0 Source + // Current Inner-Loop Count +#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 // IMDMA Stream 0 Source + // Current Outer-Loop Count +#define IMDMA_S0_IRQ_STATUS 0xFFC01868 // IMDMA Stream 0 Source + // Interrupt/Status + +#define IMDMA_D1_CONFIG 0xFFC01888 // IMDMA Stream 1 Destination + // Configuration +#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 // IMDMA Stream 1 Destination + // Next Descriptor Ptr Reg +#define IMDMA_D1_START_ADDR 0xFFC01884 // IMDMA Stream 1 Destination + // Start Address +#define IMDMA_D1_X_COUNT 0xFFC01890 // IMDMA Stream 1 Destination + // Inner-Loop Count +#define IMDMA_D1_Y_COUNT 0xFFC01898 // IMDMA Stream 1 Destination + // Outer-Loop Count +#define IMDMA_D1_X_MODIFY 0xFFC01894 // IMDMA Stream 1 Dest + // Inner-Loop Address-Increment +#define IMDMA_D1_Y_MODIFY 0xFFC0189C // IMDMA Stream 1 Dest + // Outer-Loop Address-Increment +#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 // IMDMA Stream 1 Destination + // Current Descriptor Ptr +#define IMDMA_D1_CURR_ADDR 0xFFC018A4 // IMDMA Stream 1 Destination + // Current Address +#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 // IMDMA Stream 1 Destination + // Current Inner-Loop Count +#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 // IMDMA Stream 1 Destination + // Current Outer-Loop Count +#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 // IMDMA Stream 1 Destination + // Interrupt/Status + +#define IMDMA_S1_CONFIG 0xFFC018C8 // IMDMA Stream 1 Source + // Configuration +#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 // IMDMA Stream 1 Source Next + // Descriptor Ptr Reg +#define IMDMA_S1_START_ADDR 0xFFC018C4 // IMDMA Stream 1 Source Start + // Address +#define IMDMA_S1_X_COUNT 0xFFC018D0 // IMDMA Stream 1 Source + // Inner-Loop Count +#define IMDMA_S1_Y_COUNT 0xFFC018D8 // IMDMA Stream 1 Source + // Outer-Loop Count +#define IMDMA_S1_X_MODIFY 0xFFC018D4 // IMDMA Stream 1 Source + // Inner-Loop Address-Increment +#define IMDMA_S1_Y_MODIFY 0xFFC018DC // IMDMA Stream 1 Source + // Outer-Loop Address-Increment +#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 // IMDMA Stream 1 Source + // Current Descriptor Ptr reg +#define IMDMA_S1_CURR_ADDR 0xFFC018E4 // IMDMA Stream 1 Source Current + // Address +#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 // IMDMA Stream 1 Source + // Current Inner-Loop Count +#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 // IMDMA Stream 1 Source + // Current Outer-Loop Count +#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 // IMDMA Stream 1 Source + // Interrupt/Status + +//**************************************************************************** +// System MMR Register Bits +//**************************************************************************** + +// ********************* PLL AND RESET MASKS ************************ + +//// PLL_CTL Masks +#define PLL_CLKIN 0x00000000 // Pass CLKIN to PLL +#define PLL_CLKIN_DIV2 0x00000001 // Pass CLKIN/2 to PLL +#define PLL_OFF 0x00000002 // Shut off PLL clocks +#define STOPCK_OFF 0x00000008 // Core clock off +#define PDWN 0x00000020 // Put the PLL in a Deep + // Sleep state +#define BYPASS 0x00000100 // Bypass the PLL + +//// PLL_DIV Masks + +#define SCLK_DIV(x) (x) // SCLK = VCO / x + +#define CCLK_DIV1 0x00000000 // CCLK = VCO / 1 +#define CCLK_DIV2 0x00000010 // CCLK = VCO / 2 +#define CCLK_DIV4 0x00000020 // CCLK = VCO / 4 +#define CCLK_DIV8 0x00000030 // CCLK = VCO / 8 + +// SWRST Mask +#define SYSTEM_RESET 0x00000007 // Initiates a system + // software reset +#define SWRST_DBL_FAULT_B 0x00000800 // SWRST Core B Double Fault +#define SWRST_DBL_FAULT_A 0x00001000 // SWRST Core A Double Fault +#define SWRST_WDT_B 0x00002000 // SWRST Watchdog B +#define SWRST_WDT_A 0x00004000 // SWRST Watchdog A +#define SWRST_OCCURRED 0x00008000 // SWRST Status + +// ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** + +// SICu_IARv Masks +// u = A or B +// v = 0 to 7 +// w = 0 or 1 + +// Per_number = 0 to 63 +// IVG_number = 7 to 15 +// Peripheral #Per_number assigned IVG #IVG_number +// Usage: +// r0.l = lo(Peripheral_IVG(62, 10)); +// r0.h = hi(Peripheral_IVG(62, 10)); +#define Peripheral_IVG(Per_number, IVG_number) \ + ( (IVG_number) -7) << ( ((Per_number)%8) *4) + +// SICx_IMASKw Masks +// masks are 32 bit wide, so two writes reguired for "64 bit" wide registers +#define SIC_UNMASK_ALL 0x00000000 // Unmask all peripheral + // interrupts +#define SIC_MASK_ALL 0xFFFFFFFF // Mask all peripheral + // interrupts +#define SIC_MASK(x) (1 << (x)) // Mask Peripheral #x + // interrupt +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) // Unmask Peripheral #x + // interrupt + +// SIC_IWR Masks +#define IWR_DISABLE_ALL 0x00000000 // Wakeup Disable all + // peripherals +#define IWR_ENABLE_ALL 0xFFFFFFFF // Wakeup Enable all + // peripherals +// x = pos 0 to 31, for 32-63 use value-32 +#define IWR_ENABLE(x) (1 << (x)) // Wakeup Enable Peripheral + // #x +// Wakeup Disable Peripheral #x +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) + +// ********* WATCHDOG TIMER MASKS ********************8 + +// Watchdog Timer WDOG_CTL Register +#define WDOGA_CTL 0xFFC00200 +#define WDOGA_CNT 0xFFC00204 +#define WDOGA_STAT 0xFFC00208 +#define WDOGB_CTL 0xFFC01200 +#define WDOGB_CNT 0xFFC01204 +#define WDOGB_STAT 0xFFC01208 +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 // Set Watchdog Timer to + // generate reset +#define ENABLE_NMI 0x00000002 // Set Watchdog Timer to + // generate non-maskable + // interrupt +#define ENABLE_GPI 0x00000004 // Set Watchdog Timer to + // generate general-purpose + // interrupt +#define DISABLE_EVT 0x00000006 // Disable Watchdog Timer + // interrupts + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +// ***************************** UART CONTROLLER MASKS ********************** + +// UART_LCR Register + +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +// UART_MCR Register +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +// UART_LSR Register +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +// UART_IER Register +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +// UART_IIR Register +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +// UART_GCTL Register +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +// ********** SERIAL PORT MASKS ********************** + +// SPORTx_TCR1 Masks +#define TSPEN 0x0001 // TX enable +#define ITCLK 0x0002 // Internal TX Clock Select +#define TDTYPE 0x000C // TX Data Formatting Select +#define TLSBIT 0x0010 // TX Bit Order +#define ITFS 0x0200 // Internal TX Frame Sync Select +#define TFSR 0x0400 // TX Frame Sync Required Select +#define DITFS 0x0800 // Data Independent TX Frame Sync Select +#define LTFS 0x1000 // Low TX Frame Sync Select +#define LATFS 0x2000 // Late TX Frame Sync Select +#define TCKFE 0x4000 // TX Clock Falling Edge Select + +// SPORTx_TCR2 Masks +#define SLEN 0x001F // TX Word Length +#define TXSE 0x0100 // TX Secondary Enable +#define TSFSE 0x0200 // TX Stereo Frame Sync Enable +#define TRFST 0x0400 // TX Right-First Data Order + +// SPORTx_RCR1 Masks +#define RSPEN 0x0001 // RX enable +#define IRCLK 0x0002 // Internal RX Clock Select +#define RDTYPE 0x000C // RX Data Formatting Select +#define RULAW 0x0008 // u-Law enable +#define RALAW 0x000C // A-Law enable +#define RLSBIT 0x0010 // RX Bit Order +#define IRFS 0x0200 // Internal RX Frame Sync Select +#define RFSR 0x0400 // RX Frame Sync Required Select +#define LRFS 0x1000 // Low RX Frame Sync Select +#define LARFS 0x2000 // Late RX Frame Sync Select +#define RCKFE 0x4000 // RX Clock Falling Edge Select + +// SPORTx_RCR2 Masks +#define SLEN 0x001F // RX Word Length +#define RXSE 0x0100 // RX Secondary Enable +#define RSFSE 0x0200 // RX Stereo Frame Sync Enable +#define RRFST 0x0400 // Right-First Data Order + +//SPORTx_STAT Masks +#define RXNE 0x0001 // RX FIFO Not Empty Status +#define RUVF 0x0002 // RX Underflow Status +#define ROVF 0x0004 // RX Overflow Status +#define TXF 0x0008 // TX FIFO Full Status +#define TUVF 0x0010 // TX Underflow Status +#define TOVF 0x0020 // TX Overflow Status +#define TXHRE 0x0040 // TX Hold Register Empty + +//SPORTx_MCMC1 Masks +#define WSIZE 0x0000F000 // Multichannel Window Size Field +#define WOFF 0x000003FF // Multichannel Window Offset Field + +//SPORTx_MCMC2 Masks +#define MCCRM 0x00000003 // Multichannel Clock Recovery Mode +#define MCDTXPE 0x00000004 // Multichannel DMA Transmit Packing +#define MCDRXPE 0x00000008 // Multichannel DMA Receive Packing +#define MCMEN 0x00000010 // Multichannel Frame Mode Enable +#define FSDR 0x00000080 // Multichannel Frame Sync to Data + // Relationship +#define MFD 0x0000F000 // Multichannel Frame Delay + +// ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** + +//// PPI_CONTROL Masks +#define PORT_EN 0x00000001 // PPI Port Enable +#define PORT_DIR 0x00000002 // PPI Port Direction +#define XFR_TYPE 0x0000000C // PPI Transfer Type +#define PORT_CFG 0x00000030 // PPI Port Configuration +#define FLD_SEL 0x00000040 // PPI Active Field Select +#define PACK_EN 0x00000080 // PPI Packing Mode +#define DMA32 0x00000100 // PPI 32-bit DMA Enable +#define SKIP_EN 0x00000200 // PPI Skip Element Enable +#define SKIP_EO 0x00000400 // PPI Skip Even/Odd Elements +#define DLENGTH 0x00003800 // PPI Data Length +#define DLEN_8 0x0 // PPI Data Length mask for DLEN=8 +#define DLEN(x) (((x-9) & 0x07) << 11) // PPI Data Length (only works for + // x=10-->x=16) +#define POL 0x0000C000 // PPI Signal Polarities + +//// PPI_STATUS Masks +#define FLD 0x00000400 // Field Indicator +#define FT_ERR 0x00000800 // Frame Track Error +#define OVR 0x00001000 // FIFO Overflow Error +#define UNDR 0x00002000 // FIFO Underrun Error +#define ERR_DET 0x00004000 // Error Detected Indicator +#define ERR_NCOR 0x00008000 // Error Not Corrected Indicator + +// ********** DMA CONTROLLER MASKS *********************8 + +// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks +#define DMAEN 0x00000001 // Channel Enable +#define WNR 0x00000002 // Channel Direction (W/R*) +#define WDSIZE_8 0x00000000 // Word Size 8 bits +#define WDSIZE_16 0x00000004 // Word Size 16 bits +#define WDSIZE_32 0x00000008 // Word Size 32 bits +#define DMA2D 0x00000010 // 2D/1D* Mode +#define RESTART 0x00000020 // Restart +#define DI_SEL 0x00000040 // Data Interrupt Select +#define DI_EN 0x00000080 // Data Interrupt Enable +#define NDSIZE 0x00000900 // Next Descriptor Size +#define FLOW 0x00007000 // Flow Control + +#define DMAEN_P 0 // Channel Enable +#define WNR_P 1 // Channel Direction (W/R*) +#define DMA2D_P 4 // 2D/1D* Mode +#define RESTART_P 5 // Restart +#define DI_SEL_P 6 // Data Interrupt Select +#define DI_EN_P 7 // Data Interrupt Enable + +////DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks + +#define DMA_DONE 0x00000001 // DMA Done Indicator +#define DMA_ERR 0x00000002 // DMA Error Indicator +#define DFETCH 0x00000004 // Descriptor Fetch Indicator +#define DMA_RUN 0x00000008 // DMA Running Indicator + +#define DMA_DONE_P 0 // DMA Done Indicator +#define DMA_ERR_P 1 // DMA Error Indicator +#define DFETCH_P 2 // Descriptor Fetch Indicator +#define DMA_RUN_P 3 // DMA Running Indicator + +////DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks + +#define CTYPE 0x00000040 // DMA Channel Type Indicator +#define CTYPE_P 6 // DMA Channel Type Indicator BIT POSITION +#define PCAP8 0x00000080 // DMA 8-bit Operation Indicator +#define PCAP16 0x00000100 // DMA 16-bit Operation Indicator +#define PCAP32 0x00000200 // DMA 32-bit Operation Indicator +#define PCAPWR 0x00000400 // DMA Write Operation Indicator +#define PCAPRD 0x00000800 // DMA Read Operation Indicator +#define PMAP 0x00007000 // DMA Peripheral Map Field + +// ************* GENERAL PURPOSE TIMER MASKS ******************** + +/* PWM Timer bit definitions */ + +// TIMER_ENABLE Register +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 +#define TIMEN3 0x0008 +#define TIMEN4 0x0010 +#define TIMEN5 0x0020 +#define TIMEN6 0x0040 +#define TIMEN7 0x0080 +#define TIMEN8 0x0001 +#define TIMEN9 0x0002 +#define TIMEN10 0x0004 +#define TIMEN11 0x0008 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 +#define TIMEN3_P 0x03 +#define TIMEN4_P 0x04 +#define TIMEN5_P 0x05 +#define TIMEN6_P 0x06 +#define TIMEN7_P 0x07 +#define TIMEN8_P 0x00 +#define TIMEN9_P 0x01 +#define TIMEN10_P 0x02 +#define TIMEN11_P 0x03 + +// TIMER_DISABLE Register +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 +#define TIMDIS3 0x0008 +#define TIMDIS4 0x0010 +#define TIMDIS5 0x0020 +#define TIMDIS6 0x0040 +#define TIMDIS7 0x0080 +#define TIMDIS8 0x0001 +#define TIMDIS9 0x0002 +#define TIMDIS10 0x0004 +#define TIMDIS11 0x0008 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 +#define TIMDIS3_P 0x03 +#define TIMDIS4_P 0x04 +#define TIMDIS5_P 0x05 +#define TIMDIS6_P 0x06 +#define TIMDIS7_P 0x07 +#define TIMDIS8_P 0x00 +#define TIMDIS9_P 0x01 +#define TIMDIS10_P 0x02 +#define TIMDIS11_P 0x03 + +// TIMER_STATUS Register +#define TIMIL0 0x00000001 +#define TIMIL1 0x00000002 +#define TIMIL2 0x00000004 +#define TIMIL3 0x00000008 +#define TIMIL4 0x00010000 +#define TIMIL5 0x00020000 +#define TIMIL6 0x00040000 +#define TIMIL7 0x00080000 +#define TIMIL8 0x0001 +#define TIMIL9 0x0002 +#define TIMIL10 0x0004 +#define TIMIL11 0x0008 +#define TOVL_ERR0 0x00000010 +#define TOVL_ERR1 0x00000020 +#define TOVL_ERR2 0x00000040 +#define TOVL_ERR3 0x00000080 +#define TOVL_ERR4 0x00100000 +#define TOVL_ERR5 0x00200000 +#define TOVL_ERR6 0x00400000 +#define TOVL_ERR7 0x00800000 +#define TOVL_ERR8 0x0010 +#define TOVL_ERR9 0x0020 +#define TOVL_ERR10 0x0040 +#define TOVL_ERR11 0x0080 +#define TRUN0 0x00001000 +#define TRUN1 0x00002000 +#define TRUN2 0x00004000 +#define TRUN3 0x00008000 +#define TRUN4 0x10000000 +#define TRUN5 0x20000000 +#define TRUN6 0x40000000 +#define TRUN7 0x80000000 +#define TRUN8 0x1000 +#define TRUN9 0x2000 +#define TRUN10 0x4000 +#define TRUN11 0x8000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TIMIL3_P 0x03 +#define TIMIL4_P 0x10 +#define TIMIL5_P 0x11 +#define TIMIL6_P 0x12 +#define TIMIL7_P 0x13 +#define TIMIL8_P 0x00 +#define TIMIL9_P 0x01 +#define TIMIL10_P 0x02 +#define TIMIL11_P 0x03 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TOVL_ERR3_P 0x07 +#define TOVL_ERR4_P 0x14 +#define TOVL_ERR5_P 0x15 +#define TOVL_ERR6_P 0x16 +#define TOVL_ERR7_P 0x17 +#define TOVL_ERR8_P 0x04 +#define TOVL_ERR9_P 0x05 +#define TOVL_ERR10_P 0x06 +#define TOVL_ERR11_P 0x07 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E +#define TRUN3_P 0x0F +#define TRUN4_P 0x1C +#define TRUN5_P 0x1D +#define TRUN6_P 0x1E +#define TRUN7_P 0x1F +#define TRUN8_P 0x0C +#define TRUN9_P 0x0D +#define TRUN10_P 0x0E +#define TRUN11_P 0x0F + +// TIMERx_CONFIG Registers +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/// ****************** PROGRAMMABLE FLAG MASKS ********************* + +// General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +// General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +// *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** + +//// SPI_CTL Masks +#define TIMOD 0x00000003 // Transfer initiation mode + // and interrupt generation +#define SZ 0x00000004 // Send Zero (=0) or last + // (=1) word when TDBR empty. +#define GM 0x00000008 // When RDBR full, get more + // (=1) data or discard (=0) + // incoming Data +#define PSSE 0x00000010 // Enable (=1) Slave-Select + // input for Master. +#define EMISO 0x00000020 // Enable (=1) MISO pin as an + // output. +#define SIZE 0x00000100 // Word length (0 => 8 bits, + // 1 => 16 bits) +#define LSBF 0x00000200 // Data format (0 => MSB + // sent/received first 1 => + // LSB sent/received first) +#define CPHA 0x00000400 // Clock phase (0 => SPICLK + // starts toggling in middle + // of xfer, 1 => SPICLK + // toggles at the beginning + // of xfer. +#define CPOL 0x00000800 // Clock polarity (0 => + // active-high, 1 => + // active-low) +#define MSTR 0x00001000 // Configures SPI as master + // (=1) or slave (=0) +#define WOM 0x00002000 // Open drain (=1) data + // output enable (for MOSI + // and MISO) +#define SPE 0x00004000 // SPI module enable (=1), + // disable (=0) + +//// SPI_FLG Masks +#define FLS1 0x00000002 // Enables (=1) SPI_FLOUT1 as + // flag output for SPI + // Slave-select +#define FLS2 0x00000004 // Enables (=1) SPI_FLOUT2 as + // flag output for SPI + // Slave-select +#define FLS3 0x00000008 // Enables (=1) SPI_FLOUT3 as + // flag output for SPI + // Slave-select +#define FLS4 0x00000010 // Enables (=1) SPI_FLOUT4 as + // flag output for SPI + // Slave-select +#define FLS5 0x00000020 // Enables (=1) SPI_FLOUT5 as + // flag output for SPI + // Slave-select +#define FLS6 0x00000040 // Enables (=1) SPI_FLOUT6 as + // flag output for SPI + // Slave-select +#define FLS7 0x00000080 // Enables (=1) SPI_FLOUT7 as + // flag output for SPI + // Slave-select +#define FLG1 0x00000200 // Activates (=0) SPI_FLOUT1 + // as flag output for SPI + // Slave-select +#define FLG2 0x00000400 // Activates (=0) SPI_FLOUT2 + // as flag output for SPI + // Slave-select +#define FLG3 0x00000800 // Activates (=0) SPI_FLOUT3 + // as flag output for SPI + // Slave-select +#define FLG4 0x00001000 // Activates (=0) SPI_FLOUT4 + // as flag output for SPI + // Slave-select +#define FLG5 0x00002000 // Activates (=0) SPI_FLOUT5 + // as flag output for SPI + // Slave-select +#define FLG6 0x00004000 // Activates (=0) SPI_FLOUT6 + // as flag output for SPI + // Slave-select +#define FLG7 0x00008000 // Activates (=0) SPI_FLOUT7 + // as flag output for SPI + // Slave-select + +//// SPI_FLG Bit Positions +#define FLS1_P 0x00000001 // Enables (=1) SPI_FLOUT1 as + // flag output for SPI + // Slave-select +#define FLS2_P 0x00000002 // Enables (=1) SPI_FLOUT2 as + // flag output for SPI + // Slave-select +#define FLS3_P 0x00000003 // Enables (=1) SPI_FLOUT3 as + // flag output for SPI + // Slave-select +#define FLS4_P 0x00000004 // Enables (=1) SPI_FLOUT4 as + // flag output for SPI + // Slave-select +#define FLS5_P 0x00000005 // Enables (=1) SPI_FLOUT5 as + // flag output for SPI + // Slave-select +#define FLS6_P 0x00000006 // Enables (=1) SPI_FLOUT6 as + // flag output for SPI + // Slave-select +#define FLS7_P 0x00000007 // Enables (=1) SPI_FLOUT7 as + // flag output for SPI + // Slave-select +#define FLG1_P 0x00000009 // Activates (=0) SPI_FLOUT1 + // as flag output for SPI + // Slave-select +#define FLG2_P 0x0000000A // Activates (=0) SPI_FLOUT2 + // as flag output for SPI + // Slave-select +#define FLG3_P 0x0000000B // Activates (=0) SPI_FLOUT3 + // as flag output for SPI + // Slave-select +#define FLG4_P 0x0000000C // Activates (=0) SPI_FLOUT4 + // as flag output for SPI + // Slave-select +#define FLG5_P 0x0000000D // Activates (=0) SPI_FLOUT5 + // as flag output for SPI + // Slave-select +#define FLG6_P 0x0000000E // Activates (=0) SPI_FLOUT6 + // as flag output for SPI + // Slave-select +#define FLG7_P 0x0000000F // Activates (=0) SPI_FLOUT7 + // as flag output for SPI + // Slave-select + +//// SPI_STAT Masks +#define SPIF 0x00000001 // Set (=1) when SPI + // single-word transfer + // complete +#define MODF 0x00000002 // Set (=1) in a master + // device when some other + // device tries to become + // master +#define TXE 0x00000004 // Set (=1) when transmission + // occurs with no new data in + // SPI_TDBR +#define TXS 0x00000008 // SPI_TDBR Data Buffer + // Status (0=Empty, 1=Full) +#define RBSY 0x00000010 // Set (=1) when data is + // received with RDBR full +#define RXS 0x00000020 // SPI_RDBR Data Buffer + // Status (0=Empty, 1=Full) +#define TXCOL 0x00000040 // When set (=1), corrupt + // data may have been + // transmitted + +// ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* + +// AMGCTL Masks +#define AMCKEN 0x0001 // Enable CLKOUT +#define AMBEN_B0 0x0002 // Enable Asynchronous Memory Bank 0 + // only +#define AMBEN_B0_B1 0x0004 // Enable Asynchronous Memory Banks 0 + // & 1 only +#define AMBEN_B0_B1_B2 0x0006 // Enable Asynchronous Memory Banks 0, + // 1, and 2 +#define AMBEN_ALL 0x0008 // Enable Asynchronous Memory Banks + // (all) 0, 1, 2, and 3 +#define B0_PEN 0x0010 // Enable 16-bit packing Bank 0 +#define B1_PEN 0x0020 // Enable 16-bit packing Bank 1 +#define B2_PEN 0x0040 // Enable 16-bit packing Bank 2 +#define B3_PEN 0x0080 // Enable 16-bit packing Bank 3 + +// AMGCTL Bit Positions +#define AMCKEN_P 0x00000000 // Enable CLKOUT +#define AMBEN_P0 0x00000001 // Asynchronous Memory + // Enable, 000 - banks 0-3 + // disabled, 001 - Bank 0 + // enabled +#define AMBEN_P1 0x00000002 // Asynchronous Memory + // Enable, 010 - banks 0&1 + // enabled, 011 - banks 0-3 + // enabled +#define AMBEN_P2 0x00000003 // Asynchronous Memory + // Enable, 1xx - All banks + // (bank 0, 1, 2, and 3) + // enabled +#define B0_PEN_P 0x004 // Enable 16-bit packing Bank 0 +#define B1_PEN_P 0x005 // Enable 16-bit packing Bank 1 +#define B2_PEN_P 0x006 // Enable 16-bit packing Bank 2 +#define B3_PEN_P 0x007 // Enable 16-bit packing Bank 3 + +// AMBCTL0 Masks +#define B0RDYEN 0x00000001 // Bank 0 RDY Enable, + // 0=disable, 1=enable +#define B0RDYPOL 0x00000002 // Bank 0 RDY Active high, + // 0=active low, 1=active high +#define B0TT_1 0x00000004 // Bank 0 Transition Time from + // Read to Write = 1 cycle +#define B0TT_2 0x00000008 // Bank 0 Transition Time from + // Read to Write = 2 cycles +#define B0TT_3 0x0000000C // Bank 0 Transition Time from + // Read to Write = 3 cycles +#define B0TT_4 0x00000000 // Bank 0 Transition Time from + // Read to Write = 4 cycles +#define B0ST_1 0x00000010 // Bank 0 Setup Time from AOE + // asserted to Read/Write + // asserted=1 cycle +#define B0ST_2 0x00000020 // Bank 0 Setup Time from AOE + // asserted to Read/Write + // asserted=2 cycles +#define B0ST_3 0x00000030 // Bank 0 Setup Time from AOE + // asserted to Read/Write + // asserted=3 cycles +#define B0ST_4 0x00000000 // Bank 0 Setup Time from AOE + // asserted to Read/Write + // asserted=4 cycles +#define B0HT_1 0x00000040 // Bank 0 Hold Time from + // Read/Write deasserted to AOE + // deasserted = 1 cycle +#define B0HT_2 0x00000080 // Bank 0 Hold Time from + // Read/Write deasserted to AOE + // deasserted = 2 cycles +#define B0HT_3 0x000000C0 // Bank 0 Hold Time from + // Read/Write deasserted to AOE + // deasserted = 3 cycles +#define B0HT_0 0x00000000 // Bank 0 Hold Time from + // Read/Write deasserted to AOE + // deasserted = 0 cycles +#define B0RAT_1 0x00000100 // Bank 0 Read Access Time = + // 1 cycle +#define B0RAT_2 0x00000200 // Bank 0 Read Access Time = + // 2 cycles +#define B0RAT_3 0x00000300 // Bank 0 Read Access Time = + // 3 cycles +#define B0RAT_4 0x00000400 // Bank 0 Read Access Time = + // 4 cycles +#define B0RAT_5 0x00000500 // Bank 0 Read Access Time = + // 5 cycles +#define B0RAT_6 0x00000600 // Bank 0 Read Access Time = + // 6 cycles +#define B0RAT_7 0x00000700 // Bank 0 Read Access Time = + // 7 cycles +#define B0RAT_8 0x00000800 // Bank 0 Read Access Time = + // 8 cycles +#define B0RAT_9 0x00000900 // Bank 0 Read Access Time = + // 9 cycles +#define B0RAT_10 0x00000A00 // Bank 0 Read Access Time = + // 10 cycles +#define B0RAT_11 0x00000B00 // Bank 0 Read Access Time = + // 11 cycles +#define B0RAT_12 0x00000C00 // Bank 0 Read Access Time = + // 12 cycles +#define B0RAT_13 0x00000D00 // Bank 0 Read Access Time = + // 13 cycles +#define B0RAT_14 0x00000E00 // Bank 0 Read Access Time = + // 14 cycles +#define B0RAT_15 0x00000F00 // Bank 0 Read Access Time = + // 15 cycles +#define B0WAT_1 0x00001000 // Bank 0 Write Access Time = + // 1 cycle +#define B0WAT_2 0x00002000 // Bank 0 Write Access Time = + // 2 cycles +#define B0WAT_3 0x00003000 // Bank 0 Write Access Time = + // 3 cycles +#define B0WAT_4 0x00004000 // Bank 0 Write Access Time = + // 4 cycles +#define B0WAT_5 0x00005000 // Bank 0 Write Access Time = + // 5 cycles +#define B0WAT_6 0x00006000 // Bank 0 Write Access Time = + // 6 cycles +#define B0WAT_7 0x00007000 // Bank 0 Write Access Time = + // 7 cycles +#define B0WAT_8 0x00008000 // Bank 0 Write Access Time = + // 8 cycles +#define B0WAT_9 0x00009000 // Bank 0 Write Access Time = + // 9 cycles +#define B0WAT_10 0x0000A000 // Bank 0 Write Access Time = + // 10 cycles +#define B0WAT_11 0x0000B000 // Bank 0 Write Access Time = + // 11 cycles +#define B0WAT_12 0x0000C000 // Bank 0 Write Access Time = + // 12 cycles +#define B0WAT_13 0x0000D000 // Bank 0 Write Access Time = + // 13 cycles +#define B0WAT_14 0x0000E000 // Bank 0 Write Access Time = + // 14 cycles +#define B0WAT_15 0x0000F000 // Bank 0 Write Access Time = + // 15 cycles +#define B1RDYEN 0x00010000 // Bank 1 RDY enable, + // 0=disable, 1=enable +#define B1RDYPOL 0x00020000 // Bank 1 RDY Active high, + // 0=active low, 1=active + // high +#define B1TT_1 0x00040000 // Bank 1 Transition Time + // from Read to Write = 1 + // cycle +#define B1TT_2 0x00080000 // Bank 1 Transition Time + // from Read to Write = 2 + // cycles +#define B1TT_3 0x000C0000 // Bank 1 Transition Time + // from Read to Write = 3 + // cycles +#define B1TT_4 0x00000000 // Bank 1 Transition Time + // from Read to Write = 4 + // cycles +#define B1ST_1 0x00100000 // Bank 1 Setup Time from AOE + // asserted to Read or Write + // asserted = 1 cycle +#define B1ST_2 0x00200000 // Bank 1 Setup Time from AOE + // asserted to Read or Write + // asserted = 2 cycles +#define B1ST_3 0x00300000 // Bank 1 Setup Time from AOE + // asserted to Read or Write + // asserted = 3 cycles +#define B1ST_4 0x00000000 // Bank 1 Setup Time from AOE + // asserted to Read or Write + // asserted = 4 cycles +#define B1HT_1 0x00400000 // Bank 1 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 1 cycle +#define B1HT_2 0x00800000 // Bank 1 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 2 cycles +#define B1HT_3 0x00C00000 // Bank 1 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 3 cycles +#define B1HT_0 0x00000000 // Bank 1 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 0 cycles +#define B1RAT_1 0x01000000 // Bank 1 Read Access Time = + // 1 cycle +#define B1RAT_2 0x02000000 // Bank 1 Read Access Time = + // 2 cycles +#define B1RAT_3 0x03000000 // Bank 1 Read Access Time = + // 3 cycles +#define B1RAT_4 0x04000000 // Bank 1 Read Access Time = + // 4 cycles +#define B1RAT_5 0x05000000 // Bank 1 Read Access Time = + // 5 cycles +#define B1RAT_6 0x06000000 // Bank 1 Read Access Time = + // 6 cycles +#define B1RAT_7 0x07000000 // Bank 1 Read Access Time = + // 7 cycles +#define B1RAT_8 0x08000000 // Bank 1 Read Access Time = + // 8 cycles +#define B1RAT_9 0x09000000 // Bank 1 Read Access Time = + // 9 cycles +#define B1RAT_10 0x0A000000 // Bank 1 Read Access Time = + // 10 cycles +#define B1RAT_11 0x0B000000 // Bank 1 Read Access Time = + // 11 cycles +#define B1RAT_12 0x0C000000 // Bank 1 Read Access Time = + // 12 cycles +#define B1RAT_13 0x0D000000 // Bank 1 Read Access Time = + // 13 cycles +#define B1RAT_14 0x0E000000 // Bank 1 Read Access Time = + // 14 cycles +#define B1RAT_15 0x0F000000 // Bank 1 Read Access Time = + // 15 cycles +#define B1WAT_1 0x10000000 // Bank 1 Write Access Time = + // 1 cycle +#define B1WAT_2 0x20000000 // Bank 1 Write Access Time = + // 2 cycles +#define B1WAT_3 0x30000000 // Bank 1 Write Access Time = + // 3 cycles +#define B1WAT_4 0x40000000 // Bank 1 Write Access Time = + // 4 cycles +#define B1WAT_5 0x50000000 // Bank 1 Write Access Time = + // 5 cycles +#define B1WAT_6 0x60000000 // Bank 1 Write Access Time = + // 6 cycles +#define B1WAT_7 0x70000000 // Bank 1 Write Access Time = + // 7 cycles +#define B1WAT_8 0x80000000 // Bank 1 Write Access Time = + // 8 cycles +#define B1WAT_9 0x90000000 // Bank 1 Write Access Time = + // 9 cycles +#define B1WAT_10 0xA0000000 // Bank 1 Write Access Time = + // 10 cycles +#define B1WAT_11 0xB0000000 // Bank 1 Write Access Time = + // 11 cycles +#define B1WAT_12 0xC0000000 // Bank 1 Write Access Time = + // 12 cycles +#define B1WAT_13 0xD0000000 // Bank 1 Write Access Time = + // 13 cycles +#define B1WAT_14 0xE0000000 // Bank 1 Write Access Time = + // 14 cycles +#define B1WAT_15 0xF0000000 // Bank 1 Write Access Time = + // 15 cycles + +// AMBCTL1 Masks +#define B2RDYEN 0x00000001 // Bank 2 RDY Enable, + // 0=disable, 1=enable +#define B2RDYPOL 0x00000002 // Bank 2 RDY Active high, + // 0=active low, 1=active + // high +#define B2TT_1 0x00000004 // Bank 2 Transition Time + // from Read to Write = 1 + // cycle +#define B2TT_2 0x00000008 // Bank 2 Transition Time + // from Read to Write = 2 + // cycles +#define B2TT_3 0x0000000C // Bank 2 Transition Time + // from Read to Write = 3 + // cycles +#define B2TT_4 0x00000000 // Bank 2 Transition Time + // from Read to Write = 4 + // cycles +#define B2ST_1 0x00000010 // Bank 2 Setup Time from AOE + // asserted to Read or Write + // asserted = 1 cycle +#define B2ST_2 0x00000020 // Bank 2 Setup Time from AOE + // asserted to Read or Write + // asserted = 2 cycles +#define B2ST_3 0x00000030 // Bank 2 Setup Time from AOE + // asserted to Read or Write + // asserted = 3 cycles +#define B2ST_4 0x00000000 // Bank 2 Setup Time from AOE + // asserted to Read or Write + // asserted = 4 cycles +#define B2HT_1 0x00000040 // Bank 2 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 1 cycle +#define B2HT_2 0x00000080 // Bank 2 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 2 cycles +#define B2HT_3 0x000000C0 // Bank 2 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 3 cycles +#define B2HT_0 0x00000000 // Bank 2 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 0 cycles +#define B2RAT_1 0x00000100 // Bank 2 Read Access Time = + // 1 cycle +#define B2RAT_2 0x00000200 // Bank 2 Read Access Time = + // 2 cycles +#define B2RAT_3 0x00000300 // Bank 2 Read Access Time = + // 3 cycles +#define B2RAT_4 0x00000400 // Bank 2 Read Access Time = + // 4 cycles +#define B2RAT_5 0x00000500 // Bank 2 Read Access Time = + // 5 cycles +#define B2RAT_6 0x00000600 // Bank 2 Read Access Time = + // 6 cycles +#define B2RAT_7 0x00000700 // Bank 2 Read Access Time = + // 7 cycles +#define B2RAT_8 0x00000800 // Bank 2 Read Access Time = + // 8 cycles +#define B2RAT_9 0x00000900 // Bank 2 Read Access Time = + // 9 cycles +#define B2RAT_10 0x00000A00 // Bank 2 Read Access Time = + // 10 cycles +#define B2RAT_11 0x00000B00 // Bank 2 Read Access Time = + // 11 cycles +#define B2RAT_12 0x00000C00 // Bank 2 Read Access Time = + // 12 cycles +#define B2RAT_13 0x00000D00 // Bank 2 Read Access Time = + // 13 cycles +#define B2RAT_14 0x00000E00 // Bank 2 Read Access Time = + // 14 cycles +#define B2RAT_15 0x00000F00 // Bank 2 Read Access Time = + // 15 cycles +#define B2WAT_1 0x00001000 // Bank 2 Write Access Time = + // 1 cycle +#define B2WAT_2 0x00002000 // Bank 2 Write Access Time = + // 2 cycles +#define B2WAT_3 0x00003000 // Bank 2 Write Access Time = + // 3 cycles +#define B2WAT_4 0x00004000 // Bank 2 Write Access Time = + // 4 cycles +#define B2WAT_5 0x00005000 // Bank 2 Write Access Time = + // 5 cycles +#define B2WAT_6 0x00006000 // Bank 2 Write Access Time = + // 6 cycles +#define B2WAT_7 0x00007000 // Bank 2 Write Access Time = + // 7 cycles +#define B2WAT_8 0x00008000 // Bank 2 Write Access Time = + // 8 cycles +#define B2WAT_9 0x00009000 // Bank 2 Write Access Time = + // 9 cycles +#define B2WAT_10 0x0000A000 // Bank 2 Write Access Time = + // 10 cycles +#define B2WAT_11 0x0000B000 // Bank 2 Write Access Time = + // 11 cycles +#define B2WAT_12 0x0000C000 // Bank 2 Write Access Time = + // 12 cycles +#define B2WAT_13 0x0000D000 // Bank 2 Write Access Time = + // 13 cycles +#define B2WAT_14 0x0000E000 // Bank 2 Write Access Time = + // 14 cycles +#define B2WAT_15 0x0000F000 // Bank 2 Write Access Time = + // 15 cycles +#define B3RDYEN 0x00010000 // Bank 3 RDY enable, + // 0=disable, 1=enable +#define B3RDYPOL 0x00020000 // Bank 3 RDY Active high, + // 0=active low, 1=active + // high +#define B3TT_1 0x00040000 // Bank 3 Transition Time + // from Read to Write = 1 + // cycle +#define B3TT_2 0x00080000 // Bank 3 Transition Time + // from Read to Write = 2 + // cycles +#define B3TT_3 0x000C0000 // Bank 3 Transition Time + // from Read to Write = 3 + // cycles +#define B3TT_4 0x00000000 // Bank 3 Transition Time + // from Read to Write = 4 + // cycles +#define B3ST_1 0x00100000 // Bank 3 Setup Time from AOE + // asserted to Read or Write + // asserted = 1 cycle +#define B3ST_2 0x00200000 // Bank 3 Setup Time from AOE + // asserted to Read or Write + // asserted = 2 cycles +#define B3ST_3 0x00300000 // Bank 3 Setup Time from AOE + // asserted to Read or Write + // asserted = 3 cycles +#define B3ST_4 0x00000000 // Bank 3 Setup Time from AOE + // asserted to Read or Write + // asserted = 4 cycles +#define B3HT_1 0x00400000 // Bank 3 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 1 cycle +#define B3HT_2 0x00800000 // Bank 3 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 2 cycles +#define B3HT_3 0x00C00000 // Bank 3 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 3 cycles +#define B3HT_0 0x00000000 // Bank 3 Hold Time from Read + // or Write deasserted to AOE + // deasserted = 0 cycles +#define B3RAT_1 0x01000000 // Bank 3 Read Access Time = + // 1 cycle +#define B3RAT_2 0x02000000 // Bank 3 Read Access Time = + // 2 cycles +#define B3RAT_3 0x03000000 // Bank 3 Read Access Time = + // 3 cycles +#define B3RAT_4 0x04000000 // Bank 3 Read Access Time = + // 4 cycles +#define B3RAT_5 0x05000000 // Bank 3 Read Access Time = + // 5 cycles +#define B3RAT_6 0x06000000 // Bank 3 Read Access Time = + // 6 cycles +#define B3RAT_7 0x07000000 // Bank 3 Read Access Time = + // 7 cycles +#define B3RAT_8 0x08000000 // Bank 3 Read Access Time = + // 8 cycles +#define B3RAT_9 0x09000000 // Bank 3 Read Access Time = + // 9 cycles +#define B3RAT_10 0x0A000000 // Bank 3 Read Access Time = + // 10 cycles +#define B3RAT_11 0x0B000000 // Bank 3 Read Access Time = + // 11 cycles +#define B3RAT_12 0x0C000000 // Bank 3 Read Access Time = + // 12 cycles +#define B3RAT_13 0x0D000000 // Bank 3 Read Access Time = + // 13 cycles +#define B3RAT_14 0x0E000000 // Bank 3 Read Access Time = + // 14 cycles +#define B3RAT_15 0x0F000000 // Bank 3 Read Access Time = + // 15 cycles +#define B3WAT_1 0x10000000 // Bank 3 Write Access Time = + // 1 cycle +#define B3WAT_2 0x20000000 // Bank 3 Write Access Time = + // 2 cycles +#define B3WAT_3 0x30000000 // Bank 3 Write Access Time = + // 3 cycles +#define B3WAT_4 0x40000000 // Bank 3 Write Access Time = + // 4 cycles +#define B3WAT_5 0x50000000 // Bank 3 Write Access Time = + // 5 cycles +#define B3WAT_6 0x60000000 // Bank 3 Write Access Time = + // 6 cycles +#define B3WAT_7 0x70000000 // Bank 3 Write Access Time = + // 7 cycles +#define B3WAT_8 0x80000000 // Bank 3 Write Access Time = + // 8 cycles +#define B3WAT_9 0x90000000 // Bank 3 Write Access Time = + // 9 cycles +#define B3WAT_10 0xA0000000 // Bank 3 Write Access Time = + // 10 cycles +#define B3WAT_11 0xB0000000 // Bank 3 Write Access Time = + // 11 cycles +#define B3WAT_12 0xC0000000 // Bank 3 Write Access Time = + // 12 cycles +#define B3WAT_13 0xD0000000 // Bank 3 Write Access Time = + // 13 cycles +#define B3WAT_14 0xE0000000 // Bank 3 Write Access Time = + // 14 cycles +#define B3WAT_15 0xF0000000 // Bank 3 Write Access Time = + // 15 cycles + +// ********************** SDRAM CONTROLLER MASKS *************************** + +// EBIU_SDGCTL Masks +#define SCTLE 0x00000001 // Enable SCLK[0], /SRAS, + // /SCAS, /SWE, SDQM[3:0] +#define CL_2 0x00000008 // SDRAM CAS latency = 2 + // cycles +#define CL_3 0x0000000C // SDRAM CAS latency = 3 + // cycles +#define PFE 0x00000010 // Enable SDRAM prefetch +#define PFP 0x00000020 // Prefetch has priority over + // AMC requests +#define TRAS_1 0x00000040 // SDRAM tRAS = 1 cycle +#define TRAS_2 0x00000080 // SDRAM tRAS = 2 cycles +#define TRAS_3 0x000000C0 // SDRAM tRAS = 3 cycles +#define TRAS_4 0x00000100 // SDRAM tRAS = 4 cycles +#define TRAS_5 0x00000140 // SDRAM tRAS = 5 cycles +#define TRAS_6 0x00000180 // SDRAM tRAS = 6 cycles +#define TRAS_7 0x000001C0 // SDRAM tRAS = 7 cycles +#define TRAS_8 0x00000200 // SDRAM tRAS = 8 cycles +#define TRAS_9 0x00000240 // SDRAM tRAS = 9 cycles +#define TRAS_10 0x00000280 // SDRAM tRAS = 10 cycles +#define TRAS_11 0x000002C0 // SDRAM tRAS = 11 cycles +#define TRAS_12 0x00000300 // SDRAM tRAS = 12 cycles +#define TRAS_13 0x00000340 // SDRAM tRAS = 13 cycles +#define TRAS_14 0x00000380 // SDRAM tRAS = 14 cycles +#define TRAS_15 0x000003C0 // SDRAM tRAS = 15 cycles +#define TRP_1 0x00000800 // SDRAM tRP = 1 cycle +#define TRP_2 0x00001000 // SDRAM tRP = 2 cycles +#define TRP_3 0x00001800 // SDRAM tRP = 3 cycles +#define TRP_4 0x00002000 // SDRAM tRP = 4 cycles +#define TRP_5 0x00002800 // SDRAM tRP = 5 cycles +#define TRP_6 0x00003000 // SDRAM tRP = 6 cycles +#define TRP_7 0x00003800 // SDRAM tRP = 7 cycles +#define TRCD_1 0x00008000 // SDRAM tRCD = 1 cycle +#define TRCD_2 0x00010000 // SDRAM tRCD = 2 cycles +#define TRCD_3 0x00018000 // SDRAM tRCD = 3 cycles +#define TRCD_4 0x00020000 // SDRAM tRCD = 4 cycles +#define TRCD_5 0x00028000 // SDRAM tRCD = 5 cycles +#define TRCD_6 0x00030000 // SDRAM tRCD = 6 cycles +#define TRCD_7 0x00038000 // SDRAM tRCD = 7 cycles +#define TWR_1 0x00080000 // SDRAM tWR = 1 cycle +#define TWR_2 0x00100000 // SDRAM tWR = 2 cycles +#define TWR_3 0x00180000 // SDRAM tWR = 3 cycles +#define PUPSD 0x00200000 // Power-up start delay +#define PSM 0x00400000 // SDRAM power-up sequence = + // Precharge, mode register + // set, 8 CBR refresh cycles +#define PSS 0x00800000 // enable SDRAM power-up + // sequence on next SDRAM access +#define SRFS 0x01000000 // Start SDRAM self-refresh + // mode +#define EBUFE 0x02000000 // Enable external buffering + // timing +#define FBBRW 0x04000000 // Fast back-to-back read + // write enable +#define EMREN 0x10000000 // Extended mode register + // enable +#define TCSR 0x20000000 // Temp compensated self + // refresh value 85 deg C +#define CDDBG 0x40000000 // Tristate SDRAM controls + // during bus grant + +// EBIU_SDBCTL Masks +#define EB0_E 0x00000001 // Enable SDRAM + // external bank 0 +#define EB0_SZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EB0_SZ_32 0x00000002 // SDRAM external + // bank size = 32MB +#define EB0_SZ_64 0x00000004 // SDRAM external + // bank size = 64MB +#define EB0_SZ_128 0x00000006 // SDRAM external + // bank size = 128MB +#define EB0_CAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EB0_CAW_9 0x00000010 // SDRAM external bank column + // address width = 9 bits +#define EB0_CAW_10 0x00000020 // SDRAM external bank column + // address width = 9 bits +#define EB0_CAW_11 0x00000030 // SDRAM external bank column + // address width = 9 bits + +#define EB1_E 0x00000100 // Enable SDRAM + // external bank 1 +#define EB1__SZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EB1__SZ_32 0x00000200 // SDRAM external + // bank size = 32MB +#define EB1__SZ_64 0x00000400 // SDRAM external + // bank size = 64MB +#define EB1__SZ_128 0x00000600 // SDRAM external + // bank size = 128MB +#define EB1__CAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EB1__CAW_9 0x00001000 // SDRAM external bank column + // address width = 9 bits +#define EB1__CAW_10 0x00002000 // SDRAM external bank column + // address width = 9 bits +#define EB1__CAW_11 0x00003000 // SDRAM external bank column + // address width = 9 bits + +#define EB2__E 0x00010000 // Enable SDRAM + // external bank 2 +#define EB2__SZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EB2__SZ_32 0x00020000 // SDRAM external + // bank size = 32MB +#define EB2__SZ_64 0x00040000 // SDRAM external + // bank size = 64MB +#define EB2__SZ_128 0x00060000 // SDRAM external + // bank size = 128MB +#define EB2__CAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EB2__CAW_9 0x00100000 // SDRAM external bank column + // address width = 9 bits +#define EB2__CAW_10 0x00200000 // SDRAM external bank column + // address width = 9 bits +#define EB2__CAW_11 0x00300000 // SDRAM external bank column + // address width = 9 bits + +#define EB3__E 0x01000000 // Enable SDRAM external bank 3 +#define EB3__SZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EB3__SZ_32 0x02000000 // SDRAM external + // bank size = 32MB +#define EB3__SZ_64 0x04000000 // SDRAM external + // bank size = 64MB +#define EB3__SZ_128 0x06000000 // SDRAM external + // bank size = 128MB +#define EB3__CAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EB3__CAW_9 0x10000000 // SDRAM external bank column + // address width = 9 bits +#define EB3__CAW_10 0x20000000 // SDRAM external bank column + // address width = 9 bits +#define EB3__CAW_11 0x30000000 // SDRAM external bank column + // address width = 9 bits + +// EBIU_SDSTAT Masks +#define SDCI 0x00000001 // SDRAM controller is idle +#define SDSRA 0x00000002 // SDRAM SDRAM self refresh + // is active +#define SDPUA 0x00000004 // SDRAM power up active +#define SDRS 0x00000008 // SDRAM is in reset state +#define SDEASE 0x00000010 // SDRAM EAB sticky error + // status - W1C +#define BGSTAT 0x00000020 // Bus granted + + +#if 1 /* comment by mhfan */ +#define COREMMR_BASE 0xFFE00000 // Core MMRs +#define SYSMMR_BASE 0xFFC00000 // System MMRs + +// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) +#define WDOG_CTL 0xFFC00200 // Watchdog Control register +#define WDOG_CNT 0xFFC00204 // Watchdog Count register +#define WDOG_STAT 0xFFC00208 // Watchdog Status register + +// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) +#define FIO_FLAG_D 0xFFC00700 // Flag Data register +#define FIO_FLAG_C 0xFFC00704 // Flag Clear register +#define FIO_FLAG_S 0xFFC00708 // Flag Set register +#define FIO_FLAG_T 0xFFC0070C // Flag Toggle register +#define FIO_MASKA_D 0xFFC00710 // Flag Mask Interrupt A Data + // register +#define FIO_MASKA_C 0xFFC00714 // Flag Mask Interrupt A Clear + // register +#define FIO_MASKA_S 0xFFC00718 // Flag Mask Interrupt A Set + // register +#define FIO_MASKA_T 0xFFC0071C // Flag Mask Interrupt A Toggle + // register +#define FIO_MASKB_D 0xFFC00720 // Flag Mask Interrupt B Data + // register +#define FIO_MASKB_C 0xFFC00724 // Flag Mask Interrupt B Clear + // register +#define FIO_MASKB_S 0xFFC00728 // Flag Mask Interrupt B Set + // register +#define FIO_MASKB_T 0xFFC0072C // Flag Mask Interrupt B Toggle + // register +#define FIO_DIR 0xFFC00730 // Flag Direction register +#define FIO_POLAR 0xFFC00734 // Flag Polarity register +#define FIO_EDGE 0xFFC00738 // Flag Interrupt Sensitivity + // register +#define FIO_BOTH 0xFFC0073C // Flag Set on Both Edges + // register +#define FIO_INEN 0xFFC00740 // Flag Input Enable register + +// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) +#define PPI_CONTROL 0xFFC01000 // PPI0 Control register +#define PPI_STATUS 0xFFC01004 // PPI0 Status register +#define PPI_COUNT 0xFFC01008 // PPI0 Transfer Count register +#define PPI_DELAY 0xFFC0100C // PPI0 Delay Count register +#define PPI_FRAME 0xFFC01010 // PPI0 Frame Length register + +// System Reset and Interrupt Controller registers for +// core A (0xFFC0 0100-0xFFC0 01FF) +#define SWRST 0xFFC00100 // Software Reset register +#define SYSCR 0xFFC00104 // System Reset Configuration + // register +#define RVECT 0xFFC00108 // SIC Reset Vector Address + // Register +#define SIC_SWRST 0xFFC00100 // Software Reset register +#define SIC_SYSCR 0xFFC00104 // System Reset Configuration + // register +#define SIC_RVECT 0xFFC00108 // SIC Reset Vector Address + // Register +#define SIC_IMASK 0xFFC0010C // SIC Interrupt Mask + // register 0 - hack to fix + // old tests +#define SIC_IAR 0xFFC00124 // SIC Interrupt Assignment + // Register 0 +#define SIC_IAR1 0xFFC00128 // SIC Interrupt Assignment + // Register 1 +#define SIC_IAR2 0xFFC0012C // SIC Interrupt Assignment + // Register 2 +#define SIC_ISR 0xFFC00114 // SIC Interrupt Status + // register 0 +#define SIC_IWR 0xFFC0011C // SIC Interrupt + // Wakeup-Enable register 0 + +// EBIU_SDBCTL Masks +#define EB_E 0x00000001 // Enable SDRAM + // external bank 0 +#define EB_SZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EB_SZ_32 0x00000002 // SDRAM external + // bank size = 32MB +#define EB_SZ_64 0x00000004 // SDRAM external + // bank size = 64MB +#define EB_SZ_128 0x00000006 // SDRAM external + // bank size = 128MB +#define EB_CAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EB_CAW_9 0x00000010 // SDRAM external bank column + // address width = 9 bits +#define EB_CAW_10 0x00000020 // SDRAM external bank column + // address width = 9 bits +#define EB_CAW_11 0x00000030 // SDRAM external bank column + // address width = 9 bits + +// EBIU_SDBCTL Masks +#define EBE 0x00000001 // Enable SDRAM + // external bank 0 +#define EBSZ_16 0x00000000 // SDRAM external + // bank size = 16MB +#define EBSZ_32 0x00000002 // SDRAM external + // bank size = 32MB +#define EBSZ_64 0x00000004 // SDRAM external + // bank size = 64MB +#define EBSZ_128 0x00000006 // SDRAM external + // bank size = 128MB +#define EBCAW_8 0x00000000 // SDRAM external bank column + // address width = 8 bits +#define EBCAW_9 0x00000010 // SDRAM external bank column + // address width = 9 bits +#define EBCAW_10 0x00000020 // SDRAM external bank column + // address width = 9 bits +#define EBCAW_11 0x00000030 // SDRAM external bank column + // address width = 9 bits + +// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) +#define MDMA_D0_CONFIG 0xFFC01F08 // MemDMA1 Stream 0 Destination + // Configuration +#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 // MemDMA1 Stream 0 + // Destination Next + // Descriptor Ptr Reg +#define MDMA_D0_START_ADDR 0xFFC01F04 // MemDMA1 Stream 0 Destination + // Start Address +#define MDMA_D0_X_COUNT 0xFFC01F10 // MemDMA1 Stream 0 Destination + // Inner-Loop Count +#define MDMA_D0_Y_COUNT 0xFFC01F18 // MemDMA1 Stream 0 Destination + // Outer-Loop Count +#define MDMA_D0_X_MODIFY 0xFFC01F14 // MemDMA1 Stream 0 Dest + // Inner-Loop Address-Increment +#define MDMA_D0_Y_MODIFY 0xFFC01F1C // MemDMA1 Stream 0 Dest + // Outer-Loop Address-Increment +#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 // MemDMA1 Stream 0 Dest + // Current Descriptor Ptr reg +#define MDMA_D0_CURR_ADDR 0xFFC01F24 // MemDMA1 Stream 0 Destination + // Current Address +#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 // MemDMA1 Stream 0 Dest + // Current Inner-Loop Count +#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 // MemDMA1 Stream 0 Dest + // Current Outer-Loop Count +#define MDMA_D0_IRQ_STATUS 0xFFC01F28 // MemDMA1 Stream 0 Destination + // Interrupt/Status +#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C // MemDMA1 Stream 0 + // Destination Peripheral Map + +#define MDMA_S0_CONFIG 0xFFC01F48 // MemDMA1 Stream 0 Source + // Configuration +#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 // MemDMA1 Stream 0 Source + // Next Descriptor Ptr Reg +#define MDMA_S0_START_ADDR 0xFFC01F44 // MemDMA1 Stream 0 Source + // Start Address +#define MDMA_S0_X_COUNT 0xFFC01F50 // MemDMA1 Stream 0 Source + // Inner-Loop Count +#define MDMA_S0_Y_COUNT 0xFFC01F58 // MemDMA1 Stream 0 Source + // Outer-Loop Count +#define MDMA_S0_X_MODIFY 0xFFC01F54 // MemDMA1 Stream 0 Source + // Inner-Loop Address-Increment +#define MDMA_S0_Y_MODIFY 0xFFC01F5C // MemDMA1 Stream 0 Source + // Outer-Loop Address-Increment +#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 // MemDMA1 Stream 0 Source + // Current Descriptor Ptr reg +#define MDMA_S0_CURR_ADDR 0xFFC01F64 // MemDMA1 Stream 0 Source + // Current Address +#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 // MemDMA1 Stream 0 Source + // Current Inner-Loop Count +#define MDMA_S0_CURR_Y_COUNT ` 0xFFC01F78 // MemDMA1 Stream 0 Source + // Current Outer-Loop Count +#define MDMA_S0_IRQ_STATUS 0xFFC01F68 // MemDMA1 Stream 0 Source + // Interrupt/Status +#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C // MemDMA1 Stream 0 Source + // Peripheral Map + +#define MDMA_D1_CONFIG 0xFFC01F88 // MemDMA1 Stream 1 Destination + // Configuration +#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 // MemDMA1 Stream 1 + // Destination Next + // Descriptor Ptr Reg +#define MDMA_D1_START_ADDR 0xFFC01F84 // MemDMA1 Stream 1 Destination + // Start Address +#define MDMA_D1_X_COUNT 0xFFC01F90 // MemDMA1 Stream 1 Destination + // Inner-Loop Count +#define MDMA_D1_Y_COUNT 0xFFC01F98 // MemDMA1 Stream 1 Destination + // Outer-Loop Count +#define MDMA_D1_X_MODIFY 0xFFC01F94 // MemDMA1 Stream 1 Dest + // Inner-Loop Address-Increment +#define MDMA_D1_Y_MODIFY 0xFFC01F9C // MemDMA1 Stream 1 Dest + // Outer-Loop Address-Increment +#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 // MemDMA1 Stream 1 Dest + // Current Descriptor Ptr reg +#define MDMA_D1_CURR_ADDR 0xFFC01FA4 // MemDMA1 Stream 1 Dest + // Current Address +#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 // MemDMA1 Stream 1 Dest + // Current Inner-Loop Count +#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 // MemDMA1 Stream 1 Dest + // Current Outer-Loop Count +#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 // MemDMA1 Stream 1 Dest + // Interrupt/Status +#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC // MemDMA1 Stream 1 Dest + // Peripheral Map + +#define MDMA_S1_CONFIG 0xFFC01FC8 // MemDMA1 Stream 1 Source + // Configuration +#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 // MemDMA1 Stream 1 Source + // Next Descriptor Ptr Reg +#define MDMA_S1_START_ADDR 0xFFC01FC4 // MemDMA1 Stream 1 Source + // Start Address +#define MDMA_S1_X_COUNT 0xFFC01FD0 // MemDMA1 Stream 1 Source + // Inner-Loop Count +#define MDMA_S1_Y_COUNT 0xFFC01FD8 // MemDMA1 Stream 1 Source + // Outer-Loop Count +#define MDMA_S1_X_MODIFY 0xFFC01FD4 // MemDMA1 Stream 1 Source + // Inner-Loop Address-Increment +#define MDMA_S1_Y_MODIFY 0xFFC01FDC // MemDMA1 Stream 1 Source + // Outer-Loop Address-Increment +#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 // MemDMA1 Stream 1 Source + // Current Descriptor Ptr reg +#define MDMA_S1_CURR_ADDR 0xFFC01FE4 // MemDMA1 Stream 1 Source + // Current Address +#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 // MemDMA1 Stream 1 Source + // Current Inner-Loop Count +#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 // MemDMA1 Stream 1 Source + // Current Outer-Loop Count +#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 // MemDMA1 Stream 1 Source + // Interrupt/Status +#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC // MemDMA1 Stream 1 Source + // Peripheral Map + +#define DMA0_CONFIG 0xFFC01C08 // DMA1 Channel 0 Configuration + // register +#define DMA0_NEXT_DESC_PTR 0xFFC01C00 // DMA1 Channel 0 Next + // Descripter Ptr Reg +#define DMA0_START_ADDR 0xFFC01C04 // DMA1 Channel 0 Start Address +#define DMA0_X_COUNT 0xFFC01C10 // DMA1 Channel 0 Inner Loop + // Count +#define DMA0_Y_COUNT 0xFFC01C18 // DMA1 Channel 0 Outer Loop + // Count +#define DMA0_X_MODIFY 0xFFC01C14 // DMA1 Channel 0 Inner Loop + // Addr Increment +#define DMA0_Y_MODIFY 0xFFC01C1C // DMA1 Channel 0 Outer Loop + // Addr Increment +#define DMA0_CURR_DESC_PTR 0xFFC01C20 // DMA1 Channel 0 Current + // Descriptor Pointer +#define DMA0_CURR_ADDR 0xFFC01C24 // DMA1 Channel 0 Current + // Address Pointer +#define DMA0_CURR_X_COUNT 0xFFC01C30 // DMA1 Channel 0 Current Inner + // Loop Count +#define DMA0_CURR_Y_COUNT 0xFFC01C38 // DMA1 Channel 0 Current Outer + // Loop Count +#define DMA0_IRQ_STATUS 0xFFC01C28 // DMA1 Channel 0 Interrupt + // Status Register +#define DMA0_PERIPHERAL_MAP 0xFFC01C2C // DMA1 Channel 0 Peripheral + // Map Register + +#define DMA1_CONFIG 0xFFC00C08 // DMA2 Channel 0 Configuration + // register +#define DMA1_NEXT_DESC_PTR 0xFFC00C00 // DMA2 Channel 0 Next + // Descripter Ptr Reg +#define DMA1_START_ADDR 0xFFC00C04 // DMA2 Channel 0 Start Address +#define DMA1_X_COUNT 0xFFC00C10 // DMA2 Channel 0 Inner Loop + // Count +#define DMA1_Y_COUNT 0xFFC00C18 // DMA2 Channel 0 Outer Loop + // Count +#define DMA1_X_MODIFY 0xFFC00C14 // DMA2 Channel 0 Inner Loop + // Addr Increment +#define DMA1_Y_MODIFY 0xFFC00C1C // DMA2 Channel 0 Outer Loop + // Addr Increment +#define DMA1_CURR_DESC_PTR 0xFFC00C20 // DMA2 Channel 0 Current + // Descriptor Pointer +#define DMA1_CURR_ADDR 0xFFC00C24 // DMA2 Channel 0 Current + // Address Pointer +#define DMA1_CURR_X_COUNT 0xFFC00C30 // DMA2 Channel 0 Current Inner + // Loop Count +#define DMA1_CURR_Y_COUNT 0xFFC00C38 // DMA2 Channel 0 Current Outer + // Loop Count +#define DMA1_IRQ_STATUS 0xFFC00C28 // DMA2 Channel 0 Interrupt + // /Status Register +#define DMA1_PERIPHERAL_MAP 0xFFC00C2C // DMA2 Channel 0 Peripheral + // Map Register + +#define DMA2_CONFIG 0xFFC00C48 // DMA2 Channel 1 Configuration + // register +#define DMA2_NEXT_DESC_PTR 0xFFC00C40 // DMA2 Channel 1 Next + // Descripter Ptr Reg +#define DMA2_START_ADDR 0xFFC00C44 // DMA2 Channel 1 Start Address +#define DMA2_X_COUNT 0xFFC00C50 // DMA2 Channel 1 Inner Loop + // Count +#define DMA2_Y_COUNT 0xFFC00C58 // DMA2 Channel 1 Outer Loop + // Count +#define DMA2_X_MODIFY 0xFFC00C54 // DMA2 Channel 1 Inner Loop + // Addr Increment +#define DMA2_Y_MODIFY 0xFFC00C5C // DMA2 Channel 1 Outer Loop + // Addr Increment +#define DMA2_CURR_DESC_PTR 0xFFC00C60 // DMA2 Channel 1 Current + // Descriptor Pointer +#define DMA2_CURR_ADDR 0xFFC00C64 // DMA2 Channel 1 Current + // Address Pointer +#define DMA2_CURR_X_COUNT 0xFFC00C70 // DMA2 Channel 1 Current + // Inner Loop Count +#define DMA2_CURR_Y_COUNT 0xFFC00C78 // DMA2 Channel 1 Current + // Outer Loop Count +#define DMA2_IRQ_STATUS 0xFFC00C68 // DMA2 Channel 1 Interrupt + // /Status Register +#define DMA2_PERIPHERAL_MAP 0xFFC00C6C // DMA2 Channel 1 Peripheral + // Map Register + +#define DMA3_CONFIG 0xFFC00C88 // DMA2 Channel 2 Configuration + // register +#define DMA3_NEXT_DESC_PTR 0xFFC00C80 // DMA2 Channel 2 Next + // Descripter Ptr Reg +#define DMA3_START_ADDR 0xFFC00C84 // DMA2 Channel 2 Start Address +#define DMA3_X_COUNT 0xFFC00C90 // DMA2 Channel 2 Inner Loop + // Count +#define DMA3_Y_COUNT 0xFFC00C98 // DMA2 Channel 2 Outer Loop + // Count +#define DMA3_X_MODIFY 0xFFC00C94 // DMA2 Channel 2 Inner Loop + // Addr Increment +#define DMA3_Y_MODIFY 0xFFC00C9C // DMA2 Channel 2 Outer Loop + // Addr Increment +#define DMA3_CURR_DESC_PTR 0xFFC00CA0 // DMA2 Channel 2 Current + // Descriptor Pointer +#define DMA3_CURR_ADDR 0xFFC00CA4 // DMA2 Channel 2 Current + // Address Pointer +#define DMA3_CURR_X_COUNT 0xFFC00CB0 // DMA2 Channel 2 Current Inner + // Loop Count +#define DMA3_CURR_Y_COUNT 0xFFC00CB8 // DMA2 Channel 2 Current Outer + // Loop Count +#define DMA3_IRQ_STATUS 0xFFC00CA8 // DMA2 Channel 2 Interrupt + // /Status Register +#define DMA3_PERIPHERAL_MAP 0xFFC00CAC // DMA2 Channel 2 Peripheral + // Map Register + +#define DMA4_CONFIG 0xFFC00CC8 // DMA2 Channel 3 Configuration + // register +#define DMA4_NEXT_DESC_PTR 0xFFC00CC0 // DMA2 Channel 3 Next + // Descripter Ptr Reg +#define DMA4_START_ADDR 0xFFC00CC4 // DMA2 Channel 3 Start Address +#define DMA4_X_COUNT 0xFFC00CD0 // DMA2 Channel 3 Inner Loop + // Count +#define DMA4_Y_COUNT 0xFFC00CD8 // DMA2 Channel 3 Outer Loop + // Count +#define DMA4_X_MODIFY 0xFFC00CD4 // DMA2 Channel 3 Inner Loop + // Addr Increment +#define DMA4_Y_MODIFY 0xFFC00CDC // DMA2 Channel 3 Outer Loop + // Addr Increment +#define DMA4_CURR_DESC_PTR 0xFFC00CE0 // DMA2 Channel 3 Current + // Descriptor Pointer +#define DMA4_CURR_ADDR 0xFFC00CE4 // DMA2 Channel 3 Current + // Address Pointer +#define DMA4_CURR_X_COUNT 0xFFC00CF0 // DMA2 Channel 3 Current Inner + // Loop Count +#define DMA4_CURR_Y_COUNT 0xFFC00CF8 // DMA2 Channel 3 Current Outer + // Loop Count +#define DMA4_IRQ_STATUS 0xFFC00CE8 // DMA2 Channel 3 Interrupt + // /Status Register +#define DMA4_PERIPHERAL_MAP 0xFFC00CEC // DMA2 Channel 3 Peripheral + // Map Register + +#define DMA5_CONFIG 0xFFC00D08 // DMA2 Channel 4 Configuration + // register +#define DMA5_NEXT_DESC_PTR 0xFFC00D00 // DMA2 Channel 4 Next + // Descripter Ptr Reg +#define DMA5_START_ADDR 0xFFC00D04 // DMA2 Channel 4 Start Address +#define DMA5_X_COUNT 0xFFC00D10 // DMA2 Channel 4 Inner Loop + // Count +#define DMA5_Y_COUNT 0xFFC00D18 // DMA2 Channel 4 Outer Loop + // Count +#define DMA5_X_MODIFY 0xFFC00D14 // DMA2 Channel 4 Inner Loop + // Addr Increment +#define DMA5_Y_MODIFY 0xFFC00D1C // DMA2 Channel 4 Outer Loop + // Addr Increment +#define DMA5_CURR_DESC_PTR 0xFFC00D20 // DMA2 Channel 4 Current + // Descriptor Pointer +#define DMA5_CURR_ADDR 0xFFC00D24 // DMA2 Channel 4 Current + // Address Pointer +#define DMA5_CURR_X_COUNT 0xFFC00D30 // DMA2 Channel 4 Current Inner + // Loop Count +#define DMA5_CURR_Y_COUNT 0xFFC00D38 // DMA2 Channel 4 Current Outer + // Loop Count +#define DMA5_IRQ_STATUS 0xFFC00D28 // DMA2 Channel 4 Interrupt + // /Status Register +#define DMA5_PERIPHERAL_MAP 0xFFC00D2C // DMA2 Channel 4 Peripheral + // Map Register + +#define DMA6_CONFIG 0xFFC00D48 // DMA2 Channel 5 Configuration + // register +#define DMA6_NEXT_DESC_PTR 0xFFC00D40 // DMA2 Channel 5 Next + // Descripter Ptr Reg +#define DMA6_START_ADDR 0xFFC00D44 // DMA2 Channel 5 Start Address +#define DMA6_X_COUNT 0xFFC00D50 // DMA2 Channel 5 Inner Loop + // Count +#define DMA6_Y_COUNT 0xFFC00D58 // DMA2 Channel 5 Outer Loop + // Count +#define DMA6_X_MODIFY 0xFFC00D54 // DMA2 Channel 5 Inner Loop + // Addr Increment +#define DMA6_Y_MODIFY 0xFFC00D5C // DMA2 Channel 5 Outer Loop + // Addr Increment +#define DMA6_CURR_DESC_PTR 0xFFC00D60 // DMA2 Channel 5 Current + // Descriptor Pointer +#define DMA6_CURR_ADDR 0xFFC00D64 // DMA2 Channel 5 Current + // Address Pointer +#define DMA6_CURR_X_COUNT 0xFFC00D70 // DMA2 Channel 5 Current Inner + // Loop Count +#define DMA6_CURR_Y_COUNT 0xFFC00D78 // DMA2 Channel 5 Current Outer + // Loop Count +#define DMA6_IRQ_STATUS 0xFFC00D68 // DMA2 Channel 5 Interrupt + // /Status Register +#define DMA6_PERIPHERAL_MAP 0xFFC00D6C // DMA2 Channel 5 Peripheral + // Map Register + +#define DMA7_CONFIG 0xFFC00D88 // DMA2 Channel 6 Configuration + // register +#define DMA7_NEXT_DESC_PTR 0xFFC00D80 // DMA2 Channel 6 Next + // Descripter Ptr Reg +#define DMA7_START_ADDR 0xFFC00D84 // DMA2 Channel 6 Start Address +#define DMA7_X_COUNT 0xFFC00D90 // DMA2 Channel 6 Inner Loop + // Count +#define DMA7_Y_COUNT 0xFFC00D98 // DMA2 Channel 6 Outer Loop + // Count +#define DMA7_X_MODIFY 0xFFC00D94 // DMA2 Channel 6 Inner Loop + // Addr Increment +#define DMA7_Y_MODIFY 0xFFC00D9C // DMA2 Channel 6 Outer Loop + // Addr Increment +#define DMA7_CURR_DESC_PTR 0xFFC00DA0 // DMA2 Channel 6 Current + // Descriptor Pointer +#define DMA7_CURR_ADDR 0xFFC00DA4 // DMA2 Channel 6 Current + // Address Pointer +#define DMA7_CURR_X_COUNT 0xFFC00DB0 // DMA2 Channel 6 Current Inner + // Loop Count +#define DMA7_CURR_Y_COUNT 0xFFC00DB8 // DMA2 Channel 6 Current Outer + // Loop Count +#define DMA7_IRQ_STATUS 0xFFC00DA8 // DMA2 Channel 6 Interrupt + // /Status Register +#define DMA7_PERIPHERAL_MAP 0xFFC00DAC // DMA2 Channel 6 Peripheral + // Map Register + +#define TIMER_ENABLE 0xFFC00680 // Timer Enable Register +#define TIMER_DISABLE 0xFFC00684 // Timer Disable register +#define TIMER_STATUS 0xFFC00688 // Timer Status register + +// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks +#define WDSIZE8 0x00000000 // Word Size 8 bits +#define WDSIZE16 0x00000004 // Word Size 16 bits +#define WDSIZE32 0x00000008 // Word Size 32 bits +#endif /* comment by mhfan */ + +#endif /* _DEF_BF561_H */ diff --git a/include/asm-blackfin/cpu/defBF561_extn.h b/include/asm-blackfin/cpu/defBF561_extn.h new file mode 100644 index 0000000000..8112c3fe1e --- /dev/null +++ b/include/asm-blackfin/cpu/defBF561_extn.h @@ -0,0 +1,76 @@ +/* + * defBF533_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF533_EXTN_H +#define _DEF_BF533_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define PLL_DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h deleted file mode 100644 index 56a12f07b3..0000000000 --- a/include/asm-blackfin/global_data.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * U-boot - global_data.h Declarations for global data of u-boot - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include <asm/irq.h> - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) - */ -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long board_type; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - unsigned long ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5") - -#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index e5b388e262..0a8551218a 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -25,10 +25,6 @@ #ifndef _BLACKFIN_IO_H #define _BLACKFIN_IO_H -#ifdef __KERNEL__ - -#include <linux/config.h> - /* function prototypes for CF support */ extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); @@ -119,4 +115,3 @@ extern void blkfin_inv_cache_all(void); #define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) #endif -#endif diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h deleted file mode 100644 index 0a43ba1c5a..0000000000 --- a/include/asm-blackfin/machdep.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * U-boot - machdep.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_MACHDEP_H -#define _BLACKFIN_MACHDEP_H - -/* Machine dependent initial routines: - * - * Based on include/asm-m68knommu/machdep.h - * For blackfin, just now we only have bfin, so they'd point to the default bfin - * - */ - -struct pt_regs; -struct kbd_repeat; -struct mktime; -struct hwclk_time; -struct gendisk; -struct buffer_head; - -extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); - -/* machine dependent keyboard functions */ -extern int (*mach_keyb_init) (void); -extern int (*mach_kbdrate) (struct kbd_repeat *); -extern void (*mach_kbd_leds) (unsigned int); - -/* machine dependent irq functions */ -extern void (*mach_init_IRQ) (void); -extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *); -extern int (*mach_request_irq) (unsigned int irq, - void (*handler) (int, void *, - struct pt_regs *), - unsigned long flags, const char *devname, - void *dev_id); -extern void (*mach_free_irq) (unsigned int irq, void *dev_id); -extern void (*mach_get_model) (char *model); -extern int (*mach_get_hardware_list) (char *buffer); -extern int (*mach_get_irq_list) (char *buf); -extern void (*mach_process_int) (int irq, struct pt_regs * fp); - -/* machine dependent timer functions */ -extern unsigned long (*mach_gettimeoffset) (void); -extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour, - int *min, int *sec); -extern int (*mach_hwclk) (int, struct hwclk_time *); -extern int (*mach_set_clock_mmss) (unsigned long); -extern void (*mach_reset) (void); -extern void (*mach_halt) (void); -extern void (*mach_power_off) (void); -extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); -extern void (*mach_hd_setup) (char *, int *); -extern long mach_max_dma_address; -extern void (*mach_floppy_setup) (char *, int *); -extern void (*mach_floppy_eject) (void); -extern void (*mach_heartbeat) (int); -extern void (*mach_l2_flush) (int); -extern int mach_sysrq_key; -extern int mach_sysrq_shift_state; -extern int mach_sysrq_shift_mask; -extern char *mach_sysrq_xlate; - -#ifdef CONFIG_UCLINUX -extern void config_BSP(char *command, int len); -extern void (*mach_tick) (void); -#endif - -#endif diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h index 406ece5377..bf90cd56c6 100644 --- a/include/asm-blackfin/page.h +++ b/include/asm-blackfin/page.h @@ -25,8 +25,6 @@ #ifndef _BLACKFIN_PAGE_H #define _BLACKFIN_PAGE_H -#include <linux/config.h> - /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT (12) @@ -112,11 +110,6 @@ extern __inline__ int get_order(unsigned long size) #define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) #define VALID_PAGE(page) ((page - mem_map) < max_mapnr) -#define BUG() do { \ - \ - while (1); /* dead-loop */ \ -} while (0) - #define PAGE_BUG(page) do { \ BUG(); \ } while (0) diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h index 262473fc3d..1b9ee01982 100644 --- a/include/asm-blackfin/page_offset.h +++ b/include/asm-blackfin/page_offset.h @@ -22,12 +22,6 @@ * MA 02111-1307 USA */ -/* - * Changes made by Akbar Hussain April 10, 2001 - */ - -#include <linux/config.h> - /* This handles the memory map.. */ #ifdef CONFIG_BLACKFIN diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index a89ac0a9c4..7095e95626 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -36,7 +36,6 @@ */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) -#include <linux/config.h> #include <asm/segment.h> #include <asm/ptrace.h> #include <asm/current.h> diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h index 6ce96880ac..440aaf9d9c 100644 --- a/include/asm-blackfin/setup.h +++ b/include/asm-blackfin/setup.h @@ -29,8 +29,6 @@ #ifndef _BLACKFIN_SETUP_H #define _BLACKFIN_SETUP_H -#include <linux/config.h> - /* * Linux/Blackfin Architectures */ @@ -75,12 +73,14 @@ extern unsigned long vme_brdtype; extern int blackfin_num_memory; /* # of memory blocks found (and used) */ extern int blackfin_realnum_memory; /* real # of memory blocks found */ -extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ struct mem_info { unsigned long addr; /* physical address of memory chunk */ unsigned long size; /* length of memory chunk (in bytes) */ }; + +extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ + #endif #endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index ffd81d61a8..883009ae0d 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -27,53 +27,4 @@ #ifndef _BLACKFINNOMMU_STRING_H_ #define _BLACKFINNOMMU_STRING_H_ -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#include <asm/setup.h> -#include <asm/page.h> -#include <asm/cpu/defBF533.h> - -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRNCMP -#define __HAVE_ARCH_MEMCPY - -extern char *strcpy(char *dest, const char *src); -extern char *strncpy(char *dest, const char *src, size_t n); -extern int strcmp(const char *cs, const char *ct); -extern int strncmp(const char *cs, const char *ct, size_t count); -extern void * memcpy(void * dest,const void *src,size_t count); -extern void *memset(void *s, int c, size_t count); -extern int memcmp(const void *, const void *, __kernel_size_t); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ - #endif /* _BLACKFIN_STRING_H_ */ diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile deleted file mode 100644 index de7114b80a..0000000000 --- a/lib_blackfin/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# U-boot Makefile -# -# Copyright (c) 2005 blackfin.uclinux.org -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).a - -SOBJS = - -COBJS = board.o bf533_linux.o bf533_string.o cache.o muldi3.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c deleted file mode 100644 index d9dc2b6d0c..0000000000 --- a/lib_blackfin/board.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * U-boot - board.c First C file to be called contains init routines - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <devices.h> -#include <version.h> -#include <net.h> -#include <environment.h> -#include "blackfin_board.h" -#include "../drivers/smc91111.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; - - -static void mem_malloc_init(void) -{ - mem_malloc_start = CFG_MALLOC_BASE; - mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN); - mem_malloc_brk = mem_malloc_start; - memset((void *) mem_malloc_start, 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk(ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - - return ((void *) old); -} - -static int display_banner(void) -{ - sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING); - printf("%s\n", version_string); - return (0); -} - -static void display_flash_config(ulong size) -{ - puts("FLASH: "); - print_size(size, "\n"); - return; -} - -static int init_baudrate(void) -{ - uchar tmp[64]; - int i = getenv_r("baudrate", tmp, sizeof(tmp)); - gd->bd->bi_baudrate = gd->baudrate = (i > 0) - ? (int) simple_strtoul(tmp, NULL, 10) - : CONFIG_BAUDRATE; - return (0); -} - -#ifdef DEBUG -static void display_global_data(void) -{ - bd_t *bd; - bd = gd->bd; - printf("--flags:%x\n", gd->flags); - printf("--board_type:%x\n", gd->board_type); - printf("--baudrate:%x\n", gd->baudrate); - printf("--have_console:%x\n", gd->have_console); - printf("--ram_size:%x\n", gd->ram_size); - printf("--reloc_off:%x\n", gd->reloc_off); - printf("--env_addr:%x\n", gd->env_addr); - printf("--env_valid:%x\n", gd->env_valid); - printf("--bd:%x %x\n", gd->bd, bd); - printf("---bi_baudrate:%x\n", bd->bi_baudrate); - printf("---bi_ip_addr:%x\n", bd->bi_ip_addr); - printf("---bi_enetaddr:%x %x %x %x %x %x\n", - bd->bi_enetaddr[0], - bd->bi_enetaddr[1], - bd->bi_enetaddr[2], - bd->bi_enetaddr[3], - bd->bi_enetaddr[4], - bd->bi_enetaddr[5]); - printf("---bi_arch_number:%x\n", bd->bi_arch_number); - printf("---bi_boot_params:%x\n", bd->bi_boot_params); - printf("---bi_memstart:%x\n", bd->bi_memstart); - printf("---bi_memsize:%x\n", bd->bi_memsize); - printf("---bi_flashstart:%x\n", bd->bi_flashstart); - printf("---bi_flashsize:%x\n", bd->bi_flashsize); - printf("---bi_flashoffset:%x\n", bd->bi_flashoffset); - printf("--jt:%x *:%x\n", gd->jt, *(gd->jt)); -} -#endif - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - -void board_init_f(ulong bootflag) -{ - ulong addr; - bd_t *bd; - - gd = (gd_t *) (CFG_GBL_DATA_ADDR); - memset((void *) gd, 0, sizeof(gd_t)); - - /* Board data initialization */ - addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t)); - - /* Align to 4 byte boundary */ - addr &= ~(4 - 1); - bd = (bd_t*)addr; - gd->bd = bd; - memset((void *) bd, 0, sizeof(bd_t)); - - /* Initialize */ - init_IRQ(); - env_init(); /* initialize environment */ - init_baudrate(); /* initialze baudrate settings */ - serial_init(); /* serial communications setup */ - console_init_f(); - display_banner(); /* say that we are here */ - checkboard(); -#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE) - rtc_init(); -#endif - timer_init(); - printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \ - CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000); - printf("SDRAM: "); - print_size(initdram(0), "\n"); - board_init_r((gd_t *) gd, 0x20000010); -} - -void board_init_r(gd_t * id, ulong dest_addr) -{ - ulong size; - extern void malloc_bin_reloc(void); - char *s, *e; - bd_t *bd; - int i; - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - bd = gd->bd; - -#if CONFIG_STAMP - /* There are some other pointer constants we must deal with */ - /* configure available FLASH banks */ - size = flash_init(); - display_flash_config(size); - flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]); - bd->bi_flashstart = CFG_FLASH_BASE; - bd->bi_flashsize = size; - bd->bi_flashoffset = 0; -#else - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; -#endif - /* initialize malloc() area */ - mem_malloc_init(); - malloc_bin_reloc(); - - /* relocate environment function pointers etc. */ - env_relocate(); - - /* board MAC address */ - s = getenv("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - - /* Initialize devices */ - devices_init(); - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - - /* Initialize from environment */ - if ((s = getenv("loadaddr")) != NULL) { - load_addr = simple_strtoul(s, NULL, 16); - } -#if (CONFIG_COMMANDS & CFG_CMD_NET) - if ((s = getenv("bootfile")) != NULL) { - copy_filename(BootFile, s, sizeof(BootFile)); - } -#endif -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - -#ifdef CONFIG_DRIVER_SMC91111 -#ifdef SHARED_RESOURCES - /* Switch to Ethernet */ - swap_to(ETHERNET); -#endif - if ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) { - printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS); - } else { - printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS); - } - -#ifdef SHARED_RESOURCES - swap_to(FLASH); -#endif -#endif -#ifdef CONFIG_SOFT_I2C - init_func_i2c(); -#endif - -#ifdef DEBUG - display_global_data(void); -#endif - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - main_loop(); - } -} - -#ifdef CONFIG_SOFT_I2C -static int init_func_i2c (void) -{ - puts ("I2C: "); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - puts ("ready\n"); - return (0); -} -#endif - -void hang(void) -{ - puts("### ERROR ### Please RESET the board ###\n"); - for (;;); -} |