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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:19:22 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:48 +0100 |
| commit | af228d8aed952d4ad5844662024b840b9e3cad90 (patch) | |
| tree | 9b4a067929c5b32a97308cc54887087c1a6394eb | |
| parent | 203d2c0097938e426fdd0ca899183334d29bef7b (diff) | |
| download | barebox-af228d8aed952d4ad5844662024b840b9e3cad90.tar.gz barebox-af228d8aed952d4ad5844662024b840b9e3cad90.tar.xz | |
PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates
Port of a Linux commit d91dfe5054d4f2c424bd70ca34fc3328ee179f20
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.
Enable write permission before updating the Class Code and Interrupt
Pin.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | drivers/pci/pcie-designware-host.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pci/pcie-designware-host.c b/drivers/pci/pcie-designware-host.c index e98560818c..b42d2ac93f 100644 --- a/drivers/pci/pcie-designware-host.c +++ b/drivers/pci/pcie-designware-host.c @@ -403,8 +403,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* Program correct class for RC */ + /* Enable write permission for the DBI read-only register */ + dw_pcie_dbi_ro_wr_en(pci); + /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + /* Better disable write permission right after the update */ + dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; |