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authorSascha Hauer <s.hauer@pengutronix.de>2019-07-12 07:10:19 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-07-12 07:10:19 +0200
commitaf66ec677c40dfaed68a124d21dd59d5f8c63381 (patch)
tree8e58a7467542269f631215fbf60637c4a974ff6f
parentf9dfe479ebacbb3efacef4525682546713b11597 (diff)
parentbc482d1ab37b8aeb8cbb0aa380df93ff6e73c9bc (diff)
downloadbarebox-af66ec677c40dfaed68a124d21dd59d5f8c63381.tar.gz
Merge branch 'for-next/zii'
-rwxr-xr-xDocumentation/boards/imx/zii-imx7d-dev/bootstrap.sh (renamed from Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh)0
-rw-r--r--Documentation/boards/imx/zii-imx7d-dev/openocd.cfg (renamed from Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg)4
-rw-r--r--Documentation/boards/imx/zii-imx7d-dev/readme.rst (renamed from Documentation/boards/imx/zii-imx7d-rpu2/readme.rst)4
-rw-r--r--Documentation/boards/imx/zii-vf610-dev/openocd.cfg301
-rw-r--r--arch/arm/boards/Makefile2
-rw-r--r--arch/arm/boards/zii-imx7d-dev/Makefile3
-rw-r--r--arch/arm/boards/zii-imx7d-dev/board.c (renamed from arch/arm/boards/zii-imx7d-rpu2/board.c)3
-rw-r--r--arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg (renamed from arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg)0
-rw-r--r--arch/arm/boards/zii-imx7d-dev/lowlevel.c108
-rw-r--r--arch/arm/boards/zii-imx7d-rpu2/Makefile2
-rw-r--r--arch/arm/boards/zii-imx7d-rpu2/lowlevel.c50
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/imx7d-zii-rmu2.dts8
-rw-r--r--arch/arm/dts/imx7d-zii-rmu2.dtsi361
-rw-r--r--arch/arm/dts/imx7d-zii-rpu2.dts608
-rw-r--r--arch/arm/dts/vf610-zii-dev-rev-b.dts45
-rw-r--r--arch/arm/dts/vf610-zii-dev-rev-c.dts45
-rw-r--r--arch/arm/mach-imx/Kconfig4
-rw-r--r--images/Makefile.imx8
19 files changed, 666 insertions, 892 deletions
diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh b/Documentation/boards/imx/zii-imx7d-dev/bootstrap.sh
index 49bab03..49bab03 100755
--- a/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh
+++ b/Documentation/boards/imx/zii-imx7d-dev/bootstrap.sh
diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg b/Documentation/boards/imx/zii-imx7d-dev/openocd.cfg
index 675832b..f971c3f 100644
--- a/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg
+++ b/Documentation/boards/imx/zii-imx7d-dev/openocd.cfg
@@ -32,7 +32,7 @@ proc disable_wdog { } {
set ddr_init_failed 0
proc check_bits_set_32 { addr mask } {
- while { [expr [mrw $addr] & $mask == 0] } { }
+ while { [expr [mrw $addr] & $mask] == 0 } { }
}
proc ddr_init { } {
@@ -132,7 +132,7 @@ proc start_barebox { } {
set MX7_DDR_BASE_ADDR 0x80000000
echo "Bootstrap: Loading Barebox"
halt
- load_image images/barebox-zii-imx7d-rpu2.img $MX7_DDR_BASE_ADDR bin
+ load_image images/barebox-zii-imx7d-dev.img $MX7_DDR_BASE_ADDR bin
arm core_state arm
echo [format "Bootstrap: Jumping to 0x%08x" $MX7_DDR_BASE_ADDR]
resume $MX7_DDR_BASE_ADDR
diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst b/Documentation/boards/imx/zii-imx7d-dev/readme.rst
index dd984ac..d47bc90 100644
--- a/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst
+++ b/Documentation/boards/imx/zii-imx7d-dev/readme.rst
@@ -21,14 +21,14 @@ follows:
.. code-block:: sh
cd barebox
- Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh
+ Documentation/boards/imx/zii-imx7d-dev/bootstrap.sh
A custom OpenOCD binary and options can be specified as follows:
.. code-block:: sh
OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \
- Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh
+ Documentation/boards/imx/zii-imx7d-dev/bootstrap.sh
Disabling DSA in Embedeed Switch
diff --git a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
index 509f9e3..222f487 100644
--- a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
+++ b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
@@ -19,6 +19,8 @@ reset_config srst_only srst_push_pull connect_deassert_srst
# set a slow default JTAG clock, can be overridden later
adapter_khz 1000
+adapter_nsrst_delay 100
+
# Source generic VF6xx target configuration
source [find target/vybrid_vf6xx.cfg]
source [find mem_helper.tcl]
@@ -26,159 +28,167 @@ source [find mem_helper.tcl]
set ddr_init_failed 0
proc check_bits_set_32 { addr mask } {
- while { [expr [mrw $addr] & $mask == 0] } { }
+ while { [expr [mrw $addr] & $mask] == 0 } { }
}
proc ddr_init { } {
echo "Bootstrap: Initializing DDR"
- mww phys 0x40048220 0x00000180
- mww phys 0x40048224 0x00000180
- mww phys 0x40048228 0x00000180
- mww phys 0x4004822c 0x00000180
- mww phys 0x40048230 0x00000180
- mww phys 0x40048234 0x00000180
- mww phys 0x40048238 0x00000180
- mww phys 0x4004823c 0x00000180
- mww phys 0x40048240 0x00000180
- mww phys 0x40048244 0x00000180
- mww phys 0x40048248 0x00000180
- mww phys 0x4004824c 0x00000180
- mww phys 0x40048250 0x00000180
- mww phys 0x40048254 0x00000180
- mww phys 0x40048258 0x00000180
- mww phys 0x4004825c 0x00000180
- mww phys 0x40048260 0x00000180
- mww phys 0x40048264 0x00000180
- mww phys 0x40048268 0x00000180
- mww phys 0x4004826c 0x00000180
- mww phys 0x40048270 0x00000180
- mww phys 0x40048274 0x00010180
- mww phys 0x40048278 0x00000180
- mww phys 0x4004827c 0x00000180
- mww phys 0x40048280 0x00000180
- mww phys 0x40048284 0x00000180
- mww phys 0x40048288 0x00000180
- mww phys 0x4004828c 0x00000180
- mww phys 0x40048290 0x00000180
- mww phys 0x40048294 0x00000180
- mww phys 0x40048298 0x00000180
- mww phys 0x4004829c 0x00000180
- mww phys 0x400482a0 0x00000180
- mww phys 0x400482a4 0x00000180
- mww phys 0x400482a8 0x00000180
- mww phys 0x400482ac 0x00000180
- mww phys 0x400482b0 0x00000180
- mww phys 0x400482b4 0x00000180
- mww phys 0x400482b8 0x00000180
- mww phys 0x400482bc 0x00000180
- mww phys 0x400482c0 0x00000180
- mww phys 0x400482c4 0x00010180
- mww phys 0x400482c8 0x00010180
- mww phys 0x400482cc 0x00000180
- mww phys 0x400482d0 0x00000180
- mww phys 0x400482d4 0x00000180
- mww phys 0x400482d8 0x00000180
- mww phys 0x4004821c 0x00000180
+ #
+ # vf610-iomux-ddr-default.imxcfg
+ #
+ mww phys 0x40048220 0x00000180 ;# wm 32 VF610_PAD_DDR_A15__DDR_A_15 VF610_DDR_PAD_CTRL
+ mww phys 0x40048224 0x00000180 ;# wm 32 VF610_PAD_DDR_A14__DDR_A_14 VF610_DDR_PAD_CTRL
+ mww phys 0x40048228 0x00000180 ;# wm 32 VF610_PAD_DDR_A13__DDR_A_13 VF610_DDR_PAD_CTRL
+ mww phys 0x4004822c 0x00000180 ;# wm 32 VF610_PAD_DDR_A12__DDR_A_12 VF610_DDR_PAD_CTRL
+ mww phys 0x40048230 0x00000180 ;# wm 32 VF610_PAD_DDR_A11__DDR_A_11 VF610_DDR_PAD_CTRL
+ mww phys 0x40048234 0x00000180 ;# wm 32 VF610_PAD_DDR_A10__DDR_A_10 VF610_DDR_PAD_CTRL
+ mww phys 0x40048238 0x00000180 ;# wm 32 VF610_PAD_DDR_A9__DDR_A_9 VF610_DDR_PAD_CTRL
+ mww phys 0x4004823c 0x00000180 ;# wm 32 VF610_PAD_DDR_A8__DDR_A_8 VF610_DDR_PAD_CTRL
+ mww phys 0x40048240 0x00000180 ;# wm 32 VF610_PAD_DDR_A7__DDR_A_7 VF610_DDR_PAD_CTRL
+ mww phys 0x40048244 0x00000180 ;# wm 32 VF610_PAD_DDR_A6__DDR_A_6 VF610_DDR_PAD_CTRL
+ mww phys 0x40048248 0x00000180 ;# wm 32 VF610_PAD_DDR_A5__DDR_A_5 VF610_DDR_PAD_CTRL
+ mww phys 0x4004824c 0x00000180 ;# wm 32 VF610_PAD_DDR_A4__DDR_A_4 VF610_DDR_PAD_CTRL
+ mww phys 0x40048250 0x00000180 ;# wm 32 VF610_PAD_DDR_A3__DDR_A_3 VF610_DDR_PAD_CTRL
+ mww phys 0x40048254 0x00000180 ;# wm 32 VF610_PAD_DDR_A2__DDR_A_2 VF610_DDR_PAD_CTRL
+ mww phys 0x40048258 0x00000180 ;# wm 32 VF610_PAD_DDR_A1__DDR_A_1 VF610_DDR_PAD_CTRL
+ mww phys 0x4004825c 0x00000180 ;# wm 32 VF610_PAD_DDR_A0__DDR_A_0 VF610_DDR_PAD_CTRL
+ mww phys 0x40048260 0x00000180 ;# wm 32 VF610_PAD_DDR_BA2__DDR_BA_2 VF610_DDR_PAD_CTRL
+ mww phys 0x40048264 0x00000180 ;# wm 32 VF610_PAD_DDR_BA1__DDR_BA_1 VF610_DDR_PAD_CTRL
+ mww phys 0x40048268 0x00000180 ;# wm 32 VF610_PAD_DDR_BA0__DDR_BA_0 VF610_DDR_PAD_CTRL
+ mww phys 0x4004826c 0x00000180 ;# wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B VF610_DDR_PAD_CTRL
+ mww phys 0x40048270 0x00000180 ;# wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0 VF610_DDR_PAD_CTRL
+ mww phys 0x40048274 0x00010180 ;# wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0 VF610_DDR_PAD_CTRL_1
+ mww phys 0x40048278 0x00000180 ;# wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0 VF610_DDR_PAD_CTRL
+ mww phys 0x4004827c 0x00000180 ;# wm 32 VF610_PAD_DDR_D15__DDR_D_15 VF610_DDR_PAD_CTRL
+ mww phys 0x40048280 0x00000180 ;# wm 32 VF610_PAD_DDR_D14__DDR_D_14 VF610_DDR_PAD_CTRL
+ mww phys 0x40048284 0x00000180 ;# wm 32 VF610_PAD_DDR_D13__DDR_D_13 VF610_DDR_PAD_CTRL
+ mww phys 0x40048288 0x00000180 ;# wm 32 VF610_PAD_DDR_D12__DDR_D_12 VF610_DDR_PAD_CTRL
+ mww phys 0x4004828c 0x00000180 ;# wm 32 VF610_PAD_DDR_D11__DDR_D_11 VF610_DDR_PAD_CTRL
+ mww phys 0x40048290 0x00000180 ;# wm 32 VF610_PAD_DDR_D10__DDR_D_10 VF610_DDR_PAD_CTRL
+ mww phys 0x40048294 0x00000180 ;# wm 32 VF610_PAD_DDR_D9__DDR_D_9 VF610_DDR_PAD_CTRL
+ mww phys 0x40048298 0x00000180 ;# wm 32 VF610_PAD_DDR_D8__DDR_D_8 VF610_DDR_PAD_CTRL
+ mww phys 0x4004829c 0x00000180 ;# wm 32 VF610_PAD_DDR_D7__DDR_D_7 VF610_DDR_PAD_CTRL
+ mww phys 0x400482a0 0x00000180 ;# wm 32 VF610_PAD_DDR_D6__DDR_D_6 VF610_DDR_PAD_CTRL
+ mww phys 0x400482a4 0x00000180 ;# wm 32 VF610_PAD_DDR_D5__DDR_D_5 VF610_DDR_PAD_CTRL
+ mww phys 0x400482a8 0x00000180 ;# wm 32 VF610_PAD_DDR_D4__DDR_D_4 VF610_DDR_PAD_CTRL
+ mww phys 0x400482ac 0x00000180 ;# wm 32 VF610_PAD_DDR_D3__DDR_D_3 VF610_DDR_PAD_CTRL
+ mww phys 0x400482b0 0x00000180 ;# wm 32 VF610_PAD_DDR_D2__DDR_D_2 VF610_DDR_PAD_CTRL
+ mww phys 0x400482b4 0x00000180 ;# wm 32 VF610_PAD_DDR_D1__DDR_D_1 VF610_DDR_PAD_CTRL
+ mww phys 0x400482b8 0x00000180 ;# wm 32 VF610_PAD_DDR_D0__DDR_D_0 VF610_DDR_PAD_CTRL
+ mww phys 0x400482bc 0x00000180 ;# wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1 VF610_DDR_PAD_CTRL
+ mww phys 0x400482c0 0x00000180 ;# wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0 VF610_DDR_PAD_CTRL
+ mww phys 0x400482c4 0x00010180 ;# wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1 VF610_DDR_PAD_CTRL_1
+ mww phys 0x400482c8 0x00010180 ;# wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0 VF610_DDR_PAD_CTRL_1
+ mww phys 0x400482cc 0x00000180 ;# wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B VF610_DDR_PAD_CTRL
+ mww phys 0x400482d0 0x00000180 ;# wm 32 VF610_PAD_DDR_WE__DDR_WE_B VF610_DDR_PAD_CTRL
+ mww phys 0x400482d4 0x00000180 ;# wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0 VF610_DDR_PAD_CTRL
+ mww phys 0x400482d8 0x00000180 ;# wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1 VF610_DDR_PAD_CTRL
+ mww phys 0x4004821c 0x00000180 ;# wm 32 VF610_PAD_DDR_RESETB VF610_DDR_PAD_CTRL
+
+ mww phys 0x400482dc 0x00000180 ;# wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL
+ mww phys 0x400482e0 0x00000180 ;# wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
+
+ #
+ # vf610-ddr-cr-default.imxcfg
+ #
+ mww phys 0x400ae000 0x00000600 ;# wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3
+ mww phys 0x400ae008 0x00000005 ;# wm 32 DDRMC_CR02 0x00000005
+ mww phys 0x400ae028 0x00013880 ;# wm 32 DDRMC_CR10 0x00013880
+ mww phys 0x400ae02c 0x00030d40 ;# wm 32 DDRMC_CR11 0x00030d40
+ mww phys 0x400ae030 0x0000050c ;# wm 32 DDRMC_CR12 0x0000050c
+ mww phys 0x400ae034 0x15040400 ;# wm 32 DDRMC_CR13 0x15040400
+ mww phys 0x400ae038 0x1406040f ;# wm 32 DDRMC_CR14 0x1406040f
+ mww phys 0x400ae040 0x04040000 ;# wm 32 DDRMC_CR16 0x04040000
+ mww phys 0x400ae044 0x006db00c ;# wm 32 DDRMC_CR17 0x006db00c
+ mww phys 0x400ae048 0x00000403 ;# wm 32 DDRMC_CR18 0x00000403
+ mww phys 0x400ae050 0x01000000 ;# wm 32 DDRMC_CR20 0x01000000
+ mww phys 0x400ae054 0x00060001 ;# wm 32 DDRMC_CR21 0x00060001
+ mww phys 0x400ae058 0x000c0000 ;# wm 32 DDRMC_CR22 0x000c0000
+ mww phys 0x400ae05c 0x03000200 ;# wm 32 DDRMC_CR23 0x03000200
+ mww phys 0x400ae060 0x00000006 ;# wm 32 DDRMC_CR24 0x00000006
+ mww phys 0x400ae064 0x00010000 ;# wm 32 DDRMC_CR25 0x00010000
+ mww phys 0x400ae068 0x0c30002c ;# wm 32 DDRMC_CR26 0x0c30002c
+ mww phys 0x400ae070 0x00000000 ;# wm 32 DDRMC_CR28 0x00000000
+ mww phys 0x400ae074 0x00000003 ;# wm 32 DDRMC_CR29 0x00000003
+ mww phys 0x400ae078 0x0000000a ;# wm 32 DDRMC_CR30 0x0000000a
+ mww phys 0x400ae07c 0x00300200 ;# wm 32 DDRMC_CR31 0x00300200
+ mww phys 0x400ae084 0x00010000 ;# wm 32 DDRMC_CR33 0x00010000
+ mww phys 0x400ae088 0x00050500 ;# wm 32 DDRMC_CR34 0x00050500
+ mww phys 0x400ae098 0x00000000 ;# wm 32 DDRMC_CR38 0x00000000
+ mww phys 0x400ae09c 0x04001002 ;# wm 32 DDRMC_CR39 0x04001002
+ mww phys 0x400ae0a4 0x00000001 ;# wm 32 DDRMC_CR41 0x00000001
+ mww phys 0x400ae0c0 0x00460420 ;# wm 32 DDRMC_CR48 0x00460420
+ mww phys 0x400ae108 0x01000200 ;# wm 32 DDRMC_CR66 0x01000200
+ mww phys 0x400ae10c 0x00000040 ;# wm 32 DDRMC_CR67 0x00000040
+ mww phys 0x400ae114 0x00000200 ;# wm 32 DDRMC_CR69 0x00000200
+ mww phys 0x400ae118 0x00000040 ;# wm 32 DDRMC_CR70 0x00000040
+ mww phys 0x400ae120 0x00000000 ;# wm 32 DDRMC_CR72 0x00000000
+ mww phys 0x400ae124 0x0a010300 ;# wm 32 DDRMC_CR73 0x0a010300
+ mww phys 0x400ae128 0x01014040 ;# wm 32 DDRMC_CR74 0x01014040
+ mww phys 0x400ae12c 0x01010101 ;# wm 32 DDRMC_CR75 0x01010101
+ mww phys 0x400ae130 0x03030100 ;# wm 32 DDRMC_CR76 0x03030100
+ mww phys 0x400ae134 0x01000101 ;# wm 32 DDRMC_CR77 0x01000101
+ mww phys 0x400ae138 0x0700000c ;# wm 32 DDRMC_CR78 0x0700000c
+ mww phys 0x400ae13c 0x00000000 ;# wm 32 DDRMC_CR79 0x00000000
+ mww phys 0x400ae148 0x10000000 ;# wm 32 DDRMC_CR82 0x10000000
+ mww phys 0x400ae15c 0x01000000 ;# wm 32 DDRMC_CR87 0x01000000
+ mww phys 0x400ae160 0x00040000 ;# wm 32 DDRMC_CR88 0x00040000
+ mww phys 0x400ae164 0x00000002 ;# wm 32 DDRMC_CR89 0x00000002
+ mww phys 0x400ae16c 0x00020000 ;# wm 32 DDRMC_CR91 0x00020000
+ mww phys 0x400ae180 0x00002819 ;# wm 32 DDRMC_CR96 0x00002819
+ mww phys 0x400ae1d4 0x00000000 ;# wm 32 DDRMC_CR117 0x00000000
+ mww phys 0x400ae1d8 0x01010000 ;# wm 32 DDRMC_CR118 0x01010000
+ mww phys 0x400ae1e0 0x02020000 ;# wm 32 DDRMC_CR120 0x02020000
+ mww phys 0x400ae1e4 0x00000202 ;# wm 32 DDRMC_CR121 0x00000202
+ mww phys 0x400ae1e8 0x01010064 ;# wm 32 DDRMC_CR122 0x01010064
+ mww phys 0x400ae1ec 0x00010101 ;# wm 32 DDRMC_CR123 0x00010101
+ mww phys 0x400ae1f0 0x00000064 ;# wm 32 DDRMC_CR124 0x00000064
+ mww phys 0x400ae1f8 0x00000800 ;# wm 32 DDRMC_CR126 0x00000800
+ mww phys 0x400ae210 0x00000506 ;# wm 32 DDRMC_CR132 0x00000506
+ mww phys 0x400ae224 0x00020000 ;# wm 32 DDRMC_CR137 0x00020000
+ mww phys 0x400ae228 0x01000100 ;# wm 32 DDRMC_CR138 0x01000100
+ mww phys 0x400ae22c 0x04070303 ;# wm 32 DDRMC_CR154 0x682c4000
+ mww phys 0x400ae230 0x00000040 ;# wm 32 DDRMC_CR155 0x00000009
+ mww phys 0x400ae23c 0x06000080 ;# wm 32 DDRMC_CR158 0x00000006
+ mww phys 0x400ae240 0x04070303 ;# wm 32 DDRMC_CR161 0x00010606
+
+ #
+ # flash-header-zii-vf610-dev.imxcfg
+ #
+ mww phys 0x400ae068 0x0c300068 ;# wm 32 DDRMC_CR26 0x0c300068
+ mww phys 0x400ae07c 0x006c0200 ;# wm 32 DDRMC_CR31 0x006c0200
+ mww phys 0x400ae124 0x0a010100 ;# wm 32 DDRMC_CR73 0x0a010100
+
+ #
+ # vf610-ddr-phy-default.imxcfg
+ #
+ mww phys 0x400ae400 0x00002613 ;# wm 32 DDRMC_PHY00 DDRMC_PHY_DQ_TIMING
+ mww phys 0x400ae440 0x00002613 ;# wm 32 DDRMC_PHY16 DDRMC_PHY_DQ_TIMING
+ mww phys 0x400ae480 0x00002613 ;# wm 32 DDRMC_PHY32 DDRMC_PHY_DQ_TIMING
+
+ mww phys 0x400ae404 0x00002615 ;# wm 32 DDRMC_PHY01 DDRMC_PHY_DQS_TIMING
+ mww phys 0x400ae444 0x00002615 ;# wm 32 DDRMC_PHY17 DDRMC_PHY_DQS_TIMING
+
+ mww phys 0x400ae408 0x00210000 ;# wm 32 DDRMC_PHY02 DDRMC_PHY_CTRL
+ mww phys 0x400ae448 0x00210000 ;# wm 32 DDRMC_PHY18 DDRMC_PHY_CTRL
+ mww phys 0x400ae488 0x00210000 ;# wm 32 DDRMC_PHY34 DDRMC_PHY_CTRL
+
+ mww phys 0x400ae40c 0x0001012a ;# wm 32 DDRMC_PHY03 DDRMC_PHY_MASTER_CTRL
+ mww phys 0x400ae44c 0x0001012a ;# wm 32 DDRMC_PHY19 DDRMC_PHY_MASTER_CTRL
+ mww phys 0x400ae48c 0x0001012a ;# wm 32 DDRMC_PHY35 DDRMC_PHY_MASTER_CTRL
- mww phys 0x400482dc 0x00000180
- mww phys 0x400482e0 0x00000180
+ mww phys 0x400ae410 0x00002400 ;# wm 32 DDRMC_PHY04 DDRMC_PHY_SLAVE_CTRL
+ mww phys 0x400ae450 0x00002400 ;# wm 32 DDRMC_PHY20 DDRMC_PHY_SLAVE_CTRL
+ mww phys 0x400ae490 0x00002400 ;# wm 32 DDRMC_PHY36 DDRMC_PHY_SLAVE_CTRL
- mww phys 0x400ae000 0x00000600
- mww phys 0x400ae008 0x00000005
- mww phys 0x400ae028 0x00013880
- mww phys 0x400ae02c 0x00030d40
- mww phys 0x400ae030 0x0000050c
- mww phys 0x400ae034 0x15040400
- mww phys 0x400ae038 0x1406040f
- mww phys 0x400ae040 0x04040000
- mww phys 0x400ae044 0x006db00c
- mww phys 0x400ae048 0x00000403
- mww phys 0x400ae050 0x01000000
- mww phys 0x400ae054 0x00060001
- mww phys 0x400ae058 0x000c0000
- mww phys 0x400ae05c 0x03000200
- mww phys 0x400ae060 0x00000006
- mww phys 0x400ae064 0x00010000
- mww phys 0x400ae068 0x0c300068
- mww phys 0x400ae070 0x00000000
- mww phys 0x400ae074 0x00000003
- mww phys 0x400ae078 0x0000000a
- mww phys 0x400ae07c 0x006c0200
- mww phys 0x400ae084 0x00010000
- mww phys 0x400ae088 0x00050500
- mww phys 0x400ae098 0x00000000
- mww phys 0x400ae09c 0x04001002
- mww phys 0x400ae0a4 0x00000001
- mww phys 0x400ae0c0 0x00460420
- mww phys 0x400ae108 0x01000200
- mww phys 0x400ae10c 0x00000040
- mww phys 0x400ae114 0x00000200
- mww phys 0x400ae118 0x00000040
- mww phys 0x400ae120 0x00000000
- mww phys 0x400ae124 0x0a010100
- mww phys 0x400ae128 0x01014040
- mww phys 0x400ae12c 0x01010101
- mww phys 0x400ae130 0x03030100
- mww phys 0x400ae134 0x01000101
- mww phys 0x400ae138 0x0700000c
- mww phys 0x400ae13c 0x00000000
- mww phys 0x400ae148 0x10000000
- mww phys 0x400ae15c 0x01000000
- mww phys 0x400ae160 0x00040000
- mww phys 0x400ae164 0x00000002
- mww phys 0x400ae16c 0x00020000
- mww phys 0x400ae180 0x00002819
- mww phys 0x400ae184 0x01000000
- mww phys 0x400ae188 0x00000000
- mww phys 0x400ae18c 0x00000000
- mww phys 0x400ae198 0x00010100
- mww phys 0x400ae1a4 0x00000000
- mww phys 0x400ae1a8 0x00000004
- mww phys 0x400ae1b8 0x00040000
- mww phys 0x400ae1d4 0x00000000
- mww phys 0x400ae1d8 0x01010000
- mww phys 0x400ae1e0 0x02020000
- mww phys 0x400ae1e4 0x00000202
- mww phys 0x400ae1e8 0x01010064
- mww phys 0x400ae1ec 0x00010101
- mww phys 0x400ae1f0 0x00000064
- mww phys 0x400ae1f8 0x00000800
- mww phys 0x400ae210 0x00000506
- mww phys 0x400ae224 0x00020000
- mww phys 0x400ae228 0x01000100
- mww phys 0x400ae22c 0x04070303
- mww phys 0x400ae230 0x00000040
- mww phys 0x400ae23c 0x06000080
- mww phys 0x400ae240 0x04070303
- mww phys 0x400ae244 0x00000040
- mww phys 0x400ae248 0x00000040
- mww phys 0x400ae24c 0x000f0000
- mww phys 0x400ae250 0x000f0000
- mww phys 0x400ae25c 0x00000101
- mww phys 0x400ae268 0x682c4000
- mww phys 0x400ae26c 0x00000081
- mww phys 0x400ae278 0x00000006
- mww phys 0x400ae284 0x00010606
+ mww phys 0x400ae4c4 0x00000000 ;# wm 32 DDRMC_PHY49 DDRMC_PHY_OFF
+ mww phys 0x400ae4c8 0x00001100 ;# wm 32 DDRMC_PHY50 DDRMC_PHY50_DDR3_MODE_EN_SW_HALF_CYCLE
+ mww phys 0x400ae4d0 0x00010101 ;# wm 32 DDRMC_PHY52 DDRMC_PHY_PROC_PAD_ODT
- mww phys 0x400ae400 0x00002613
- mww phys 0x400ae440 0x00002613
- mww phys 0x400ae404 0x00002615
- mww phys 0x400ae444 0x00002615
- mww phys 0x400ae408 0x00210000
- mww phys 0x400ae448 0x00210000
- mww phys 0x400ae488 0x00210000
- mww phys 0x400ae40c 0x0001012a
- mww phys 0x400ae44c 0x0001012a
- mww phys 0x400ae48c 0x0001012a
- mww phys 0x400ae410 0x00002400
- mww phys 0x400ae450 0x00002400
- mww phys 0x400ae490 0x00002400
- mww phys 0x400ae4c4 0x00000000
- mww phys 0x400ae4c8 0x00001100
- mww phys 0x400ae4d0 0x00010101
+ mww phys 0x400ae000 0x00000601 ;# wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START
- mww phys 0x400ae000 0x00000601
+ check_bits_set_32 0x400ae140 0x100
}
proc clock_init { } {
@@ -186,8 +196,7 @@ proc clock_init { } {
#
# This code assumes that debugger would be unable to prevent
# MaskROM initialization code from running before halting the
- # processor. TODO: Port the initial clock settings as
- # specified in TRM
+ # processor.
#
# Ungate all of the peripheral clocks
#
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index bdf78d0..a814ab8 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -164,7 +164,7 @@ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/
obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/
obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/
obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/
-obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/
+obj-$(CONFIG_MACH_ZII_IMX7D_DEV) += zii-imx7d-dev/
obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/
obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/
obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
diff --git a/arch/arm/boards/zii-imx7d-dev/Makefile b/arch/arm/boards/zii-imx7d-dev/Makefile
new file mode 100644
index 0000000..e1baed1
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-dev/Makefile
@@ -0,0 +1,3 @@
+CFLAGS_pbl-lowlevel.o := -fno-tree-switch-conversion -fno-jump-tables
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/zii-imx7d-rpu2/board.c b/arch/arm/boards/zii-imx7d-dev/board.c
index 0a99976..89f0515 100644
--- a/arch/arm/boards/zii-imx7d-rpu2/board.c
+++ b/arch/arm/boards/zii-imx7d-dev/board.c
@@ -33,7 +33,8 @@ static void zii_imx7d_rpu2_init_fec(void)
static int zii_imx7d_rpu2_coredevices_init(void)
{
- if (!of_machine_is_compatible("zii,imx7d-zii-rpu2"))
+ if (!of_machine_is_compatible("zii,imx7d-zii-rpu2") &&
+ !of_machine_is_compatible("zii,imx7d-rmu2"))
return 0;
zii_imx7d_rpu2_init_fec();
diff --git a/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
index 46f3d95..46f3d95 100644
--- a/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
+++ b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
new file mode 100644
index 0000000..3ad4940
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovation
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#include <debug_ll.h>
+#include <io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx7-ccm-regs.h>
+#include <mach/iomux-mx7.h>
+#include <mach/debug_ll.h>
+#include <asm/cache.h>
+#include <mach/esdctl.h>
+
+extern char __dtb_imx7d_zii_rpu2_start[];
+extern char __dtb_imx7d_zii_rmu2_start[];
+
+static inline void setup_uart(void)
+{
+ void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
+ void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR);
+
+ writel(CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2));
+ writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M,
+ ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT));
+ writel(CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + CCM_CCGRn_SET(CCM_CCGR_UART2));
+
+ mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
+
+ imx7_uart_setup_ll();
+
+ putc_ll('>');
+}
+
+enum zii_platform_imx7d_type {
+ ZII_PLATFORM_IMX7D_RPU2 = 0b0000,
+ ZII_PLATFORM_IMX7D_RMU2 = 0b1000,
+};
+
+static unsigned int get_system_type(void)
+{
+#define GPIO_DR 0x000
+#define GPIO_GDIR 0x004
+#define SYSTEM_TYPE GENMASK(15, 12)
+
+ u32 gdir, dr;
+ void __iomem *gpio2 = IOMEM(MX7_GPIO2_BASE_ADDR);
+ void __iomem *iomuxbase = IOMEM(MX7_IOMUXC_BASE_ADDR);
+
+ /*
+ * System type is encoded as a 4-bit number specified by the
+ * following pins (pulled up or down with resistors on the
+ * board).
+ */
+ imx_setup_pad(iomuxbase, MX7D_PAD_EPDC_DATA12__GPIO2_IO12);
+ imx_setup_pad(iomuxbase, MX7D_PAD_EPDC_DATA13__GPIO2_IO13);
+ imx_setup_pad(iomuxbase, MX7D_PAD_EPDC_DATA14__GPIO2_IO14);
+ imx_setup_pad(iomuxbase, MX7D_PAD_EPDC_DATA15__GPIO2_IO15);
+
+ gdir = readl(gpio2 + GPIO_GDIR);
+ gdir &= ~SYSTEM_TYPE;
+ writel(gdir, gpio2 + GPIO_GDIR);
+
+ dr = readl(gpio2 + GPIO_DR);
+
+ return FIELD_GET(SYSTEM_TYPE, dr);
+}
+
+ENTRY_FUNCTION(start_zii_imx7d_dev, r0, r1, r2)
+{
+ void *fdt;
+ const unsigned int system_type = get_system_type();
+
+ imx7_cpu_lowlevel_init();
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ setup_uart();
+
+ switch (system_type) {
+ default:
+ if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+ relocate_to_current_adr();
+ setup_c();
+ puts_ll("\n*********************************\n");
+ puts_ll("* Unknown system type: ");
+ puthex_ll(system_type);
+ puts_ll("\n* Assuming RPU2\n");
+ puts_ll("*********************************\n");
+ }
+ /* FALLTHROUGH */
+ case ZII_PLATFORM_IMX7D_RPU2:
+ fdt = __dtb_imx7d_zii_rpu2_start;
+ break;
+ case ZII_PLATFORM_IMX7D_RMU2:
+ fdt = __dtb_imx7d_zii_rmu2_start;
+ break;
+ }
+
+ imx7d_barebox_entry(fdt + get_runtime_offset());
+}
diff --git a/arch/arm/boards/zii-imx7d-rpu2/Makefile b/arch/arm/boards/zii-imx7d-rpu2/Makefile
deleted file mode 100644
index 01c7a25..0000000
--- a/arch/arm/boards/zii-imx7d-rpu2/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y += board.o
-lwl-y += lowlevel.o
diff --git a/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c b/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
deleted file mode 100644
index 1eeab7d..0000000
--- a/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/*
- * Copyright (C) 2018 Zodiac Inflight Innovation
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- */
-
-#include <debug_ll.h>
-#include <io.h>
-#include <common.h>
-#include <linux/sizes.h>
-#include <mach/generic.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/imx7-ccm-regs.h>
-#include <mach/iomux-mx7.h>
-#include <mach/debug_ll.h>
-#include <asm/cache.h>
-#include <mach/esdctl.h>
-
-extern char __dtb_imx7d_zii_rpu2_start[];
-
-static inline void setup_uart(void)
-{
- void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
- void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR);
-
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2));
- writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M,
- ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT));
- writel(CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + CCM_CCGRn_SET(CCM_CCGR_UART2));
-
- mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
-
- imx7_uart_setup_ll();
-
- putc_ll('>');
-}
-
-ENTRY_FUNCTION(start_zii_imx7d_rpu2, r0, r1, r2)
-{
- imx7_cpu_lowlevel_init();
-
- if (IS_ENABLED(CONFIG_DEBUG_LL))
- setup_uart();
-
- imx7d_barebox_entry(__dtb_imx7d_zii_rpu2_start + get_runtime_offset());
-}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 87ddc57..957b329 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -136,7 +136,7 @@ pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
pbl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
-pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
+pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_DEV) += imx7d-zii-rpu2.dtb.o imx7d-zii-rmu2.dtb.o
pbl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
pbl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
pbl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
diff --git a/arch/arm/dts/imx7d-zii-rmu2.dts b/arch/arm/dts/imx7d-zii-rmu2.dts
new file mode 100644
index 0000000..1d0d631
--- /dev/null
+++ b/arch/arm/dts/imx7d-zii-rmu2.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+#include "imx7d-zii-rmu2.dtsi"
+#include "imx7d-ddrc.dtsi"
diff --git a/arch/arm/dts/imx7d-zii-rmu2.dtsi b/arch/arm/dts/imx7d-zii-rmu2.dtsi
new file mode 100644
index 0000000..7b36b1c
--- /dev/null
+++ b/arch/arm/dts/imx7d-zii-rmu2.dtsi
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device tree file for ZII's RMU2 board
+ *
+ * RMU - Remote Modem Unit
+ *
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+#include <dt-bindings/thermal/thermal.h>
+#include <arm/imx7d.dtsi>
+
+/ {
+ model = "ZII RMU2 Board";
+ compatible = "zii,imx7d-rmu2", "fsl,imx7d";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_leds_debug>;
+ pinctrl-names = "default";
+
+ debug {
+ label = "zii:green:debug1";
+ gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii";
+ phy-handle = <&fec1_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fec1_phy: phy@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1_phy_reset>,
+ <&pinctrl_enet1_phy_interrupt>;
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+
+ eeprom@a3 {
+ compatible = "zii,rave-sp-eeprom";
+ reg = <0xa3 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ zii,eeprom-name = "main-eeprom";
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ no-1-8-v;
+ no-sdio;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
+ MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
+ MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
+ MX7D_PAD_SD2_WP__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ >;
+ };
+
+ pinctrl_enet1_phy_reset: enet1phyresetgrp {
+ fsl,pins = <
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
+
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_leds_debug: debuggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
+ >;
+ };
+
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
+ MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
+ MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
+ fsl,phy = <
+ MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts
index 24a6d40..f8d6e89 100644
--- a/arch/arm/dts/imx7d-zii-rpu2.dts
+++ b/arch/arm/dts/imx7d-zii-rpu2.dts
@@ -3,19 +3,17 @@
/*
* Copyright (C) 2018 Zodiac Inflight Innovations
*/
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <arm/imx7d.dtsi>
+#include <arm/imx7d-zii-rpu2.dts>
#include "imx7d-ddrc.dtsi"
/ {
- model = "ZII RPU2 Board";
- compatible = "zii,imx7d-zii-rpu2","fsl,imx7d";
-
chosen {
+ /*
+ * Kernel DTS incorrectly specifies stdout-path as
+ * &uart1, this can be removed once the fix trickles
+ * down
+ */
stdout-path = &uart2;
};
@@ -25,598 +23,6 @@
* the switch shared DT node with it, so we use that
* fact to create a desirable naming
*/
- switch-eeprom = &switch0;
+ switch-eeprom = &switch;
};
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pinctrl_leds_debug>;
- pinctrl-names = "default";
-
- debug {
- label = "zii:green:debug1";
- gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_sd1_vmmc: regulator@3 {
- compatible = "regulator-fixed";
- regulator-name = "VDD_SD1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- enable-active-high;
- };
-
- reg_can1_3v3: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "can1-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- reg_can2_3v3: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "can2-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
-
- reg_vref_1v8: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "vref-1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- wlreg_on: fixedregulator@100 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "wlreg_on";
- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <100>;
- enable-active-high;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "GEN_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_5p0v_main: regulator-5p0v-main {
- compatible = "regulator-fixed";
- regulator-name = "5V_MAIN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
- };
-};
-
-&adc1 {
- vref-supply = <&reg_vref_1v8>;
- status = "okay";
-};
-
-&adc2 {
- vref-supply = <&reg_vref_1v8>;
- status = "okay";
-};
-
-&cpu0 {
- arm-supply = <&sw1a_reg>;
};
-
-&clks {
- assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
- assigned-clock-rates = <884736000>;
-};
-
-&ecspi1 {
- fsl,spi-num-chipselects = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
-
- nor_flash: nor-flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "barebox";
- reg = <0x0 0xc0000>;
- };
-
- partition@c0000 {
- label = "barebox-environment";
- reg = <0xc0000 0x40000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
- <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
- assigned-clock-rates = <0>, <100000000>;
- phy-mode = "rgmii-id";
- phy-handle = <&port_fec1>;
- status = "okay";
-
- mdio1: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- switch0: switch0@0 {
- compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- eeprom-length = <512>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- label = "eth_cu_1000_1";
- };
- port@1 {
- reg = <1>;
- label = "eth_cu_1000_2";
- };
-
- port@2 {
- reg = <2>;
- label = "pic";
-
- fixed-link {
- speed = <100>;
- full-duplex;
- };
- };
-
- port_fec1: port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&fec1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port_fec2: port@6 {
- reg = <6>;
- label = "data";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
- };
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2>;
- assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
- <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
- assigned-clock-rates = <0>, <100000000>;
- phy-mode = "rgmii-id";
- phy-handle = <&port_fec1>;
- fsl,magic-packet;
- status = "okay";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- nameplate_eeprom: at24c04@50 {
- compatible = "atmel,24c04";
- #address-cells=<1>;
- #size-cells=<1>;
- reg = <0x50>;
- };
-
- sandbox_eeprom: at24c04@52 {
- compatible = "atmel,24c04";
- reg = <0x52>;
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- pfuze3000@08 {
- compatible = "fsl,pfuze3000";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1a {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw1c_reg: sw1b {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1475000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3a_reg: sw3 {
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1650000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- vgen1_reg: vldo1 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen2_reg: vldo2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-always-on;
- };
-
- vgen3_reg: vccsd {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen4_reg: v33 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen5_reg: vldo3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vldo4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&sdma {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
- assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
- status = "okay";
-
- rave-sp {
- compatible = "zii,rave-sp-rdu2";
- current-speed = <1000000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- watchdog {
- compatible = "zii,rave-sp-watchdog";
- nvmem-cells = <&boot_source>;
- nvmem-cell-names = "boot-source";
- };
-
- eeprom@a3 {
- compatible = "zii,rave-sp-eeprom";
- reg = <0xa3 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- zii,eeprom-name = "main-eeprom";
-
- boot_source: boot-source@83 {
- reg = <0x83 1>;
- };
- };
- };
-};
-
-&usbotg1 {
- vbus-supply = <&reg_usb_otg1_vbus>;
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usbotg2 {
- vbus-supply = <&reg_usb_otg2_vbus>;
- dr_mode = "host";
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- keep-power-in-suspend;
- bus-width = <4>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- bus-width = <8>;
- non-removable;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
-};
-
-&wdog1 {
- fsl,wdog_b;
-};
-
-
-&iomuxc {
- pinctrl_leds_debug: debuggrp {
- fsl,pins = <
- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 /* HB_LED */
- >;
- };
-
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
- MX7D_PAD_SD2_WP__ENET1_MDC 0x3
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
- >;
- };
-
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
- MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f
- MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f
- MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f
- MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
- MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f
- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
- MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
- MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x59
- MX7D_PAD_SD1_CLK__SD1_CLK 0x19
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x59
- MX7D_PAD_SD3_CLK__SD3_CLK 0x19
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
- MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
- >;
- };
-};
-
diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts
index ac0807c..c90af91 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts
@@ -1,45 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
/*
* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <arm/vf610-zii-dev-rev-b.dts>
@@ -49,6 +11,9 @@
/ {
spi0 {
m25p128@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
partition@0 {
label = "bootloader";
reg = <0x0 0x100000>;
diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts
index c6341a0..ecec0b1 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts
@@ -1,45 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
/*
* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <arm/vf610-zii-dev-rev-c.dts>
@@ -60,6 +22,9 @@
&dspi0 {
m25p128@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
partition@0 {
label = "bootloader";
reg = <0x0 0x100000>;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 6a6aab6..b9374fe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -461,8 +461,8 @@ config MACH_ZII_VF610_DEV
select ARCH_VF610
select CLKDEV_LOOKUP
-config MACH_ZII_IMX7D_RPU2
- bool "ZII i.MX7D RPU2"
+config MACH_ZII_IMX7D_DEV
+ bool "ZII i.MX7D based devices"
select ARCH_IMX7
config MACH_PHYTEC_PHYCORE_IMX7
diff --git a/images/Makefile.imx b/images/Makefile.imx
index a287c11..42c194b 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -566,10 +566,10 @@ CFG_start_imx7s_element14_warp7.pblb.imximg = $(board)/element14-warp7/flash-hea
FILE_barebox-element14-imx7s-warp7.img = start_imx7s_element14_warp7.pblb.imximg
image-$(CONFIG_MACH_WARP7) += barebox-element14-imx7s-warp7.img
-pblb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += start_zii_imx7d_rpu2
-CFG_start_zii_imx7d_rpu2.pblb.imximg = $(board)/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
-FILE_barebox-zii-imx7d-rpu2.img = start_zii_imx7d_rpu2.pblb.imximg
-image-$(CONFIG_MACH_ZII_IMX7D_RPU2) += barebox-zii-imx7d-rpu2.img
+pblb-$(CONFIG_MACH_ZII_IMX7D_DEV) += start_zii_imx7d_dev
+CFG_start_zii_imx7d_dev.pblb.imximg = $(board)/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg
+FILE_barebox-zii-imx7d-dev.img = start_zii_imx7d_dev.pblb.imximg
+image-$(CONFIG_MACH_ZII_IMX7D_DEV) += barebox-zii-imx7d-dev.img
# ----------------------- i.MX8mq based boards --------------------------
pblb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk