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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2022-08-26 08:49:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-30 11:16:45 +0200 |
| commit | ba741e6b6cec471010d8f5eb40e651b4698a5c47 (patch) | |
| tree | cdb9466e392323090dba4e31983e22dbe19c112f | |
| parent | 319d017e4cdbd8d9c8fc9ca8c9f28108c7e47659 (diff) | |
| download | barebox-ba741e6b6cec471010d8f5eb40e651b4698a5c47.tar.gz barebox-ba741e6b6cec471010d8f5eb40e651b4698a5c47.tar.xz | |
ARM: socfpga: add Arria10-specific errata init
The Cortex A9 on the Arria10 has multiple known errata.
Enable at least the currently supported ones in barebox.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20220826064956.507125-2-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/lowlevel.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/cpu_init.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/init.h | 8 |
4 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c index 9f2d66a6bc..e0d15c84a4 100644 --- a/arch/arm/boards/enclustra-aa1/lowlevel.c +++ b/arch/arm/boards/enclustra-aa1/lowlevel.c @@ -19,6 +19,7 @@ #include "pll-config-arria10.c" #include "pinmux-config-arria10.c" #include <mach/generic.h> +#include <mach/init.h> #define BAREBOX_PART 0 // the bitstream is located in the second partition in the partition table @@ -40,6 +41,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2) int bitstream = 0; arm_cpu_lowlevel_init(); + arria10_cpu_lowlevel_init(); relocate_to_current_adr(); diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 935270bfad..008dbc3887 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -3,6 +3,7 @@ pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o +lwl-y += cpu_init.o pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-xload.o \ arria10-xload-emmc.o diff --git a/arch/arm/mach-socfpga/cpu_init.c b/arch/arm/mach-socfpga/cpu_init.c new file mode 100644 index 0000000000..1e0df1f6a5 --- /dev/null +++ b/arch/arm/mach-socfpga/cpu_init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/errata.h> +#include <mach/init.h> + +void arria10_cpu_lowlevel_init(void) +{ + enable_arm_errata_794072_war(); + enable_arm_errata_845369_war(); +} diff --git a/arch/arm/mach-socfpga/include/mach/init.h b/arch/arm/mach-socfpga/include/mach/init.h new file mode 100644 index 0000000000..c0e073ee13 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/init.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __MACH_INIT_H +#define __MACH_INIT_H + +void arria10_cpu_lowlevel_init(void); + +#endif |