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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2020-10-20 05:29:34 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-10-21 11:50:43 +0200 |
| commit | bde2b74852109b807ae0b8590389f4e221c7e621 (patch) | |
| tree | 3dde2d0d3f3cce2e0e35ab00d33a32df9593e4eb | |
| parent | b357c7088d3a3e47a8fdd2ea737bf80e0bfca3cd (diff) | |
| download | barebox-bde2b74852109b807ae0b8590389f4e221c7e621.tar.gz barebox-bde2b74852109b807ae0b8590389f4e221c7e621.tar.xz | |
Documentation: boards: stm32mp: search engine optimization
The vendor calls it STM32MP1. Have this name appear in the documentation
as well to be easier found during web search.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | Documentation/boards/stm32mp.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/boards/stm32mp.rst b/Documentation/boards/stm32mp.rst index a06578602d..87fff7d125 100644 --- a/Documentation/boards/stm32mp.rst +++ b/Documentation/boards/stm32mp.rst @@ -5,7 +5,7 @@ The STM32MP is a line of 32-bit ARM SoCs. They reuse peripherals of the STM32 line of microcontrollers and can have a STM32 MCU embedded as co-processor as well. -The boot process of the STM32MP SoC is a two step process. +The boot process of the STM32MP1 SoC is a two step process. The first stage boot loader (FSBL) is loaded by the ROM code into the built-in SYSRAM and executed. The FSBL sets up the SDRAM, install a secure monitor and then the second stage boot loader (SSBL) is loaded into DRAM. |