ARM64: Setup vectors in all lower execption levels

barebox on ARM64 often changes the exception level when loading a TF-A
or other secure monitor firmware. Make sure we have setup the vector
table in the exception level we then end up in.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 16 insertions, 9 deletions

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index e8475d2e47..baccf47808 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -194,15 +194,22 @@ extern unsigned long vectors;
 
 static int aarch64_init_vectors(void)
 {
-        unsigned int el;
-
-        el = current_el();
-        if (el == 1)
-                asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc");
-        else if (el == 2)
-                asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc");
-        else
-                asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc");
+	unsigned int el;
+
+	el = current_el();
+	switch (el) {
+	case 3:
+		asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	case 2:
+		asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	case 1:
+		asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc");
+		/* Fall through */
+	default:
+		break;
+	}
 
 	return 0;
 }