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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-12-16 21:19:10 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-08 16:28:48 +0100 |
| commit | e4cdb347a43618cb5395ab302322e4fb2a9a48ff (patch) | |
| tree | 680c7d89b56bf70d978b5abc8a065f3fdb9aa5cf | |
| parent | 90c2e60f3f2945aca47636059b142c147882f4ed (diff) | |
| download | barebox-e4cdb347a43618cb5395ab302322e4fb2a9a48ff.tar.gz barebox-e4cdb347a43618cb5395ab302322e4fb2a9a48ff.tar.xz | |
PCI: dwc: designware: Fix style errors in pcie-designware.c
Port of a Linux commit 314fc854f50317931fb4dfaab431695ab886e8de
No functional change. Fix all checkpatch warnings and check errors in
pcie-designware.c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | drivers/pci/pcie-designware.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index 59884d5145..f5a77ae155 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -39,13 +39,13 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_BAD_REGISTER_NUMBER; } - if (size == 4) + if (size == 4) { *val = readl(addr); - else if (size == 2) + } else if (size == 2) { *val = readw(addr); - else if (size == 1) + } else if (size == 1) { *val = readb(addr); - else { + } else { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -260,8 +260,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp) cfg_res = dev_get_resource_by_name(dev, IORESOURCE_MEM, "config"); if (cfg_res) { - pp->cfg0_size = resource_size(cfg_res)/2; - pp->cfg1_size = resource_size(cfg_res)/2; + pp->cfg0_size = resource_size(cfg_res) / 2; + pp->cfg1_size = resource_size(cfg_res) / 2; pp->cfg0_base = cfg_res->start; pp->cfg1_base = cfg_res->start + pp->cfg0_size; @@ -308,8 +308,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } if (restype == 0) { of_pci_range_to_resource(&range, np, &pp->cfg); - pp->cfg0_size = resource_size(&pp->cfg)/2; - pp->cfg1_size = resource_size(&pp->cfg)/2; + pp->cfg0_size = resource_size(&pp->cfg) / 2; + pp->cfg1_size = resource_size(&pp->cfg) / 2; pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->cfg0_size; @@ -351,7 +351,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) + u32 devfn, int where, int size, u32 *val) { int ret, type; u32 address, busdev, cfg_size; @@ -392,7 +392,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, } static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) + u32 devfn, int where, int size, u32 val) { int ret, type; u32 busdev, cfg_size; @@ -457,7 +457,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, } static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) + int size, u32 *val) { struct pcie_port *pp = host_to_pcie(bus->host); int ret; @@ -482,7 +482,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, } static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) + int where, int size, u32 val) { struct pcie_port *pp = host_to_pcie(bus->host); int ret; |