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| author | Lucas Stach <dev@lynxeye.de> | 2014-05-07 22:05:30 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-08 09:35:50 +0200 |
| commit | fb6e4db3ce9187b5da334d2ea911ac374c06fdf7 (patch) | |
| tree | fd2ef95e5cf23529e91f8e12c656ca637875cd75 | |
| parent | acbecd19879844ed0522f67f3c55cb0cd849623e (diff) | |
| download | barebox-fb6e4db3ce9187b5da334d2ea911ac374c06fdf7.tar.gz barebox-fb6e4db3ce9187b5da334d2ea911ac374c06fdf7.tar.xz | |
ARM: tegra30: ramp vdd_core to 1,2V
This isn't much different from the default 1,16V
and I haven't seen this make a difference on any
board, but it seems to be required for some T30 SKUs.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/nvidia-beaver/entry.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c index 25452a6a75..576fcb7a5b 100644 --- a/arch/arm/boards/nvidia-beaver/entry.c +++ b/arch/arm/boards/nvidia-beaver/entry.c @@ -30,6 +30,7 @@ ENTRY_FUNCTION(start_nvidia_beaver, r0, r1, r2) tegra_cpu_lowlevel_setup(); tegra_dvc_init(); + tegra30_tps62366a_ramp_vddcore(); tegra30_tps65911_cpu_rail_enable(); fdt = (uint32_t)__dtb_tegra30_beaver_start - get_runtime_offset(); diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h index f7f6328f65..32f10d7838 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h @@ -70,3 +70,21 @@ void tegra30_tps65911_cpu_rail_enable(void) tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES); tegra_ll_delay_usec(10 * 1000); } + +static inline __attribute__((always_inline)) +void tegra30_tps62366a_ramp_vddcore(void) +{ + tegra_dvc_write_addr(0xc0, 2); + /* set VDDcore to 1,2V */ + tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES); + tegra_ll_delay_usec(1000); +} + +static inline __attribute__((always_inline)) +void tegra30_tps62361b_ramp_vddcore(void) +{ + tegra_dvc_write_addr(0xc0, 2); + /* set VDDcore to 1,2V */ + tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES); + tegra_ll_delay_usec(1000); +} |