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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-06-11 11:33:34 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-06-11 11:33:34 +0200 |
commit | 543a7c8e10e0dbc1af8207e4a30e439c4c66c473 (patch) | |
tree | 05189f4b5380690ff8bb2aa5e1c2b5be3a5ce9d0 /Documentation/boards/imx | |
parent | cde5183f1ab7ba0936e84ec26dffc57a27879046 (diff) | |
parent | ead7521b93a3ece8e037090d03b7f9ac0c3e9026 (diff) | |
download | barebox-543a7c8e10e0dbc1af8207e4a30e439c4c66c473.tar.gz barebox-543a7c8e10e0dbc1af8207e4a30e439c4c66c473.tar.xz |
Merge branch 'for-next/imx'
Diffstat (limited to 'Documentation/boards/imx')
-rw-r--r-- | Documentation/boards/imx/digi-ccimx6ulsbcpro.rst | 26 | ||||
-rwxr-xr-x | Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh | 6 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg | 282 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx6-rdu2/readme.rst | 31 | ||||
-rwxr-xr-x | Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh | 6 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg | 143 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx7d-rpu2/readme.rst | 47 | ||||
-rwxr-xr-x | Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh | 6 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg | 99 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx8mq-dev/readme.rst | 4 | ||||
-rwxr-xr-x | Documentation/boards/imx/zii-vf610-dev/bootstrap.sh | 6 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-vf610-dev/openocd.cfg | 259 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-vf610-dev/readme.rst | 53 |
13 files changed, 918 insertions, 50 deletions
diff --git a/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst b/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst new file mode 100644 index 0000000000..bcb2ec2f07 --- /dev/null +++ b/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst @@ -0,0 +1,26 @@ +Digi CC-IMX6UL-SBC-PRO +====================== + +This board is based on the i.MX6UL SoC. + +The SBC Pro is shipped with: + + * 256MiB NAND flash + * 256MiB DDR3 SDRAM + +see https://www.digi.com/products/embedded-systems/single-board-computers/connectcore-for-i-mx6ul-sbc-pro +for more information. + +MAC addresses +------------- +The Digi modules save their MAC addresses not in the OCOTP nodes, but in the +U-Boot environment. It is advised to boot the board using the shipped U-Boot +Bootloader and to read out and save the MAC addresses for the board. +The environment variables which contain the addresses are `$ethaddr` and +`$eth1addr`. +The MAC addresses can than be persisted to the barebox environment by using + +.. code-block:: sh + + nv dev.eth0.ethaddr=<eth0addr> + nv dev.eth1.ethaddr=<eth1addr> diff --git a/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh b/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh new file mode 100755 index 0000000000..7342e890ec --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; reset init; start_barebox" diff --git a/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg b/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg new file mode 100644 index 0000000000..c5a65c44e6 --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg @@ -0,0 +1,282 @@ +# +# Board configuration file for the Zodiac RDU2 boards (6Q/6Q+ based) +# +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x003b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +# select JTAG +transport select jtag + +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# delay after SRST goes inactive +adapter_nsrst_delay 30 + +# board has i.MX6Q(+) with 4 Cortex-A9 cores +set CHIPNAME imx6q +set IMX_FLAVOUR q + +source [find target/imx6.cfg] +source [find mem_helper.tcl] + +proc disable_wdog { } { + echo "Bootstrap: Disabling SoC watchdog" + mwh phys 0x020bc000 0x30 +} + +proc ddr_init_imx6q { } { + echo "Bootstrap: Initializing DDR for i.MX6Q" + + mww phys 0x020e0798 0x000C0000 + mww phys 0x020e0758 0x00000000 + mww phys 0x020e0588 0x00000030 + mww phys 0x020e0594 0x00000030 + mww phys 0x020e056c 0x00000030 + mww phys 0x020e0578 0x00000030 + mww phys 0x020e074c 0x00000030 + mww phys 0x020e057c 0x00000030 + mww phys 0x020e058c 0x00000000 + mww phys 0x020e059c 0x00000030 + mww phys 0x020e05a0 0x00000030 + mww phys 0x020e078c 0x00000030 + mww phys 0x020e0750 0x00020000 + mww phys 0x020e05a8 0x00000028 + mww phys 0x020e05b0 0x00000028 + mww phys 0x020e0524 0x00000028 + mww phys 0x020e051c 0x00000028 + mww phys 0x020e0518 0x00000028 + mww phys 0x020e050c 0x00000028 + mww phys 0x020e05b8 0x00000028 + mww phys 0x020e05c0 0x00000028 + mww phys 0x020e0774 0x00020000 + mww phys 0x020e0784 0x00000028 + mww phys 0x020e0788 0x00000028 + mww phys 0x020e0794 0x00000028 + mww phys 0x020e079c 0x00000028 + mww phys 0x020e07a0 0x00000028 + mww phys 0x020e07a4 0x00000028 + mww phys 0x020e07a8 0x00000028 + mww phys 0x020e0748 0x00000028 + mww phys 0x020e05ac 0x00000028 + mww phys 0x020e05b4 0x00000028 + mww phys 0x020e0528 0x00000028 + mww phys 0x020e0520 0x00000028 + mww phys 0x020e0514 0x00000028 + mww phys 0x020e0510 0x00000028 + mww phys 0x020e05bc 0x00000028 + mww phys 0x020e05c4 0x00000028 + mww phys 0x021b0800 0xa1390003 + mww phys 0x021b080c 0x001F001F + mww phys 0x021b0810 0x001F001F + mww phys 0x021b480c 0x001F001F + mww phys 0x021b4810 0x001F001F + mww phys 0x021b083c 0x43260335 + mww phys 0x021b0840 0x031A030B + mww phys 0x021b483c 0x4323033B + mww phys 0x021b4840 0x0323026F + mww phys 0x021b0848 0x483D4545 + mww phys 0x021b4848 0x44433E48 + mww phys 0x021b0850 0x41444840 + mww phys 0x021b4850 0x4835483E + mww phys 0x021b081c 0x33333333 + mww phys 0x021b0820 0x33333333 + mww phys 0x021b0824 0x33333333 + mww phys 0x021b0828 0x33333333 + mww phys 0x021b481c 0x33333333 + mww phys 0x021b4820 0x33333333 + mww phys 0x021b4824 0x33333333 + mww phys 0x021b4828 0x33333333 + mww phys 0x021b08b8 0x00000800 + mww phys 0x021b48b8 0x00000800 + mww phys 0x021b0004 0x00020036 + mww phys 0x021b0008 0x09444040 + mww phys 0x021b000c 0x8A8F7955 + mww phys 0x021b0010 0xFF328F64 + mww phys 0x021b0014 0x01FF00DB + mww phys 0x021b0018 0x00001740 + mww phys 0x021b001c 0x00008000 + mww phys 0x021b002c 0x000026d2 + mww phys 0x021b0030 0x008F1023 + mww phys 0x021b0040 0x00000047 + mww phys 0x021b0000 0x841A0000 + mww phys 0x021b001c 0x04088032 + mww phys 0x021b001c 0x00008033 + mww phys 0x021b001c 0x00048031 + mww phys 0x021b001c 0x09408030 + mww phys 0x021b001c 0x04008040 + mww phys 0x021b0020 0x00005800 + mww phys 0x021b0818 0x00011117 + mww phys 0x021b4818 0x00011117 + mww phys 0x021b0004 0x00025576 + mww phys 0x021b0404 0x00011006 + mww phys 0x021b001c 0x00000000 + + # set the default clock gate to save power + mww phys 0x020c4068 0x00C03F3F + mww phys 0x020c406c 0x0030FC03 + mww phys 0x020c4070 0x0FFFC000 + mww phys 0x020c4074 0x3FF00000 + mww phys 0x020c4078 0xFFFFF300 + mww phys 0x020c407c 0x0F0000F3 + mww phys 0x020c4080 0x00000FFF + + # enable AXI cache for VDOA/VPU/IPU + mww phys 0x020e0010 0xF00000CF + # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 + mww phys 0x020e0018 0x007F007F + mww phys 0x020e001c 0x007F007F +} + +proc ddr_init_imx6qp { } { + echo "Bootstrap: Initializing DDR for i.MX6Q+" + + mww phys 0x020e0798 0x000C0000 + mww phys 0x020e0758 0x00000000 + mww phys 0x020e0588 0x00000030 + mww phys 0x020e0594 0x00000030 + mww phys 0x020e056c 0x00000030 + mww phys 0x020e0578 0x00000030 + mww phys 0x020e074c 0x00000030 + mww phys 0x020e057c 0x00000030 + mww phys 0x020e058c 0x00000000 + mww phys 0x020e059c 0x00000030 + mww phys 0x020e05a0 0x00000030 + mww phys 0x020e078c 0x00000030 + mww phys 0x020e0750 0x00020000 + mww phys 0x020e05a8 0x00000030 + mww phys 0x020e05b0 0x00000030 + mww phys 0x020e0524 0x00000030 + mww phys 0x020e051c 0x00000030 + mww phys 0x020e0518 0x00000030 + mww phys 0x020e050c 0x00000030 + mww phys 0x020e05b8 0x00000030 + mww phys 0x020e05c0 0x00000030 + mww phys 0x020e0774 0x00020000 + mww phys 0x020e0784 0x00000030 + mww phys 0x020e0788 0x00000030 + mww phys 0x020e0794 0x00000030 + mww phys 0x020e079c 0x00000030 + mww phys 0x020e07a0 0x00000030 + mww phys 0x020e07a4 0x00000030 + mww phys 0x020e07a8 0x00000030 + mww phys 0x020e0748 0x00000030 + mww phys 0x020e05ac 0x00000030 + mww phys 0x020e05b4 0x00000030 + mww phys 0x020e0528 0x00000030 + mww phys 0x020e0520 0x00000030 + mww phys 0x020e0514 0x00000030 + mww phys 0x020e0510 0x00000030 + mww phys 0x020e05bc 0x00000030 + mww phys 0x020e05c4 0x00000030 + mww phys 0x021b0800 0xa1390003 + mww phys 0x021b080c 0x001b001e + mww phys 0x021b0810 0x002e0029 + mww phys 0x021b480c 0x001b002a + mww phys 0x021b4810 0x0019002c + mww phys 0x021b083c 0x43240334 + mww phys 0x021b0840 0x0324031a + mww phys 0x021b483c 0x43340344 + mww phys 0x021b4840 0x03280276 + mww phys 0x021b0848 0x44383A3E + mww phys 0x021b4848 0x3C3C3846 + mww phys 0x021b0850 0x2e303230 + mww phys 0x021b4850 0x38283E34 + mww phys 0x021b081c 0x33333333 + mww phys 0x021b0820 0x33333333 + mww phys 0x021b0824 0x33333333 + mww phys 0x021b0828 0x33333333 + mww phys 0x021b481c 0x33333333 + mww phys 0x021b4820 0x33333333 + mww phys 0x021b4824 0x33333333 + mww phys 0x021b4828 0x33333333 + mww phys 0x021b08c0 0x24912492 + mww phys 0x021b48c0 0x24912492 + mww phys 0x021b08b8 0x00000800 + mww phys 0x021b48b8 0x00000800 + mww phys 0x021b0004 0x00020036 + mww phys 0x021b0008 0x09444040 + mww phys 0x021b000c 0x898E7955 + mww phys 0x021b0010 0xFF328F64 + mww phys 0x021b0014 0x01FF00DB + mww phys 0x021b0018 0x00001740 + mww phys 0x021b001c 0x00008000 + + mww phys 0x021b002c 0x000026d2 + mww phys 0x021b0030 0x008E1023 + mww phys 0x021b0040 0x00000047 + mww phys 0x021b0400 0x14420000 + mww phys 0x021b0000 0x841A0000 + mww phys 0x00bb0008 0x00000004 + mww phys 0x00bb000c 0x2891E41A + mww phys 0x00bb0038 0x00000564 + mww phys 0x00bb0014 0x00000040 + mww phys 0x00bb0028 0x00000020 + mww phys 0x00bb002c 0x00000020 + mww phys 0x021b001c 0x04088032 + mww phys 0x021b001c 0x00008033 + mww phys 0x021b001c 0x00048031 + mww phys 0x021b001c 0x09408030 + mww phys 0x021b001c 0x04008040 + mww phys 0x021b0020 0x00005800 + mww phys 0x021b0818 0x00011117 + mww phys 0x021b4818 0x00011117 + mww phys 0x021b0004 0x00025576 + mww phys 0x021b0404 0x00011006 + mww phys 0x021b001c 0x00000000 + + # set the default clock gate to save power + mww phys 0x020c4068 0x00C03F3F + mww phys 0x020c406c 0x0030FC03 + mww phys 0x020c4070 0x0FFFC000 + mww phys 0x020c4074 0x3FF00000 + mww phys 0x020c4078 0xFFFFF300 + mww phys 0x020c407c 0x0F0000F3 + mww phys 0x020c4080 0x00000FFF + + # enable AXI cache for VDOA/VPU/IPU + mww phys 0x020e0010 0xF00000CF + # set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 + mww phys 0x020e0018 0x77177717 + mww phys 0x020e001c 0x77177717 +} + +proc ddr_init { } { + # + # Steps to detect 6Q vs 6Q+ are borrowed from + # arch/arm/mach-imx/inclue/mach/imx6.h + # + set MX6_ANATOP_BASE_ADDR 0x020c8000 + set IMX6_ANATOP_SI_REV 0x260 + set si_rev [mrw [expr $MX6_ANATOP_BASE_ADDR + $IMX6_ANATOP_SI_REV]] + set rev_major [expr ($si_rev >> 8) & 0xF] + + if { $rev_major >= 1 } { + ddr_init_imx6qp + } else { + ddr_init_imx6q + } +} + +proc start_barebox { } { + set MX6_DDR_BASE_ADDR 0x10000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-imx6-rdu2.img $MX6_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $MX6_DDR_BASE_ADDR] + resume $MX6_DDR_BASE_ADDR +} + +proc board_init { } { + disable_wdog + ddr_init +} + +${_TARGETNAME}.0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-imx6-rdu2/readme.rst b/Documentation/boards/imx/zii-imx6-rdu2/readme.rst new file mode 100644 index 0000000000..4694f2e30e --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/readme.rst @@ -0,0 +1,31 @@ +ZII i.MX6 RDU2 Boards +===================== + +Building Barebox +---------------- + +To build Barebox for ZII RDU2 boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> imx_v7_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh b/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh new file mode 100755 index 0000000000..49bab03200 --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; safe_reset; start_barebox;" diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg b/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg new file mode 100644 index 0000000000..675832b7cf --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg @@ -0,0 +1,143 @@ +# +# Board configuration file for the Zodiac RPU2 board +# + +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x007b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +transport select jtag + +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# need at least 100ms delay after SRST release for JTAG +adapter_nsrst_delay 100 + +# source the target file +source [find target/imx7.cfg] +source [find mem_helper.tcl] + +# function to disable the on-chip watchdog +proc disable_wdog { } { + echo "Bootstrap: Disabling SoC watchdog" + mwh phys 0x30280008 0x00 +} + +set ddr_init_failed 0 + +proc check_bits_set_32 { addr mask } { + while { [expr [mrw $addr] & $mask == 0] } { } +} + +proc ddr_init { } { + echo "Bootstrap: Initializing DDR" + + mww phys 0x30340004 0x4F400005 + # Clear then set bit30 to ensure exit from DDR retention + mww phys 0x30360388 0x40000000 + mww phys 0x30360384 0x40000000 + + mww phys 0x30391000 0x00000002 + mww phys 0x307a0000 0x01040001 + mww phys 0x307a01a0 0x80400003 + mww phys 0x307a01a4 0x00100020 + mww phys 0x307a01a8 0x80100004 + mww phys 0x307a0064 0x00400046 + mww phys 0x307a0490 0x00000001 + mww phys 0x307a00d0 0x00020083 + mww phys 0x307a00d4 0x00690000 + mww phys 0x307a00dc 0x09300004 + mww phys 0x307a00e0 0x04080000 + mww phys 0x307a00e4 0x00100004 + mww phys 0x307a00f4 0x0000033f + mww phys 0x307a0100 0x09081109 + mww phys 0x307a0104 0x0007020d + mww phys 0x307a0108 0x03040407 + mww phys 0x307a010c 0x00002006 + mww phys 0x307a0110 0x04020205 + mww phys 0x307a0114 0x03030202 + mww phys 0x307a0120 0x00000803 + mww phys 0x307a0180 0x00800020 + mww phys 0x307a0184 0x02000100 + mww phys 0x307a0190 0x02098204 + mww phys 0x307a0194 0x00030303 + mww phys 0x307a0200 0x00000016 + mww phys 0x307a0204 0x00171717 + mww phys 0x307a0214 0x04040404 + mww phys 0x307a0218 0x0f040404 + mww phys 0x307a0240 0x06000604 + mww phys 0x307a0244 0x00000001 + mww phys 0x30391000 0x00000000 + mww phys 0x30790000 0x17420f40 + mww phys 0x30790004 0x10210100 + mww phys 0x30790010 0x00060807 + mww phys 0x307900b0 0x1010007e + mww phys 0x3079009c 0x00000d6e + mww phys 0x30790020 0x08080808 + mww phys 0x30790030 0x08080808 + mww phys 0x30790050 0x01000010 + mww phys 0x30790050 0x00000010 + + mww phys 0x307900c0 0x0e407304 + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e447306 + + check_bits_set_32 0x307900c4 0x1 + + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e407304 + + mww phys 0x30384130 0x00000000 + mww phys 0x30340020 0x00000178 + mww phys 0x30384130 0x00000002 + mww phys 0x30790018 0x0000000f + + check_bits_set_32 0x307900c4 0x1 +} + +# This function applies the initial configuration after a "reset init" +# command +proc board_init { } { + global ddr_init_failed + disable_wdog + + if {[catch {ddr_init} errmsg]} { + set ddr_init_failed 1 + } else { + set ddr_init_failed 0 + } +} + +proc safe_reset {} { + global ddr_init_failed + + set status 5 + while { $status != 0 } { + reset init + if { $ddr_init_failed == 1 } { + incr status -1 + } else { + set status 0 + } + } +} + +proc start_barebox { } { + set MX7_DDR_BASE_ADDR 0x80000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-imx7d-rpu2.img $MX7_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $MX7_DDR_BASE_ADDR] + resume $MX7_DDR_BASE_ADDR +} + +# hook the init function into the reset-init event +${_TARGETNAME}.0 configure -event reset-init { board_init } + diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst b/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst new file mode 100644 index 0000000000..dd984ac176 --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst @@ -0,0 +1,47 @@ +ZII i.MX7D Based Boards +======================= + +Building Barebox +---------------- + +To build Barebox for ZII i.MX7 based boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> imx_v7_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh + + +Disabling DSA in Embedeed Switch +-------------------------------- + +Booting the Linux kernel that the device ships with will re-configure the on-board +switch into DSA mode, which would make the Ethernet connection unusable in +Barebox. To undo that and re-configure the switch into dumb/pass-through +mode, do the following: + +.. code-block:: sh + + memset -b -d /dev/switch-eeprom 0x00 0xff 4 + +Once that is done, power cycling the device should force the switch to +re-read the EEPROM and reconfigure itself. diff --git a/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh b/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh new file mode 100755 index 0000000000..7342e890ec --- /dev/null +++ b/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; reset init; start_barebox" diff --git a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg index 31f94227e6..cc0bec6b74 100644 --- a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg +++ b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg @@ -1,3 +1,7 @@ +# +# Board configuration file for the Zodiac RDU3 boards +# + interface ftdi ftdi_vid_pid 0x0403 0x6011 @@ -5,13 +9,11 @@ ftdi_layout_init 0x0038 0x003b ftdi_layout_signal nSRST -data 0x0010 ftdi_layout_signal LED -data 0x0020 -# Board has a standard ARM-20 JTAG connector with -# nSRST available. -reset_config srst_only srst_push_pull connect_deassert_srst - # select JTAG transport select jtag +reset_config srst_only srst_push_pull connect_deassert_srst + # set a slow default JTAG clock, can be overridden later adapter_khz 1000 @@ -27,60 +29,61 @@ source [find target/imx8m.cfg] source [find mem_helper.tcl] proc ddr_init { } { - # - # We use the same start address as is configured in our i.MX boot - # header (address originally taken from U-Boot). - # - set IMX8MQ_TCM_BASE_ADDR 0x007e1000 - set IMX8MQ_TCM_MAX_SIZE 0x3f000 - # - # Header word at offset 0x28 is not used on AArch64 and is just - # filled with placeholder value 0xffff_ffff, see - # arch/arm/include/asm/barebox-arm-head.h for more details - # - set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28] - set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef - set RDU3_TCM_MAGIC_REPLY 0xbaadf00d - - echo "==== Uploading DDR helper ====" - - halt - load_image images/start_zii_imx8mq_dev.pblb \ - $IMX8MQ_TCM_BASE_ADDR \ + echo "Bootstrap: Initializing DDR" + # + # We use the same start address as is configured in our i.MX boot + # header (address originally taken from U-Boot). + # + set IMX8MQ_TCM_BASE_ADDR 0x007e1000 + set IMX8MQ_TCM_MAX_SIZE 0x3f000 + # + # Header word at offset 0x28 is not used on AArch64 and is just + # filled with placeholder value 0xffff_ffff, see + # arch/arm/include/asm/barebox-arm-head.h for more details + # + set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28] + set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef + set RDU3_TCM_MAGIC_REPLY 0xbaadf00d + + echo "Bootstrap: Uploading DDR helper" + + halt + load_image images/start_zii_imx8mq_dev.pblb \ + $IMX8MQ_TCM_BASE_ADDR \ bin \ $IMX8MQ_TCM_BASE_ADDR \ $IMX8MQ_TCM_MAX_SIZE - echo "==== Running DDR helper ====" + echo "Bootstrap: Running DDR helper" - mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST - resume $IMX8MQ_TCM_BASE_ADDR + mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST + resume $IMX8MQ_TCM_BASE_ADDR - echo "==== Waiting for DDR helper to finish ====" + echo "Bootstrap: Waiting for DDR helper to finish" - if {[catch {wait_halt} errmsg] || - [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} { - echo "==== DDR initialization FAILED ====" - } else { - echo "==== DDR is ready ====" - } + if {[catch {wait_halt} errmsg] || + [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} { + echo "Bootstrap: DDR initialization FAILED" + } else { + echo "Bootstrap: DDR is ready" + } } proc start_barebox {} { - # - # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order - # to be able to initialize ATF firmware since that's where it - # expects entry point to BL33 would be - # - set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 - - echo "==== Starting Barebox ====" - load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin - resume $MX8MQ_ATF_BL33_BASE_ADDR + # + # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order + # to be able to initialize ATF firmware since that's where it + # expects entry point to BL33 would be + # + set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 + echo "Bootstrap: Loading Barebox" + load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin + echo [format "Bootstrap: Jumping to 0x%08x" $MX8MQ_ATF_BL33_BASE_ADDR] + resume $MX8MQ_ATF_BL33_BASE_ADDR } -# proc board_init { } { -# ddr_init -# } +proc board_init { } { + ddr_init +} -# ${_TARGETNAME}.0 configure -event reset-init { board_init } +${_TARGETNAME}.0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst index dc031e4af4..363e00e6ca 100644 --- a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst +++ b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst @@ -20,5 +20,5 @@ follows: .. code-block:: sh - cd barebox - openocd -f Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg --command "init; ddr_init; start_barebox" + cd barebox + Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh diff --git a/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh b/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh new file mode 100755 index 0000000000..49bab03200 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; safe_reset; start_barebox;" diff --git a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg new file mode 100644 index 0000000000..509f9e33c2 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg @@ -0,0 +1,259 @@ +# +# Board configuration file for the Zodiac VF6xx based boards +# + +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x007b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +# select JTAG +transport select jtag + +# Board has a standard ARM-20 JTAG connector with +# nSRST available. +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# Source generic VF6xx target configuration +source [find target/vybrid_vf6xx.cfg] +source [find mem_helper.tcl] + +set ddr_init_failed 0 + +proc check_bits_set_32 { addr mask } { + while { [expr [mrw $addr] & $mask == 0] } { } +} + +proc ddr_init { } { + echo "Bootstrap: Initializing DDR" + + mww phys 0x40048220 0x00000180 + mww phys 0x40048224 0x00000180 + mww phys 0x40048228 0x00000180 + mww phys 0x4004822c 0x00000180 + mww phys 0x40048230 0x00000180 + mww phys 0x40048234 0x00000180 + mww phys 0x40048238 0x00000180 + mww phys 0x4004823c 0x00000180 + mww phys 0x40048240 0x00000180 + mww phys 0x40048244 0x00000180 + mww phys 0x40048248 0x00000180 + mww phys 0x4004824c 0x00000180 + mww phys 0x40048250 0x00000180 + mww phys 0x40048254 0x00000180 + mww phys 0x40048258 0x00000180 + mww phys 0x4004825c 0x00000180 + mww phys 0x40048260 0x00000180 + mww phys 0x40048264 0x00000180 + mww phys 0x40048268 0x00000180 + mww phys 0x4004826c 0x00000180 + mww phys 0x40048270 0x00000180 + mww phys 0x40048274 0x00010180 + mww phys 0x40048278 0x00000180 + mww phys 0x4004827c 0x00000180 + mww phys 0x40048280 0x00000180 + mww phys 0x40048284 0x00000180 + mww phys 0x40048288 0x00000180 + mww phys 0x4004828c 0x00000180 + mww phys 0x40048290 0x00000180 + mww phys 0x40048294 0x00000180 + mww phys 0x40048298 0x00000180 + mww phys 0x4004829c 0x00000180 + mww phys 0x400482a0 0x00000180 + mww phys 0x400482a4 0x00000180 + mww phys 0x400482a8 0x00000180 + mww phys 0x400482ac 0x00000180 + mww phys 0x400482b0 0x00000180 + mww phys 0x400482b4 0x00000180 + mww phys 0x400482b8 0x00000180 + mww phys 0x400482bc 0x00000180 + mww phys 0x400482c0 0x00000180 + mww phys 0x400482c4 0x00010180 + mww phys 0x400482c8 0x00010180 + mww phys 0x400482cc 0x00000180 + mww phys 0x400482d0 0x00000180 + mww phys 0x400482d4 0x00000180 + mww phys 0x400482d8 0x00000180 + mww phys 0x4004821c 0x00000180 + + mww phys 0x400482dc 0x00000180 + mww phys 0x400482e0 0x00000180 + + mww phys 0x400ae000 0x00000600 + mww phys 0x400ae008 0x00000005 + mww phys 0x400ae028 0x00013880 + mww phys 0x400ae02c 0x00030d40 + mww phys 0x400ae030 0x0000050c + mww phys 0x400ae034 0x15040400 + mww phys 0x400ae038 0x1406040f + mww phys 0x400ae040 0x04040000 + mww phys 0x400ae044 0x006db00c + mww phys 0x400ae048 0x00000403 + mww phys 0x400ae050 0x01000000 + mww phys 0x400ae054 0x00060001 + mww phys 0x400ae058 0x000c0000 + mww phys 0x400ae05c 0x03000200 + mww phys 0x400ae060 0x00000006 + mww phys 0x400ae064 0x00010000 + mww phys 0x400ae068 0x0c300068 + mww phys 0x400ae070 0x00000000 + mww phys 0x400ae074 0x00000003 + mww phys 0x400ae078 0x0000000a + mww phys 0x400ae07c 0x006c0200 + mww phys 0x400ae084 0x00010000 + mww phys 0x400ae088 0x00050500 + mww phys 0x400ae098 0x00000000 + mww phys 0x400ae09c 0x04001002 + mww phys 0x400ae0a4 0x00000001 + mww phys 0x400ae0c0 0x00460420 + mww phys 0x400ae108 0x01000200 + mww phys 0x400ae10c 0x00000040 + mww phys 0x400ae114 0x00000200 + mww phys 0x400ae118 0x00000040 + mww phys 0x400ae120 0x00000000 + mww phys 0x400ae124 0x0a010100 + mww phys 0x400ae128 0x01014040 + mww phys 0x400ae12c 0x01010101 + mww phys 0x400ae130 0x03030100 + mww phys 0x400ae134 0x01000101 + mww phys 0x400ae138 0x0700000c + mww phys 0x400ae13c 0x00000000 + mww phys 0x400ae148 0x10000000 + mww phys 0x400ae15c 0x01000000 + mww phys 0x400ae160 0x00040000 + mww phys 0x400ae164 0x00000002 + mww phys 0x400ae16c 0x00020000 + mww phys 0x400ae180 0x00002819 + mww phys 0x400ae184 0x01000000 + mww phys 0x400ae188 0x00000000 + mww phys 0x400ae18c 0x00000000 + mww phys 0x400ae198 0x00010100 + mww phys 0x400ae1a4 0x00000000 + mww phys 0x400ae1a8 0x00000004 + mww phys 0x400ae1b8 0x00040000 + mww phys 0x400ae1d4 0x00000000 + mww phys 0x400ae1d8 0x01010000 + mww phys 0x400ae1e0 0x02020000 + mww phys 0x400ae1e4 0x00000202 + mww phys 0x400ae1e8 0x01010064 + mww phys 0x400ae1ec 0x00010101 + mww phys 0x400ae1f0 0x00000064 + mww phys 0x400ae1f8 0x00000800 + mww phys 0x400ae210 0x00000506 + mww phys 0x400ae224 0x00020000 + mww phys 0x400ae228 0x01000100 + mww phys 0x400ae22c 0x04070303 + mww phys 0x400ae230 0x00000040 + mww phys 0x400ae23c 0x06000080 + mww phys 0x400ae240 0x04070303 + mww phys 0x400ae244 0x00000040 + mww phys 0x400ae248 0x00000040 + mww phys 0x400ae24c 0x000f0000 + mww phys 0x400ae250 0x000f0000 + mww phys 0x400ae25c 0x00000101 + mww phys 0x400ae268 0x682c4000 + mww phys 0x400ae26c 0x00000081 + mww phys 0x400ae278 0x00000006 + mww phys 0x400ae284 0x00010606 + + mww phys 0x400ae400 0x00002613 + mww phys 0x400ae440 0x00002613 + mww phys 0x400ae404 0x00002615 + mww phys 0x400ae444 0x00002615 + mww phys 0x400ae408 0x00210000 + mww phys 0x400ae448 0x00210000 + mww phys 0x400ae488 0x00210000 + mww phys 0x400ae40c 0x0001012a + mww phys 0x400ae44c 0x0001012a + mww phys 0x400ae48c 0x0001012a + mww phys 0x400ae410 0x00002400 + mww phys 0x400ae450 0x00002400 + mww phys 0x400ae490 0x00002400 + mww phys 0x400ae4c4 0x00000000 + mww phys 0x400ae4c8 0x00001100 + mww phys 0x400ae4d0 0x00010101 + + mww phys 0x400ae000 0x00000601 +} + +proc clock_init { } { + echo "Bootstrap: Initializing clocks" + # + # This code assumes that debugger would be unable to prevent + # MaskROM initialization code from running before halting the + # processor. TODO: Port the initial clock settings as + # specified in TRM + # + # Ungate all of the peripheral clocks + # + mww phys 0x4006b040 0xffffffff + mww phys 0x4006b044 0xffffffff + mww phys 0x4006b048 0xffffffff + mww phys 0x4006b04c 0xffffffff + mww phys 0x4006b050 0xffffffff + mww phys 0x4006b058 0xffffffff + mww phys 0x4006b05c 0xffffffff + mww phys 0x4006b060 0xffffffff + mww phys 0x4006b064 0xffffffff + mww phys 0x4006b068 0xffffffff + mww phys 0x4006b06c 0xffffffff + # + # There are two possibilities for clocking DDR controller: ARM + # Cortex A core clock or PLL2 PFD4. Mask ROM configures ARM + # Cortex A clock to run at 264Mhz which is not sufficient to + # run DDR (it requres 300Mhz minimum) so instead we configure + # PLL2 PFD4 as a DDR clock + # + # PLL2 on, Fout = Fin * 22 + # + mww phys 0x40050030 0x00002001 + + check_bits_set_32 0x40050030 0x80000000 + + mww phys 0x4006b008 [expr [mrw 0x4006b008] & ~0x00000040] + mww phys 0x4006b008 [expr [mrw 0x4006b008] | 0x00002000] +} + +# This function applies the initial configuration after a "reset init" +# command +proc board_init { } { + global ddr_init_failed + clock_init + + if {[catch {ddr_init} errmsg]} { + set ddr_init_failed 1 + } else { + set ddr_init_failed 0 + } +} + +proc safe_reset {} { + global ddr_init_failed + + set status 5 + while { $status != 0 } { + reset init + if { $ddr_init_failed == 1 } { + incr status -1 + } else { + set status 0 + } + } +} + +proc start_barebox { } { + set VF610_DDR_BASE_ADDR 0x80000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-vf610-dev.img $VF610_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $VF610_DDR_BASE_ADDR] + resume $VF610_DDR_BASE_ADDR +} + +${_TARGETNAME}0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-vf610-dev/readme.rst b/Documentation/boards/imx/zii-vf610-dev/readme.rst new file mode 100644 index 0000000000..08ae0e0e67 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/readme.rst @@ -0,0 +1,53 @@ +ZII VF610 Based Boards +====================== + +Building Barebox +---------------- + +To build Barebox for ZII VF610 based boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> zii_vf610_dev_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-vf610-dev/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-vf610-dev/bootstrap.sh + +Writing Barebox to NVM +---------------------- + +With exception of Dev boards, all of ZII's VF610 based boards should +come with eMMC. To permanently write Barebox to it do: + +.. code-block:: sh + + barebox_update -t eMMC -y barebox.img + +This should also automatically configure your board to boot that +image. Note that the original ZII stack's bootloader in eMMC should be +left intact. Barebox is configured to be programmed to one of the MMC boot +partitions, whereas the original bootloader is located in user partition. + +To restore the board to booting using the original bootloader do: + +.. code-block:: sh + + detect mmc0 + mmc0.boot=disabled |