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authorRoland Hieber <rohieb@rohieb.name>2018-06-12 00:02:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-06-13 09:15:53 +0200
commit9088663afaa6f13589be2ac8272d72adfd720ae3 (patch)
treef0e77657642f3c038a4fd166b9aa33b6ec9ce060 /Documentation/boards/imx
parenta2631ff3f657c38b8aa2df269bd222217199c5db (diff)
downloadbarebox-9088663afaa6f13589be2ac8272d72adfd720ae3.tar.gz
barebox-9088663afaa6f13589be2ac8272d72adfd720ae3.tar.xz
doc: boards: element14 WaRP7: fix header level and nested list
Signed-off-by: Roland Hieber <rohieb@rohieb.name> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation/boards/imx')
-rw-r--r--Documentation/boards/imx/element14-warp7.rst5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/boards/imx/element14-warp7.rst b/Documentation/boards/imx/element14-warp7.rst
index df14f84dc4..830a2fb55b 100644
--- a/Documentation/boards/imx/element14-warp7.rst
+++ b/Documentation/boards/imx/element14-warp7.rst
@@ -4,15 +4,16 @@ element14 WaRP7
This CPU card is based on an NXP i.MX7S SoC.
Supported hardware
-==================
+------------------
- NXP PMIC PFUZE3000
- Kingston 08EMCP04-EL3AV100 eMCP (eMMC and LPDDR3 memory in one package)
+
- 8 GiB eMMC Triple-Level cell NAND flash, eMMC standard 5.0 (HS400)
- 512 MiB LPDDR3 SDRAM starting at address 0x80000000
Bootstrapping barebox
-=====================
+---------------------
The device boots in internal boot mode from eMMC and is shipped with a
vendor modified u-boot imximage.